1 /* RISC-V ISA constants */ 2 3 #ifndef TARGET_RISCV_CPU_BITS_H 4 #define TARGET_RISCV_CPU_BITS_H 5 6 #define get_field(reg, mask) (((reg) & \ 7 (uint64_t)(mask)) / ((mask) & ~((mask) << 1))) 8 #define set_field(reg, mask, val) (((reg) & ~(uint64_t)(mask)) | \ 9 (((uint64_t)(val) * ((mask) & ~((mask) << 1))) & \ 10 (uint64_t)(mask))) 11 12 /* Floating point round mode */ 13 #define FSR_RD_SHIFT 5 14 #define FSR_RD (0x7 << FSR_RD_SHIFT) 15 16 /* Floating point accrued exception flags */ 17 #define FPEXC_NX 0x01 18 #define FPEXC_UF 0x02 19 #define FPEXC_OF 0x04 20 #define FPEXC_DZ 0x08 21 #define FPEXC_NV 0x10 22 23 /* Floating point status register bits */ 24 #define FSR_AEXC_SHIFT 0 25 #define FSR_NVA (FPEXC_NV << FSR_AEXC_SHIFT) 26 #define FSR_OFA (FPEXC_OF << FSR_AEXC_SHIFT) 27 #define FSR_UFA (FPEXC_UF << FSR_AEXC_SHIFT) 28 #define FSR_DZA (FPEXC_DZ << FSR_AEXC_SHIFT) 29 #define FSR_NXA (FPEXC_NX << FSR_AEXC_SHIFT) 30 #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA) 31 32 /* Vector Fixed-Point round model */ 33 #define FSR_VXRM_SHIFT 9 34 #define FSR_VXRM (0x3 << FSR_VXRM_SHIFT) 35 36 /* Vector Fixed-Point saturation flag */ 37 #define FSR_VXSAT_SHIFT 8 38 #define FSR_VXSAT (0x1 << FSR_VXSAT_SHIFT) 39 40 /* Control and Status Registers */ 41 42 /* User Trap Setup */ 43 #define CSR_USTATUS 0x000 44 #define CSR_UIE 0x004 45 #define CSR_UTVEC 0x005 46 47 /* User Trap Handling */ 48 #define CSR_USCRATCH 0x040 49 #define CSR_UEPC 0x041 50 #define CSR_UCAUSE 0x042 51 #define CSR_UTVAL 0x043 52 #define CSR_UIP 0x044 53 54 /* User Floating-Point CSRs */ 55 #define CSR_FFLAGS 0x001 56 #define CSR_FRM 0x002 57 #define CSR_FCSR 0x003 58 59 /* User Vector CSRs */ 60 #define CSR_VSTART 0x008 61 #define CSR_VXSAT 0x009 62 #define CSR_VXRM 0x00a 63 #define CSR_VCSR 0x00f 64 #define CSR_VL 0xc20 65 #define CSR_VTYPE 0xc21 66 #define CSR_VLENB 0xc22 67 68 /* VCSR fields */ 69 #define VCSR_VXSAT_SHIFT 0 70 #define VCSR_VXSAT (0x1 << VCSR_VXSAT_SHIFT) 71 #define VCSR_VXRM_SHIFT 1 72 #define VCSR_VXRM (0x3 << VCSR_VXRM_SHIFT) 73 74 /* User Timers and Counters */ 75 #define CSR_CYCLE 0xc00 76 #define CSR_TIME 0xc01 77 #define CSR_INSTRET 0xc02 78 #define CSR_HPMCOUNTER3 0xc03 79 #define CSR_HPMCOUNTER4 0xc04 80 #define CSR_HPMCOUNTER5 0xc05 81 #define CSR_HPMCOUNTER6 0xc06 82 #define CSR_HPMCOUNTER7 0xc07 83 #define CSR_HPMCOUNTER8 0xc08 84 #define CSR_HPMCOUNTER9 0xc09 85 #define CSR_HPMCOUNTER10 0xc0a 86 #define CSR_HPMCOUNTER11 0xc0b 87 #define CSR_HPMCOUNTER12 0xc0c 88 #define CSR_HPMCOUNTER13 0xc0d 89 #define CSR_HPMCOUNTER14 0xc0e 90 #define CSR_HPMCOUNTER15 0xc0f 91 #define CSR_HPMCOUNTER16 0xc10 92 #define CSR_HPMCOUNTER17 0xc11 93 #define CSR_HPMCOUNTER18 0xc12 94 #define CSR_HPMCOUNTER19 0xc13 95 #define CSR_HPMCOUNTER20 0xc14 96 #define CSR_HPMCOUNTER21 0xc15 97 #define CSR_HPMCOUNTER22 0xc16 98 #define CSR_HPMCOUNTER23 0xc17 99 #define CSR_HPMCOUNTER24 0xc18 100 #define CSR_HPMCOUNTER25 0xc19 101 #define CSR_HPMCOUNTER26 0xc1a 102 #define CSR_HPMCOUNTER27 0xc1b 103 #define CSR_HPMCOUNTER28 0xc1c 104 #define CSR_HPMCOUNTER29 0xc1d 105 #define CSR_HPMCOUNTER30 0xc1e 106 #define CSR_HPMCOUNTER31 0xc1f 107 #define CSR_CYCLEH 0xc80 108 #define CSR_TIMEH 0xc81 109 #define CSR_INSTRETH 0xc82 110 #define CSR_HPMCOUNTER3H 0xc83 111 #define CSR_HPMCOUNTER4H 0xc84 112 #define CSR_HPMCOUNTER5H 0xc85 113 #define CSR_HPMCOUNTER6H 0xc86 114 #define CSR_HPMCOUNTER7H 0xc87 115 #define CSR_HPMCOUNTER8H 0xc88 116 #define CSR_HPMCOUNTER9H 0xc89 117 #define CSR_HPMCOUNTER10H 0xc8a 118 #define CSR_HPMCOUNTER11H 0xc8b 119 #define CSR_HPMCOUNTER12H 0xc8c 120 #define CSR_HPMCOUNTER13H 0xc8d 121 #define CSR_HPMCOUNTER14H 0xc8e 122 #define CSR_HPMCOUNTER15H 0xc8f 123 #define CSR_HPMCOUNTER16H 0xc90 124 #define CSR_HPMCOUNTER17H 0xc91 125 #define CSR_HPMCOUNTER18H 0xc92 126 #define CSR_HPMCOUNTER19H 0xc93 127 #define CSR_HPMCOUNTER20H 0xc94 128 #define CSR_HPMCOUNTER21H 0xc95 129 #define CSR_HPMCOUNTER22H 0xc96 130 #define CSR_HPMCOUNTER23H 0xc97 131 #define CSR_HPMCOUNTER24H 0xc98 132 #define CSR_HPMCOUNTER25H 0xc99 133 #define CSR_HPMCOUNTER26H 0xc9a 134 #define CSR_HPMCOUNTER27H 0xc9b 135 #define CSR_HPMCOUNTER28H 0xc9c 136 #define CSR_HPMCOUNTER29H 0xc9d 137 #define CSR_HPMCOUNTER30H 0xc9e 138 #define CSR_HPMCOUNTER31H 0xc9f 139 140 /* Machine Timers and Counters */ 141 #define CSR_MCYCLE 0xb00 142 #define CSR_MINSTRET 0xb02 143 #define CSR_MCYCLEH 0xb80 144 #define CSR_MINSTRETH 0xb82 145 146 /* Machine Information Registers */ 147 #define CSR_MVENDORID 0xf11 148 #define CSR_MARCHID 0xf12 149 #define CSR_MIMPID 0xf13 150 #define CSR_MHARTID 0xf14 151 #define CSR_MCONFIGPTR 0xf15 152 153 /* Machine Trap Setup */ 154 #define CSR_MSTATUS 0x300 155 #define CSR_MISA 0x301 156 #define CSR_MEDELEG 0x302 157 #define CSR_MIDELEG 0x303 158 #define CSR_MIE 0x304 159 #define CSR_MTVEC 0x305 160 #define CSR_MCOUNTEREN 0x306 161 162 /* 32-bit only */ 163 #define CSR_MSTATUSH 0x310 164 165 /* Machine Trap Handling */ 166 #define CSR_MSCRATCH 0x340 167 #define CSR_MEPC 0x341 168 #define CSR_MCAUSE 0x342 169 #define CSR_MTVAL 0x343 170 #define CSR_MIP 0x344 171 172 /* Machine-Level Window to Indirectly Accessed Registers (AIA) */ 173 #define CSR_MISELECT 0x350 174 #define CSR_MIREG 0x351 175 176 /* Machine-Level Interrupts (AIA) */ 177 #define CSR_MTOPEI 0x35c 178 #define CSR_MTOPI 0xfb0 179 180 /* Virtual Interrupts for Supervisor Level (AIA) */ 181 #define CSR_MVIEN 0x308 182 #define CSR_MVIP 0x309 183 184 /* Machine-Level High-Half CSRs (AIA) */ 185 #define CSR_MIDELEGH 0x313 186 #define CSR_MIEH 0x314 187 #define CSR_MVIENH 0x318 188 #define CSR_MVIPH 0x319 189 #define CSR_MIPH 0x354 190 191 /* Supervisor Trap Setup */ 192 #define CSR_SSTATUS 0x100 193 #define CSR_SEDELEG 0x102 194 #define CSR_SIDELEG 0x103 195 #define CSR_SIE 0x104 196 #define CSR_STVEC 0x105 197 #define CSR_SCOUNTEREN 0x106 198 199 /* Supervisor Configuration CSRs */ 200 #define CSR_SENVCFG 0x10A 201 202 /* Supervisor Trap Handling */ 203 #define CSR_SSCRATCH 0x140 204 #define CSR_SEPC 0x141 205 #define CSR_SCAUSE 0x142 206 #define CSR_STVAL 0x143 207 #define CSR_SIP 0x144 208 209 /* Sstc supervisor CSRs */ 210 #define CSR_STIMECMP 0x14D 211 #define CSR_STIMECMPH 0x15D 212 213 /* Supervisor Protection and Translation */ 214 #define CSR_SPTBR 0x180 215 #define CSR_SATP 0x180 216 217 /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */ 218 #define CSR_SISELECT 0x150 219 #define CSR_SIREG 0x151 220 221 /* Supervisor-Level Interrupts (AIA) */ 222 #define CSR_STOPEI 0x15c 223 #define CSR_STOPI 0xdb0 224 225 /* Supervisor-Level High-Half CSRs (AIA) */ 226 #define CSR_SIEH 0x114 227 #define CSR_SIPH 0x154 228 229 /* Hpervisor CSRs */ 230 #define CSR_HSTATUS 0x600 231 #define CSR_HEDELEG 0x602 232 #define CSR_HIDELEG 0x603 233 #define CSR_HIE 0x604 234 #define CSR_HCOUNTEREN 0x606 235 #define CSR_HGEIE 0x607 236 #define CSR_HTVAL 0x643 237 #define CSR_HVIP 0x645 238 #define CSR_HIP 0x644 239 #define CSR_HTINST 0x64A 240 #define CSR_HGEIP 0xE12 241 #define CSR_HGATP 0x680 242 #define CSR_HTIMEDELTA 0x605 243 #define CSR_HTIMEDELTAH 0x615 244 245 /* Hypervisor Configuration CSRs */ 246 #define CSR_HENVCFG 0x60A 247 #define CSR_HENVCFGH 0x61A 248 249 /* Virtual CSRs */ 250 #define CSR_VSSTATUS 0x200 251 #define CSR_VSIE 0x204 252 #define CSR_VSTVEC 0x205 253 #define CSR_VSSCRATCH 0x240 254 #define CSR_VSEPC 0x241 255 #define CSR_VSCAUSE 0x242 256 #define CSR_VSTVAL 0x243 257 #define CSR_VSIP 0x244 258 #define CSR_VSATP 0x280 259 260 #define CSR_MTINST 0x34a 261 #define CSR_MTVAL2 0x34b 262 263 /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */ 264 #define CSR_HVIEN 0x608 265 #define CSR_HVICTL 0x609 266 #define CSR_HVIPRIO1 0x646 267 #define CSR_HVIPRIO2 0x647 268 269 /* VS-Level Window to Indirectly Accessed Registers (H-extension with AIA) */ 270 #define CSR_VSISELECT 0x250 271 #define CSR_VSIREG 0x251 272 273 /* VS-Level Interrupts (H-extension with AIA) */ 274 #define CSR_VSTOPEI 0x25c 275 #define CSR_VSTOPI 0xeb0 276 277 /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */ 278 #define CSR_HIDELEGH 0x613 279 #define CSR_HVIENH 0x618 280 #define CSR_HVIPH 0x655 281 #define CSR_HVIPRIO1H 0x656 282 #define CSR_HVIPRIO2H 0x657 283 #define CSR_VSIEH 0x214 284 #define CSR_VSIPH 0x254 285 286 /* Machine Configuration CSRs */ 287 #define CSR_MENVCFG 0x30A 288 #define CSR_MENVCFGH 0x31A 289 290 /* Enhanced Physical Memory Protection (ePMP) */ 291 #define CSR_MSECCFG 0x747 292 #define CSR_MSECCFGH 0x757 293 /* Physical Memory Protection */ 294 #define CSR_PMPCFG0 0x3a0 295 #define CSR_PMPCFG1 0x3a1 296 #define CSR_PMPCFG2 0x3a2 297 #define CSR_PMPCFG3 0x3a3 298 #define CSR_PMPADDR0 0x3b0 299 #define CSR_PMPADDR1 0x3b1 300 #define CSR_PMPADDR2 0x3b2 301 #define CSR_PMPADDR3 0x3b3 302 #define CSR_PMPADDR4 0x3b4 303 #define CSR_PMPADDR5 0x3b5 304 #define CSR_PMPADDR6 0x3b6 305 #define CSR_PMPADDR7 0x3b7 306 #define CSR_PMPADDR8 0x3b8 307 #define CSR_PMPADDR9 0x3b9 308 #define CSR_PMPADDR10 0x3ba 309 #define CSR_PMPADDR11 0x3bb 310 #define CSR_PMPADDR12 0x3bc 311 #define CSR_PMPADDR13 0x3bd 312 #define CSR_PMPADDR14 0x3be 313 #define CSR_PMPADDR15 0x3bf 314 315 /* Debug/Trace Registers (shared with Debug Mode) */ 316 #define CSR_TSELECT 0x7a0 317 #define CSR_TDATA1 0x7a1 318 #define CSR_TDATA2 0x7a2 319 #define CSR_TDATA3 0x7a3 320 321 /* Debug Mode Registers */ 322 #define CSR_DCSR 0x7b0 323 #define CSR_DPC 0x7b1 324 #define CSR_DSCRATCH 0x7b2 325 326 /* Performance Counters */ 327 #define CSR_MHPMCOUNTER3 0xb03 328 #define CSR_MHPMCOUNTER4 0xb04 329 #define CSR_MHPMCOUNTER5 0xb05 330 #define CSR_MHPMCOUNTER6 0xb06 331 #define CSR_MHPMCOUNTER7 0xb07 332 #define CSR_MHPMCOUNTER8 0xb08 333 #define CSR_MHPMCOUNTER9 0xb09 334 #define CSR_MHPMCOUNTER10 0xb0a 335 #define CSR_MHPMCOUNTER11 0xb0b 336 #define CSR_MHPMCOUNTER12 0xb0c 337 #define CSR_MHPMCOUNTER13 0xb0d 338 #define CSR_MHPMCOUNTER14 0xb0e 339 #define CSR_MHPMCOUNTER15 0xb0f 340 #define CSR_MHPMCOUNTER16 0xb10 341 #define CSR_MHPMCOUNTER17 0xb11 342 #define CSR_MHPMCOUNTER18 0xb12 343 #define CSR_MHPMCOUNTER19 0xb13 344 #define CSR_MHPMCOUNTER20 0xb14 345 #define CSR_MHPMCOUNTER21 0xb15 346 #define CSR_MHPMCOUNTER22 0xb16 347 #define CSR_MHPMCOUNTER23 0xb17 348 #define CSR_MHPMCOUNTER24 0xb18 349 #define CSR_MHPMCOUNTER25 0xb19 350 #define CSR_MHPMCOUNTER26 0xb1a 351 #define CSR_MHPMCOUNTER27 0xb1b 352 #define CSR_MHPMCOUNTER28 0xb1c 353 #define CSR_MHPMCOUNTER29 0xb1d 354 #define CSR_MHPMCOUNTER30 0xb1e 355 #define CSR_MHPMCOUNTER31 0xb1f 356 357 /* Machine counter-inhibit register */ 358 #define CSR_MCOUNTINHIBIT 0x320 359 360 #define CSR_MHPMEVENT3 0x323 361 #define CSR_MHPMEVENT4 0x324 362 #define CSR_MHPMEVENT5 0x325 363 #define CSR_MHPMEVENT6 0x326 364 #define CSR_MHPMEVENT7 0x327 365 #define CSR_MHPMEVENT8 0x328 366 #define CSR_MHPMEVENT9 0x329 367 #define CSR_MHPMEVENT10 0x32a 368 #define CSR_MHPMEVENT11 0x32b 369 #define CSR_MHPMEVENT12 0x32c 370 #define CSR_MHPMEVENT13 0x32d 371 #define CSR_MHPMEVENT14 0x32e 372 #define CSR_MHPMEVENT15 0x32f 373 #define CSR_MHPMEVENT16 0x330 374 #define CSR_MHPMEVENT17 0x331 375 #define CSR_MHPMEVENT18 0x332 376 #define CSR_MHPMEVENT19 0x333 377 #define CSR_MHPMEVENT20 0x334 378 #define CSR_MHPMEVENT21 0x335 379 #define CSR_MHPMEVENT22 0x336 380 #define CSR_MHPMEVENT23 0x337 381 #define CSR_MHPMEVENT24 0x338 382 #define CSR_MHPMEVENT25 0x339 383 #define CSR_MHPMEVENT26 0x33a 384 #define CSR_MHPMEVENT27 0x33b 385 #define CSR_MHPMEVENT28 0x33c 386 #define CSR_MHPMEVENT29 0x33d 387 #define CSR_MHPMEVENT30 0x33e 388 #define CSR_MHPMEVENT31 0x33f 389 #define CSR_MHPMCOUNTER3H 0xb83 390 #define CSR_MHPMCOUNTER4H 0xb84 391 #define CSR_MHPMCOUNTER5H 0xb85 392 #define CSR_MHPMCOUNTER6H 0xb86 393 #define CSR_MHPMCOUNTER7H 0xb87 394 #define CSR_MHPMCOUNTER8H 0xb88 395 #define CSR_MHPMCOUNTER9H 0xb89 396 #define CSR_MHPMCOUNTER10H 0xb8a 397 #define CSR_MHPMCOUNTER11H 0xb8b 398 #define CSR_MHPMCOUNTER12H 0xb8c 399 #define CSR_MHPMCOUNTER13H 0xb8d 400 #define CSR_MHPMCOUNTER14H 0xb8e 401 #define CSR_MHPMCOUNTER15H 0xb8f 402 #define CSR_MHPMCOUNTER16H 0xb90 403 #define CSR_MHPMCOUNTER17H 0xb91 404 #define CSR_MHPMCOUNTER18H 0xb92 405 #define CSR_MHPMCOUNTER19H 0xb93 406 #define CSR_MHPMCOUNTER20H 0xb94 407 #define CSR_MHPMCOUNTER21H 0xb95 408 #define CSR_MHPMCOUNTER22H 0xb96 409 #define CSR_MHPMCOUNTER23H 0xb97 410 #define CSR_MHPMCOUNTER24H 0xb98 411 #define CSR_MHPMCOUNTER25H 0xb99 412 #define CSR_MHPMCOUNTER26H 0xb9a 413 #define CSR_MHPMCOUNTER27H 0xb9b 414 #define CSR_MHPMCOUNTER28H 0xb9c 415 #define CSR_MHPMCOUNTER29H 0xb9d 416 #define CSR_MHPMCOUNTER30H 0xb9e 417 #define CSR_MHPMCOUNTER31H 0xb9f 418 419 /* 420 * User PointerMasking registers 421 * NB: actual CSR numbers might be changed in future 422 */ 423 #define CSR_UMTE 0x4c0 424 #define CSR_UPMMASK 0x4c1 425 #define CSR_UPMBASE 0x4c2 426 427 /* 428 * Machine PointerMasking registers 429 * NB: actual CSR numbers might be changed in future 430 */ 431 #define CSR_MMTE 0x3c0 432 #define CSR_MPMMASK 0x3c1 433 #define CSR_MPMBASE 0x3c2 434 435 /* 436 * Supervisor PointerMaster registers 437 * NB: actual CSR numbers might be changed in future 438 */ 439 #define CSR_SMTE 0x1c0 440 #define CSR_SPMMASK 0x1c1 441 #define CSR_SPMBASE 0x1c2 442 443 /* 444 * Hypervisor PointerMaster registers 445 * NB: actual CSR numbers might be changed in future 446 */ 447 #define CSR_VSMTE 0x2c0 448 #define CSR_VSPMMASK 0x2c1 449 #define CSR_VSPMBASE 0x2c2 450 451 /* Crypto Extension */ 452 #define CSR_SEED 0x015 453 454 /* mstatus CSR bits */ 455 #define MSTATUS_UIE 0x00000001 456 #define MSTATUS_SIE 0x00000002 457 #define MSTATUS_MIE 0x00000008 458 #define MSTATUS_UPIE 0x00000010 459 #define MSTATUS_SPIE 0x00000020 460 #define MSTATUS_UBE 0x00000040 461 #define MSTATUS_MPIE 0x00000080 462 #define MSTATUS_SPP 0x00000100 463 #define MSTATUS_VS 0x00000600 464 #define MSTATUS_MPP 0x00001800 465 #define MSTATUS_FS 0x00006000 466 #define MSTATUS_XS 0x00018000 467 #define MSTATUS_MPRV 0x00020000 468 #define MSTATUS_SUM 0x00040000 /* since: priv-1.10 */ 469 #define MSTATUS_MXR 0x00080000 470 #define MSTATUS_TVM 0x00100000 /* since: priv-1.10 */ 471 #define MSTATUS_TW 0x00200000 /* since: priv-1.10 */ 472 #define MSTATUS_TSR 0x00400000 /* since: priv-1.10 */ 473 #define MSTATUS_GVA 0x4000000000ULL 474 #define MSTATUS_MPV 0x8000000000ULL 475 476 #define MSTATUS64_UXL 0x0000000300000000ULL 477 #define MSTATUS64_SXL 0x0000000C00000000ULL 478 479 #define MSTATUS32_SD 0x80000000 480 #define MSTATUS64_SD 0x8000000000000000ULL 481 #define MSTATUSH128_SD 0x8000000000000000ULL 482 483 #define MISA32_MXL 0xC0000000 484 #define MISA64_MXL 0xC000000000000000ULL 485 486 typedef enum { 487 MXL_RV32 = 1, 488 MXL_RV64 = 2, 489 MXL_RV128 = 3, 490 } RISCVMXL; 491 492 /* sstatus CSR bits */ 493 #define SSTATUS_UIE 0x00000001 494 #define SSTATUS_SIE 0x00000002 495 #define SSTATUS_UPIE 0x00000010 496 #define SSTATUS_SPIE 0x00000020 497 #define SSTATUS_SPP 0x00000100 498 #define SSTATUS_VS 0x00000600 499 #define SSTATUS_FS 0x00006000 500 #define SSTATUS_XS 0x00018000 501 #define SSTATUS_SUM 0x00040000 /* since: priv-1.10 */ 502 #define SSTATUS_MXR 0x00080000 503 504 #define SSTATUS64_UXL 0x0000000300000000ULL 505 506 #define SSTATUS32_SD 0x80000000 507 #define SSTATUS64_SD 0x8000000000000000ULL 508 509 /* hstatus CSR bits */ 510 #define HSTATUS_VSBE 0x00000020 511 #define HSTATUS_GVA 0x00000040 512 #define HSTATUS_SPV 0x00000080 513 #define HSTATUS_SPVP 0x00000100 514 #define HSTATUS_HU 0x00000200 515 #define HSTATUS_VGEIN 0x0003F000 516 #define HSTATUS_VTVM 0x00100000 517 #define HSTATUS_VTW 0x00200000 518 #define HSTATUS_VTSR 0x00400000 519 #define HSTATUS_VSXL 0x300000000 520 521 #define HSTATUS32_WPRI 0xFF8FF87E 522 #define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL 523 524 #define COUNTEREN_CY (1 << 0) 525 #define COUNTEREN_TM (1 << 1) 526 #define COUNTEREN_IR (1 << 2) 527 #define COUNTEREN_HPM3 (1 << 3) 528 529 /* vsstatus CSR bits */ 530 #define VSSTATUS64_UXL 0x0000000300000000ULL 531 532 /* Privilege modes */ 533 #define PRV_U 0 534 #define PRV_S 1 535 #define PRV_H 2 /* Reserved */ 536 #define PRV_M 3 537 538 /* Virtulisation Register Fields */ 539 #define VIRT_ONOFF 1 540 541 /* RV32 satp CSR field masks */ 542 #define SATP32_MODE 0x80000000 543 #define SATP32_ASID 0x7fc00000 544 #define SATP32_PPN 0x003fffff 545 546 /* RV64 satp CSR field masks */ 547 #define SATP64_MODE 0xF000000000000000ULL 548 #define SATP64_ASID 0x0FFFF00000000000ULL 549 #define SATP64_PPN 0x00000FFFFFFFFFFFULL 550 551 /* VM modes (satp.mode) privileged ISA 1.10 */ 552 #define VM_1_10_MBARE 0 553 #define VM_1_10_SV32 1 554 #define VM_1_10_SV39 8 555 #define VM_1_10_SV48 9 556 #define VM_1_10_SV57 10 557 #define VM_1_10_SV64 11 558 559 /* Page table entry (PTE) fields */ 560 #define PTE_V 0x001 /* Valid */ 561 #define PTE_R 0x002 /* Read */ 562 #define PTE_W 0x004 /* Write */ 563 #define PTE_X 0x008 /* Execute */ 564 #define PTE_U 0x010 /* User */ 565 #define PTE_G 0x020 /* Global */ 566 #define PTE_A 0x040 /* Accessed */ 567 #define PTE_D 0x080 /* Dirty */ 568 #define PTE_SOFT 0x300 /* Reserved for Software */ 569 #define PTE_PBMT 0x6000000000000000ULL /* Page-based memory types */ 570 #define PTE_N 0x8000000000000000ULL /* NAPOT translation */ 571 #define PTE_ATTR (PTE_N | PTE_PBMT) /* All attributes bits */ 572 573 /* Page table PPN shift amount */ 574 #define PTE_PPN_SHIFT 10 575 576 /* Page table PPN mask */ 577 #define PTE_PPN_MASK 0x3FFFFFFFFFFC00ULL 578 579 /* Leaf page shift amount */ 580 #define PGSHIFT 12 581 582 /* Default Reset Vector adress */ 583 #define DEFAULT_RSTVEC 0x1000 584 585 /* Exception causes */ 586 typedef enum RISCVException { 587 RISCV_EXCP_NONE = -1, /* sentinel value */ 588 RISCV_EXCP_INST_ADDR_MIS = 0x0, 589 RISCV_EXCP_INST_ACCESS_FAULT = 0x1, 590 RISCV_EXCP_ILLEGAL_INST = 0x2, 591 RISCV_EXCP_BREAKPOINT = 0x3, 592 RISCV_EXCP_LOAD_ADDR_MIS = 0x4, 593 RISCV_EXCP_LOAD_ACCESS_FAULT = 0x5, 594 RISCV_EXCP_STORE_AMO_ADDR_MIS = 0x6, 595 RISCV_EXCP_STORE_AMO_ACCESS_FAULT = 0x7, 596 RISCV_EXCP_U_ECALL = 0x8, 597 RISCV_EXCP_S_ECALL = 0x9, 598 RISCV_EXCP_VS_ECALL = 0xa, 599 RISCV_EXCP_M_ECALL = 0xb, 600 RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */ 601 RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */ 602 RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */ 603 RISCV_EXCP_SEMIHOST = 0x10, 604 RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14, 605 RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15, 606 RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16, 607 RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT = 0x17, 608 } RISCVException; 609 610 #define RISCV_EXCP_INT_FLAG 0x80000000 611 #define RISCV_EXCP_INT_MASK 0x7fffffff 612 613 /* Interrupt causes */ 614 #define IRQ_U_SOFT 0 615 #define IRQ_S_SOFT 1 616 #define IRQ_VS_SOFT 2 617 #define IRQ_M_SOFT 3 618 #define IRQ_U_TIMER 4 619 #define IRQ_S_TIMER 5 620 #define IRQ_VS_TIMER 6 621 #define IRQ_M_TIMER 7 622 #define IRQ_U_EXT 8 623 #define IRQ_S_EXT 9 624 #define IRQ_VS_EXT 10 625 #define IRQ_M_EXT 11 626 #define IRQ_S_GEXT 12 627 #define IRQ_LOCAL_MAX 16 628 #define IRQ_LOCAL_GUEST_MAX (TARGET_LONG_BITS - 1) 629 630 /* mip masks */ 631 #define MIP_USIP (1 << IRQ_U_SOFT) 632 #define MIP_SSIP (1 << IRQ_S_SOFT) 633 #define MIP_VSSIP (1 << IRQ_VS_SOFT) 634 #define MIP_MSIP (1 << IRQ_M_SOFT) 635 #define MIP_UTIP (1 << IRQ_U_TIMER) 636 #define MIP_STIP (1 << IRQ_S_TIMER) 637 #define MIP_VSTIP (1 << IRQ_VS_TIMER) 638 #define MIP_MTIP (1 << IRQ_M_TIMER) 639 #define MIP_UEIP (1 << IRQ_U_EXT) 640 #define MIP_SEIP (1 << IRQ_S_EXT) 641 #define MIP_VSEIP (1 << IRQ_VS_EXT) 642 #define MIP_MEIP (1 << IRQ_M_EXT) 643 #define MIP_SGEIP (1 << IRQ_S_GEXT) 644 645 /* sip masks */ 646 #define SIP_SSIP MIP_SSIP 647 #define SIP_STIP MIP_STIP 648 #define SIP_SEIP MIP_SEIP 649 650 /* MIE masks */ 651 #define MIE_SEIE (1 << IRQ_S_EXT) 652 #define MIE_UEIE (1 << IRQ_U_EXT) 653 #define MIE_STIE (1 << IRQ_S_TIMER) 654 #define MIE_UTIE (1 << IRQ_U_TIMER) 655 #define MIE_SSIE (1 << IRQ_S_SOFT) 656 #define MIE_USIE (1 << IRQ_U_SOFT) 657 658 /* General PointerMasking CSR bits*/ 659 #define PM_ENABLE 0x00000001ULL 660 #define PM_CURRENT 0x00000002ULL 661 #define PM_INSN 0x00000004ULL 662 #define PM_XS_MASK 0x00000003ULL 663 664 /* PointerMasking XS bits values */ 665 #define PM_EXT_DISABLE 0x00000000ULL 666 #define PM_EXT_INITIAL 0x00000001ULL 667 #define PM_EXT_CLEAN 0x00000002ULL 668 #define PM_EXT_DIRTY 0x00000003ULL 669 670 /* Execution enviornment configuration bits */ 671 #define MENVCFG_FIOM BIT(0) 672 #define MENVCFG_CBIE (3UL << 4) 673 #define MENVCFG_CBCFE BIT(6) 674 #define MENVCFG_CBZE BIT(7) 675 #define MENVCFG_PBMTE (1ULL << 62) 676 #define MENVCFG_STCE (1ULL << 63) 677 678 /* For RV32 */ 679 #define MENVCFGH_PBMTE BIT(30) 680 #define MENVCFGH_STCE BIT(31) 681 682 #define SENVCFG_FIOM MENVCFG_FIOM 683 #define SENVCFG_CBIE MENVCFG_CBIE 684 #define SENVCFG_CBCFE MENVCFG_CBCFE 685 #define SENVCFG_CBZE MENVCFG_CBZE 686 687 #define HENVCFG_FIOM MENVCFG_FIOM 688 #define HENVCFG_CBIE MENVCFG_CBIE 689 #define HENVCFG_CBCFE MENVCFG_CBCFE 690 #define HENVCFG_CBZE MENVCFG_CBZE 691 #define HENVCFG_PBMTE MENVCFG_PBMTE 692 #define HENVCFG_STCE MENVCFG_STCE 693 694 /* For RV32 */ 695 #define HENVCFGH_PBMTE MENVCFGH_PBMTE 696 #define HENVCFGH_STCE MENVCFGH_STCE 697 698 /* Offsets for every pair of control bits per each priv level */ 699 #define XS_OFFSET 0ULL 700 #define U_OFFSET 2ULL 701 #define S_OFFSET 5ULL 702 #define M_OFFSET 8ULL 703 704 #define PM_XS_BITS (PM_XS_MASK << XS_OFFSET) 705 #define U_PM_ENABLE (PM_ENABLE << U_OFFSET) 706 #define U_PM_CURRENT (PM_CURRENT << U_OFFSET) 707 #define U_PM_INSN (PM_INSN << U_OFFSET) 708 #define S_PM_ENABLE (PM_ENABLE << S_OFFSET) 709 #define S_PM_CURRENT (PM_CURRENT << S_OFFSET) 710 #define S_PM_INSN (PM_INSN << S_OFFSET) 711 #define M_PM_ENABLE (PM_ENABLE << M_OFFSET) 712 #define M_PM_CURRENT (PM_CURRENT << M_OFFSET) 713 #define M_PM_INSN (PM_INSN << M_OFFSET) 714 715 /* mmte CSR bits */ 716 #define MMTE_PM_XS_BITS PM_XS_BITS 717 #define MMTE_U_PM_ENABLE U_PM_ENABLE 718 #define MMTE_U_PM_CURRENT U_PM_CURRENT 719 #define MMTE_U_PM_INSN U_PM_INSN 720 #define MMTE_S_PM_ENABLE S_PM_ENABLE 721 #define MMTE_S_PM_CURRENT S_PM_CURRENT 722 #define MMTE_S_PM_INSN S_PM_INSN 723 #define MMTE_M_PM_ENABLE M_PM_ENABLE 724 #define MMTE_M_PM_CURRENT M_PM_CURRENT 725 #define MMTE_M_PM_INSN M_PM_INSN 726 #define MMTE_MASK (MMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | MMTE_U_PM_INSN | \ 727 MMTE_S_PM_ENABLE | MMTE_S_PM_CURRENT | MMTE_S_PM_INSN | \ 728 MMTE_M_PM_ENABLE | MMTE_M_PM_CURRENT | MMTE_M_PM_INSN | \ 729 MMTE_PM_XS_BITS) 730 731 /* (v)smte CSR bits */ 732 #define SMTE_PM_XS_BITS PM_XS_BITS 733 #define SMTE_U_PM_ENABLE U_PM_ENABLE 734 #define SMTE_U_PM_CURRENT U_PM_CURRENT 735 #define SMTE_U_PM_INSN U_PM_INSN 736 #define SMTE_S_PM_ENABLE S_PM_ENABLE 737 #define SMTE_S_PM_CURRENT S_PM_CURRENT 738 #define SMTE_S_PM_INSN S_PM_INSN 739 #define SMTE_MASK (SMTE_U_PM_ENABLE | SMTE_U_PM_CURRENT | SMTE_U_PM_INSN | \ 740 SMTE_S_PM_ENABLE | SMTE_S_PM_CURRENT | SMTE_S_PM_INSN | \ 741 SMTE_PM_XS_BITS) 742 743 /* umte CSR bits */ 744 #define UMTE_U_PM_ENABLE U_PM_ENABLE 745 #define UMTE_U_PM_CURRENT U_PM_CURRENT 746 #define UMTE_U_PM_INSN U_PM_INSN 747 #define UMTE_MASK (UMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | UMTE_U_PM_INSN) 748 749 /* MISELECT, SISELECT, and VSISELECT bits (AIA) */ 750 #define ISELECT_IPRIO0 0x30 751 #define ISELECT_IPRIO15 0x3f 752 #define ISELECT_IMSIC_EIDELIVERY 0x70 753 #define ISELECT_IMSIC_EITHRESHOLD 0x72 754 #define ISELECT_IMSIC_EIP0 0x80 755 #define ISELECT_IMSIC_EIP63 0xbf 756 #define ISELECT_IMSIC_EIE0 0xc0 757 #define ISELECT_IMSIC_EIE63 0xff 758 #define ISELECT_IMSIC_FIRST ISELECT_IMSIC_EIDELIVERY 759 #define ISELECT_IMSIC_LAST ISELECT_IMSIC_EIE63 760 #define ISELECT_MASK 0x1ff 761 762 /* Dummy [M|S|VS]ISELECT value for emulating [M|S|VS]TOPEI CSRs */ 763 #define ISELECT_IMSIC_TOPEI (ISELECT_MASK + 1) 764 765 /* IMSIC bits (AIA) */ 766 #define IMSIC_TOPEI_IID_SHIFT 16 767 #define IMSIC_TOPEI_IID_MASK 0x7ff 768 #define IMSIC_TOPEI_IPRIO_MASK 0x7ff 769 #define IMSIC_EIPx_BITS 32 770 #define IMSIC_EIEx_BITS 32 771 772 /* MTOPI and STOPI bits (AIA) */ 773 #define TOPI_IID_SHIFT 16 774 #define TOPI_IID_MASK 0xfff 775 #define TOPI_IPRIO_MASK 0xff 776 777 /* Interrupt priority bits (AIA) */ 778 #define IPRIO_IRQ_BITS 8 779 #define IPRIO_MMAXIPRIO 255 780 #define IPRIO_DEFAULT_UPPER 4 781 #define IPRIO_DEFAULT_MIDDLE (IPRIO_DEFAULT_UPPER + 12) 782 #define IPRIO_DEFAULT_M IPRIO_DEFAULT_MIDDLE 783 #define IPRIO_DEFAULT_S (IPRIO_DEFAULT_M + 3) 784 #define IPRIO_DEFAULT_SGEXT (IPRIO_DEFAULT_S + 3) 785 #define IPRIO_DEFAULT_VS (IPRIO_DEFAULT_SGEXT + 1) 786 #define IPRIO_DEFAULT_LOWER (IPRIO_DEFAULT_VS + 3) 787 788 /* HVICTL bits (AIA) */ 789 #define HVICTL_VTI 0x40000000 790 #define HVICTL_IID 0x0fff0000 791 #define HVICTL_IPRIOM 0x00000100 792 #define HVICTL_IPRIO 0x000000ff 793 #define HVICTL_VALID_MASK \ 794 (HVICTL_VTI | HVICTL_IID | HVICTL_IPRIOM | HVICTL_IPRIO) 795 796 /* seed CSR bits */ 797 #define SEED_OPST (0b11 << 30) 798 #define SEED_OPST_BIST (0b00 << 30) 799 #define SEED_OPST_WAIT (0b01 << 30) 800 #define SEED_OPST_ES16 (0b10 << 30) 801 #define SEED_OPST_DEAD (0b11 << 30) 802 #endif 803