1 /* RISC-V ISA constants */ 2 3 #ifndef TARGET_RISCV_CPU_BITS_H 4 #define TARGET_RISCV_CPU_BITS_H 5 6 #define get_field(reg, mask) (((reg) & \ 7 (uint64_t)(mask)) / ((mask) & ~((mask) << 1))) 8 #define set_field(reg, mask, val) (((reg) & ~(uint64_t)(mask)) | \ 9 (((uint64_t)(val) * ((mask) & ~((mask) << 1))) & \ 10 (uint64_t)(mask))) 11 12 /* Floating point round mode */ 13 #define FSR_RD_SHIFT 5 14 #define FSR_RD (0x7 << FSR_RD_SHIFT) 15 16 /* Floating point accrued exception flags */ 17 #define FPEXC_NX 0x01 18 #define FPEXC_UF 0x02 19 #define FPEXC_OF 0x04 20 #define FPEXC_DZ 0x08 21 #define FPEXC_NV 0x10 22 23 /* Floating point status register bits */ 24 #define FSR_AEXC_SHIFT 0 25 #define FSR_NVA (FPEXC_NV << FSR_AEXC_SHIFT) 26 #define FSR_OFA (FPEXC_OF << FSR_AEXC_SHIFT) 27 #define FSR_UFA (FPEXC_UF << FSR_AEXC_SHIFT) 28 #define FSR_DZA (FPEXC_DZ << FSR_AEXC_SHIFT) 29 #define FSR_NXA (FPEXC_NX << FSR_AEXC_SHIFT) 30 #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA) 31 32 /* Vector Fixed-Point round model */ 33 #define FSR_VXRM_SHIFT 9 34 #define FSR_VXRM (0x3 << FSR_VXRM_SHIFT) 35 36 /* Vector Fixed-Point saturation flag */ 37 #define FSR_VXSAT_SHIFT 8 38 #define FSR_VXSAT (0x1 << FSR_VXSAT_SHIFT) 39 40 /* Control and Status Registers */ 41 42 /* User Trap Setup */ 43 #define CSR_USTATUS 0x000 44 #define CSR_UIE 0x004 45 #define CSR_UTVEC 0x005 46 47 /* User Trap Handling */ 48 #define CSR_USCRATCH 0x040 49 #define CSR_UEPC 0x041 50 #define CSR_UCAUSE 0x042 51 #define CSR_UTVAL 0x043 52 #define CSR_UIP 0x044 53 54 /* User Floating-Point CSRs */ 55 #define CSR_FFLAGS 0x001 56 #define CSR_FRM 0x002 57 #define CSR_FCSR 0x003 58 59 /* User Vector CSRs */ 60 #define CSR_VSTART 0x008 61 #define CSR_VXSAT 0x009 62 #define CSR_VXRM 0x00a 63 #define CSR_VCSR 0x00f 64 #define CSR_VL 0xc20 65 #define CSR_VTYPE 0xc21 66 #define CSR_VLENB 0xc22 67 68 /* VCSR fields */ 69 #define VCSR_VXSAT_SHIFT 0 70 #define VCSR_VXSAT (0x1 << VCSR_VXSAT_SHIFT) 71 #define VCSR_VXRM_SHIFT 1 72 #define VCSR_VXRM (0x3 << VCSR_VXRM_SHIFT) 73 74 /* User Timers and Counters */ 75 #define CSR_CYCLE 0xc00 76 #define CSR_TIME 0xc01 77 #define CSR_INSTRET 0xc02 78 #define CSR_HPMCOUNTER3 0xc03 79 #define CSR_HPMCOUNTER4 0xc04 80 #define CSR_HPMCOUNTER5 0xc05 81 #define CSR_HPMCOUNTER6 0xc06 82 #define CSR_HPMCOUNTER7 0xc07 83 #define CSR_HPMCOUNTER8 0xc08 84 #define CSR_HPMCOUNTER9 0xc09 85 #define CSR_HPMCOUNTER10 0xc0a 86 #define CSR_HPMCOUNTER11 0xc0b 87 #define CSR_HPMCOUNTER12 0xc0c 88 #define CSR_HPMCOUNTER13 0xc0d 89 #define CSR_HPMCOUNTER14 0xc0e 90 #define CSR_HPMCOUNTER15 0xc0f 91 #define CSR_HPMCOUNTER16 0xc10 92 #define CSR_HPMCOUNTER17 0xc11 93 #define CSR_HPMCOUNTER18 0xc12 94 #define CSR_HPMCOUNTER19 0xc13 95 #define CSR_HPMCOUNTER20 0xc14 96 #define CSR_HPMCOUNTER21 0xc15 97 #define CSR_HPMCOUNTER22 0xc16 98 #define CSR_HPMCOUNTER23 0xc17 99 #define CSR_HPMCOUNTER24 0xc18 100 #define CSR_HPMCOUNTER25 0xc19 101 #define CSR_HPMCOUNTER26 0xc1a 102 #define CSR_HPMCOUNTER27 0xc1b 103 #define CSR_HPMCOUNTER28 0xc1c 104 #define CSR_HPMCOUNTER29 0xc1d 105 #define CSR_HPMCOUNTER30 0xc1e 106 #define CSR_HPMCOUNTER31 0xc1f 107 #define CSR_CYCLEH 0xc80 108 #define CSR_TIMEH 0xc81 109 #define CSR_INSTRETH 0xc82 110 #define CSR_HPMCOUNTER3H 0xc83 111 #define CSR_HPMCOUNTER4H 0xc84 112 #define CSR_HPMCOUNTER5H 0xc85 113 #define CSR_HPMCOUNTER6H 0xc86 114 #define CSR_HPMCOUNTER7H 0xc87 115 #define CSR_HPMCOUNTER8H 0xc88 116 #define CSR_HPMCOUNTER9H 0xc89 117 #define CSR_HPMCOUNTER10H 0xc8a 118 #define CSR_HPMCOUNTER11H 0xc8b 119 #define CSR_HPMCOUNTER12H 0xc8c 120 #define CSR_HPMCOUNTER13H 0xc8d 121 #define CSR_HPMCOUNTER14H 0xc8e 122 #define CSR_HPMCOUNTER15H 0xc8f 123 #define CSR_HPMCOUNTER16H 0xc90 124 #define CSR_HPMCOUNTER17H 0xc91 125 #define CSR_HPMCOUNTER18H 0xc92 126 #define CSR_HPMCOUNTER19H 0xc93 127 #define CSR_HPMCOUNTER20H 0xc94 128 #define CSR_HPMCOUNTER21H 0xc95 129 #define CSR_HPMCOUNTER22H 0xc96 130 #define CSR_HPMCOUNTER23H 0xc97 131 #define CSR_HPMCOUNTER24H 0xc98 132 #define CSR_HPMCOUNTER25H 0xc99 133 #define CSR_HPMCOUNTER26H 0xc9a 134 #define CSR_HPMCOUNTER27H 0xc9b 135 #define CSR_HPMCOUNTER28H 0xc9c 136 #define CSR_HPMCOUNTER29H 0xc9d 137 #define CSR_HPMCOUNTER30H 0xc9e 138 #define CSR_HPMCOUNTER31H 0xc9f 139 140 /* Machine Timers and Counters */ 141 #define CSR_MCYCLE 0xb00 142 #define CSR_MINSTRET 0xb02 143 #define CSR_MCYCLEH 0xb80 144 #define CSR_MINSTRETH 0xb82 145 146 /* Machine Information Registers */ 147 #define CSR_MVENDORID 0xf11 148 #define CSR_MARCHID 0xf12 149 #define CSR_MIMPID 0xf13 150 #define CSR_MHARTID 0xf14 151 #define CSR_MCONFIGPTR 0xf15 152 153 /* Machine Trap Setup */ 154 #define CSR_MSTATUS 0x300 155 #define CSR_MISA 0x301 156 #define CSR_MEDELEG 0x302 157 #define CSR_MIDELEG 0x303 158 #define CSR_MIE 0x304 159 #define CSR_MTVEC 0x305 160 #define CSR_MCOUNTEREN 0x306 161 162 /* 32-bit only */ 163 #define CSR_MSTATUSH 0x310 164 165 /* Machine Trap Handling */ 166 #define CSR_MSCRATCH 0x340 167 #define CSR_MEPC 0x341 168 #define CSR_MCAUSE 0x342 169 #define CSR_MTVAL 0x343 170 #define CSR_MIP 0x344 171 172 /* Machine-Level Window to Indirectly Accessed Registers (AIA) */ 173 #define CSR_MISELECT 0x350 174 #define CSR_MIREG 0x351 175 176 /* Machine-Level Interrupts (AIA) */ 177 #define CSR_MTOPEI 0x35c 178 #define CSR_MTOPI 0xfb0 179 180 /* Virtual Interrupts for Supervisor Level (AIA) */ 181 #define CSR_MVIEN 0x308 182 #define CSR_MVIP 0x309 183 184 /* Machine-Level High-Half CSRs (AIA) */ 185 #define CSR_MIDELEGH 0x313 186 #define CSR_MIEH 0x314 187 #define CSR_MVIENH 0x318 188 #define CSR_MVIPH 0x319 189 #define CSR_MIPH 0x354 190 191 /* Supervisor Trap Setup */ 192 #define CSR_SSTATUS 0x100 193 #define CSR_SEDELEG 0x102 194 #define CSR_SIDELEG 0x103 195 #define CSR_SIE 0x104 196 #define CSR_STVEC 0x105 197 #define CSR_SCOUNTEREN 0x106 198 199 /* Supervisor Configuration CSRs */ 200 #define CSR_SENVCFG 0x10A 201 202 /* Supervisor Trap Handling */ 203 #define CSR_SSCRATCH 0x140 204 #define CSR_SEPC 0x141 205 #define CSR_SCAUSE 0x142 206 #define CSR_STVAL 0x143 207 #define CSR_SIP 0x144 208 209 /* Sstc supervisor CSRs */ 210 #define CSR_STIMECMP 0x14D 211 #define CSR_STIMECMPH 0x15D 212 213 /* Supervisor Protection and Translation */ 214 #define CSR_SPTBR 0x180 215 #define CSR_SATP 0x180 216 217 /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */ 218 #define CSR_SISELECT 0x150 219 #define CSR_SIREG 0x151 220 221 /* Supervisor-Level Interrupts (AIA) */ 222 #define CSR_STOPEI 0x15c 223 #define CSR_STOPI 0xdb0 224 225 /* Supervisor-Level High-Half CSRs (AIA) */ 226 #define CSR_SIEH 0x114 227 #define CSR_SIPH 0x154 228 229 /* Hpervisor CSRs */ 230 #define CSR_HSTATUS 0x600 231 #define CSR_HEDELEG 0x602 232 #define CSR_HIDELEG 0x603 233 #define CSR_HIE 0x604 234 #define CSR_HCOUNTEREN 0x606 235 #define CSR_HGEIE 0x607 236 #define CSR_HTVAL 0x643 237 #define CSR_HVIP 0x645 238 #define CSR_HIP 0x644 239 #define CSR_HTINST 0x64A 240 #define CSR_HGEIP 0xE12 241 #define CSR_HGATP 0x680 242 #define CSR_HTIMEDELTA 0x605 243 #define CSR_HTIMEDELTAH 0x615 244 245 /* Hypervisor Configuration CSRs */ 246 #define CSR_HENVCFG 0x60A 247 #define CSR_HENVCFGH 0x61A 248 249 /* Virtual CSRs */ 250 #define CSR_VSSTATUS 0x200 251 #define CSR_VSIE 0x204 252 #define CSR_VSTVEC 0x205 253 #define CSR_VSSCRATCH 0x240 254 #define CSR_VSEPC 0x241 255 #define CSR_VSCAUSE 0x242 256 #define CSR_VSTVAL 0x243 257 #define CSR_VSIP 0x244 258 #define CSR_VSATP 0x280 259 260 /* Sstc virtual CSRs */ 261 #define CSR_VSTIMECMP 0x24D 262 #define CSR_VSTIMECMPH 0x25D 263 264 #define CSR_MTINST 0x34a 265 #define CSR_MTVAL2 0x34b 266 267 /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */ 268 #define CSR_HVIEN 0x608 269 #define CSR_HVICTL 0x609 270 #define CSR_HVIPRIO1 0x646 271 #define CSR_HVIPRIO2 0x647 272 273 /* VS-Level Window to Indirectly Accessed Registers (H-extension with AIA) */ 274 #define CSR_VSISELECT 0x250 275 #define CSR_VSIREG 0x251 276 277 /* VS-Level Interrupts (H-extension with AIA) */ 278 #define CSR_VSTOPEI 0x25c 279 #define CSR_VSTOPI 0xeb0 280 281 /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */ 282 #define CSR_HIDELEGH 0x613 283 #define CSR_HVIENH 0x618 284 #define CSR_HVIPH 0x655 285 #define CSR_HVIPRIO1H 0x656 286 #define CSR_HVIPRIO2H 0x657 287 #define CSR_VSIEH 0x214 288 #define CSR_VSIPH 0x254 289 290 /* Machine Configuration CSRs */ 291 #define CSR_MENVCFG 0x30A 292 #define CSR_MENVCFGH 0x31A 293 294 /* Enhanced Physical Memory Protection (ePMP) */ 295 #define CSR_MSECCFG 0x747 296 #define CSR_MSECCFGH 0x757 297 /* Physical Memory Protection */ 298 #define CSR_PMPCFG0 0x3a0 299 #define CSR_PMPCFG1 0x3a1 300 #define CSR_PMPCFG2 0x3a2 301 #define CSR_PMPCFG3 0x3a3 302 #define CSR_PMPADDR0 0x3b0 303 #define CSR_PMPADDR1 0x3b1 304 #define CSR_PMPADDR2 0x3b2 305 #define CSR_PMPADDR3 0x3b3 306 #define CSR_PMPADDR4 0x3b4 307 #define CSR_PMPADDR5 0x3b5 308 #define CSR_PMPADDR6 0x3b6 309 #define CSR_PMPADDR7 0x3b7 310 #define CSR_PMPADDR8 0x3b8 311 #define CSR_PMPADDR9 0x3b9 312 #define CSR_PMPADDR10 0x3ba 313 #define CSR_PMPADDR11 0x3bb 314 #define CSR_PMPADDR12 0x3bc 315 #define CSR_PMPADDR13 0x3bd 316 #define CSR_PMPADDR14 0x3be 317 #define CSR_PMPADDR15 0x3bf 318 319 /* Debug/Trace Registers (shared with Debug Mode) */ 320 #define CSR_TSELECT 0x7a0 321 #define CSR_TDATA1 0x7a1 322 #define CSR_TDATA2 0x7a2 323 #define CSR_TDATA3 0x7a3 324 325 /* Debug Mode Registers */ 326 #define CSR_DCSR 0x7b0 327 #define CSR_DPC 0x7b1 328 #define CSR_DSCRATCH 0x7b2 329 330 /* Performance Counters */ 331 #define CSR_MHPMCOUNTER3 0xb03 332 #define CSR_MHPMCOUNTER4 0xb04 333 #define CSR_MHPMCOUNTER5 0xb05 334 #define CSR_MHPMCOUNTER6 0xb06 335 #define CSR_MHPMCOUNTER7 0xb07 336 #define CSR_MHPMCOUNTER8 0xb08 337 #define CSR_MHPMCOUNTER9 0xb09 338 #define CSR_MHPMCOUNTER10 0xb0a 339 #define CSR_MHPMCOUNTER11 0xb0b 340 #define CSR_MHPMCOUNTER12 0xb0c 341 #define CSR_MHPMCOUNTER13 0xb0d 342 #define CSR_MHPMCOUNTER14 0xb0e 343 #define CSR_MHPMCOUNTER15 0xb0f 344 #define CSR_MHPMCOUNTER16 0xb10 345 #define CSR_MHPMCOUNTER17 0xb11 346 #define CSR_MHPMCOUNTER18 0xb12 347 #define CSR_MHPMCOUNTER19 0xb13 348 #define CSR_MHPMCOUNTER20 0xb14 349 #define CSR_MHPMCOUNTER21 0xb15 350 #define CSR_MHPMCOUNTER22 0xb16 351 #define CSR_MHPMCOUNTER23 0xb17 352 #define CSR_MHPMCOUNTER24 0xb18 353 #define CSR_MHPMCOUNTER25 0xb19 354 #define CSR_MHPMCOUNTER26 0xb1a 355 #define CSR_MHPMCOUNTER27 0xb1b 356 #define CSR_MHPMCOUNTER28 0xb1c 357 #define CSR_MHPMCOUNTER29 0xb1d 358 #define CSR_MHPMCOUNTER30 0xb1e 359 #define CSR_MHPMCOUNTER31 0xb1f 360 361 /* Machine counter-inhibit register */ 362 #define CSR_MCOUNTINHIBIT 0x320 363 364 #define CSR_MHPMEVENT3 0x323 365 #define CSR_MHPMEVENT4 0x324 366 #define CSR_MHPMEVENT5 0x325 367 #define CSR_MHPMEVENT6 0x326 368 #define CSR_MHPMEVENT7 0x327 369 #define CSR_MHPMEVENT8 0x328 370 #define CSR_MHPMEVENT9 0x329 371 #define CSR_MHPMEVENT10 0x32a 372 #define CSR_MHPMEVENT11 0x32b 373 #define CSR_MHPMEVENT12 0x32c 374 #define CSR_MHPMEVENT13 0x32d 375 #define CSR_MHPMEVENT14 0x32e 376 #define CSR_MHPMEVENT15 0x32f 377 #define CSR_MHPMEVENT16 0x330 378 #define CSR_MHPMEVENT17 0x331 379 #define CSR_MHPMEVENT18 0x332 380 #define CSR_MHPMEVENT19 0x333 381 #define CSR_MHPMEVENT20 0x334 382 #define CSR_MHPMEVENT21 0x335 383 #define CSR_MHPMEVENT22 0x336 384 #define CSR_MHPMEVENT23 0x337 385 #define CSR_MHPMEVENT24 0x338 386 #define CSR_MHPMEVENT25 0x339 387 #define CSR_MHPMEVENT26 0x33a 388 #define CSR_MHPMEVENT27 0x33b 389 #define CSR_MHPMEVENT28 0x33c 390 #define CSR_MHPMEVENT29 0x33d 391 #define CSR_MHPMEVENT30 0x33e 392 #define CSR_MHPMEVENT31 0x33f 393 #define CSR_MHPMCOUNTER3H 0xb83 394 #define CSR_MHPMCOUNTER4H 0xb84 395 #define CSR_MHPMCOUNTER5H 0xb85 396 #define CSR_MHPMCOUNTER6H 0xb86 397 #define CSR_MHPMCOUNTER7H 0xb87 398 #define CSR_MHPMCOUNTER8H 0xb88 399 #define CSR_MHPMCOUNTER9H 0xb89 400 #define CSR_MHPMCOUNTER10H 0xb8a 401 #define CSR_MHPMCOUNTER11H 0xb8b 402 #define CSR_MHPMCOUNTER12H 0xb8c 403 #define CSR_MHPMCOUNTER13H 0xb8d 404 #define CSR_MHPMCOUNTER14H 0xb8e 405 #define CSR_MHPMCOUNTER15H 0xb8f 406 #define CSR_MHPMCOUNTER16H 0xb90 407 #define CSR_MHPMCOUNTER17H 0xb91 408 #define CSR_MHPMCOUNTER18H 0xb92 409 #define CSR_MHPMCOUNTER19H 0xb93 410 #define CSR_MHPMCOUNTER20H 0xb94 411 #define CSR_MHPMCOUNTER21H 0xb95 412 #define CSR_MHPMCOUNTER22H 0xb96 413 #define CSR_MHPMCOUNTER23H 0xb97 414 #define CSR_MHPMCOUNTER24H 0xb98 415 #define CSR_MHPMCOUNTER25H 0xb99 416 #define CSR_MHPMCOUNTER26H 0xb9a 417 #define CSR_MHPMCOUNTER27H 0xb9b 418 #define CSR_MHPMCOUNTER28H 0xb9c 419 #define CSR_MHPMCOUNTER29H 0xb9d 420 #define CSR_MHPMCOUNTER30H 0xb9e 421 #define CSR_MHPMCOUNTER31H 0xb9f 422 423 /* 424 * User PointerMasking registers 425 * NB: actual CSR numbers might be changed in future 426 */ 427 #define CSR_UMTE 0x4c0 428 #define CSR_UPMMASK 0x4c1 429 #define CSR_UPMBASE 0x4c2 430 431 /* 432 * Machine PointerMasking registers 433 * NB: actual CSR numbers might be changed in future 434 */ 435 #define CSR_MMTE 0x3c0 436 #define CSR_MPMMASK 0x3c1 437 #define CSR_MPMBASE 0x3c2 438 439 /* 440 * Supervisor PointerMaster registers 441 * NB: actual CSR numbers might be changed in future 442 */ 443 #define CSR_SMTE 0x1c0 444 #define CSR_SPMMASK 0x1c1 445 #define CSR_SPMBASE 0x1c2 446 447 /* 448 * Hypervisor PointerMaster registers 449 * NB: actual CSR numbers might be changed in future 450 */ 451 #define CSR_VSMTE 0x2c0 452 #define CSR_VSPMMASK 0x2c1 453 #define CSR_VSPMBASE 0x2c2 454 455 /* Crypto Extension */ 456 #define CSR_SEED 0x015 457 458 /* mstatus CSR bits */ 459 #define MSTATUS_UIE 0x00000001 460 #define MSTATUS_SIE 0x00000002 461 #define MSTATUS_MIE 0x00000008 462 #define MSTATUS_UPIE 0x00000010 463 #define MSTATUS_SPIE 0x00000020 464 #define MSTATUS_UBE 0x00000040 465 #define MSTATUS_MPIE 0x00000080 466 #define MSTATUS_SPP 0x00000100 467 #define MSTATUS_VS 0x00000600 468 #define MSTATUS_MPP 0x00001800 469 #define MSTATUS_FS 0x00006000 470 #define MSTATUS_XS 0x00018000 471 #define MSTATUS_MPRV 0x00020000 472 #define MSTATUS_SUM 0x00040000 /* since: priv-1.10 */ 473 #define MSTATUS_MXR 0x00080000 474 #define MSTATUS_TVM 0x00100000 /* since: priv-1.10 */ 475 #define MSTATUS_TW 0x00200000 /* since: priv-1.10 */ 476 #define MSTATUS_TSR 0x00400000 /* since: priv-1.10 */ 477 #define MSTATUS_GVA 0x4000000000ULL 478 #define MSTATUS_MPV 0x8000000000ULL 479 480 #define MSTATUS64_UXL 0x0000000300000000ULL 481 #define MSTATUS64_SXL 0x0000000C00000000ULL 482 483 #define MSTATUS32_SD 0x80000000 484 #define MSTATUS64_SD 0x8000000000000000ULL 485 #define MSTATUSH128_SD 0x8000000000000000ULL 486 487 #define MISA32_MXL 0xC0000000 488 #define MISA64_MXL 0xC000000000000000ULL 489 490 typedef enum { 491 MXL_RV32 = 1, 492 MXL_RV64 = 2, 493 MXL_RV128 = 3, 494 } RISCVMXL; 495 496 /* sstatus CSR bits */ 497 #define SSTATUS_UIE 0x00000001 498 #define SSTATUS_SIE 0x00000002 499 #define SSTATUS_UPIE 0x00000010 500 #define SSTATUS_SPIE 0x00000020 501 #define SSTATUS_SPP 0x00000100 502 #define SSTATUS_VS 0x00000600 503 #define SSTATUS_FS 0x00006000 504 #define SSTATUS_XS 0x00018000 505 #define SSTATUS_SUM 0x00040000 /* since: priv-1.10 */ 506 #define SSTATUS_MXR 0x00080000 507 508 #define SSTATUS64_UXL 0x0000000300000000ULL 509 510 #define SSTATUS32_SD 0x80000000 511 #define SSTATUS64_SD 0x8000000000000000ULL 512 513 /* hstatus CSR bits */ 514 #define HSTATUS_VSBE 0x00000020 515 #define HSTATUS_GVA 0x00000040 516 #define HSTATUS_SPV 0x00000080 517 #define HSTATUS_SPVP 0x00000100 518 #define HSTATUS_HU 0x00000200 519 #define HSTATUS_VGEIN 0x0003F000 520 #define HSTATUS_VTVM 0x00100000 521 #define HSTATUS_VTW 0x00200000 522 #define HSTATUS_VTSR 0x00400000 523 #define HSTATUS_VSXL 0x300000000 524 525 #define HSTATUS32_WPRI 0xFF8FF87E 526 #define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL 527 528 #define COUNTEREN_CY (1 << 0) 529 #define COUNTEREN_TM (1 << 1) 530 #define COUNTEREN_IR (1 << 2) 531 #define COUNTEREN_HPM3 (1 << 3) 532 533 /* vsstatus CSR bits */ 534 #define VSSTATUS64_UXL 0x0000000300000000ULL 535 536 /* Privilege modes */ 537 #define PRV_U 0 538 #define PRV_S 1 539 #define PRV_H 2 /* Reserved */ 540 #define PRV_M 3 541 542 /* Virtulisation Register Fields */ 543 #define VIRT_ONOFF 1 544 545 /* RV32 satp CSR field masks */ 546 #define SATP32_MODE 0x80000000 547 #define SATP32_ASID 0x7fc00000 548 #define SATP32_PPN 0x003fffff 549 550 /* RV64 satp CSR field masks */ 551 #define SATP64_MODE 0xF000000000000000ULL 552 #define SATP64_ASID 0x0FFFF00000000000ULL 553 #define SATP64_PPN 0x00000FFFFFFFFFFFULL 554 555 /* VM modes (satp.mode) privileged ISA 1.10 */ 556 #define VM_1_10_MBARE 0 557 #define VM_1_10_SV32 1 558 #define VM_1_10_SV39 8 559 #define VM_1_10_SV48 9 560 #define VM_1_10_SV57 10 561 #define VM_1_10_SV64 11 562 563 /* Page table entry (PTE) fields */ 564 #define PTE_V 0x001 /* Valid */ 565 #define PTE_R 0x002 /* Read */ 566 #define PTE_W 0x004 /* Write */ 567 #define PTE_X 0x008 /* Execute */ 568 #define PTE_U 0x010 /* User */ 569 #define PTE_G 0x020 /* Global */ 570 #define PTE_A 0x040 /* Accessed */ 571 #define PTE_D 0x080 /* Dirty */ 572 #define PTE_SOFT 0x300 /* Reserved for Software */ 573 #define PTE_PBMT 0x6000000000000000ULL /* Page-based memory types */ 574 #define PTE_N 0x8000000000000000ULL /* NAPOT translation */ 575 #define PTE_ATTR (PTE_N | PTE_PBMT) /* All attributes bits */ 576 577 /* Page table PPN shift amount */ 578 #define PTE_PPN_SHIFT 10 579 580 /* Page table PPN mask */ 581 #define PTE_PPN_MASK 0x3FFFFFFFFFFC00ULL 582 583 /* Leaf page shift amount */ 584 #define PGSHIFT 12 585 586 /* Default Reset Vector adress */ 587 #define DEFAULT_RSTVEC 0x1000 588 589 /* Exception causes */ 590 typedef enum RISCVException { 591 RISCV_EXCP_NONE = -1, /* sentinel value */ 592 RISCV_EXCP_INST_ADDR_MIS = 0x0, 593 RISCV_EXCP_INST_ACCESS_FAULT = 0x1, 594 RISCV_EXCP_ILLEGAL_INST = 0x2, 595 RISCV_EXCP_BREAKPOINT = 0x3, 596 RISCV_EXCP_LOAD_ADDR_MIS = 0x4, 597 RISCV_EXCP_LOAD_ACCESS_FAULT = 0x5, 598 RISCV_EXCP_STORE_AMO_ADDR_MIS = 0x6, 599 RISCV_EXCP_STORE_AMO_ACCESS_FAULT = 0x7, 600 RISCV_EXCP_U_ECALL = 0x8, 601 RISCV_EXCP_S_ECALL = 0x9, 602 RISCV_EXCP_VS_ECALL = 0xa, 603 RISCV_EXCP_M_ECALL = 0xb, 604 RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */ 605 RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */ 606 RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */ 607 RISCV_EXCP_SEMIHOST = 0x10, 608 RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14, 609 RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15, 610 RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16, 611 RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT = 0x17, 612 } RISCVException; 613 614 #define RISCV_EXCP_INT_FLAG 0x80000000 615 #define RISCV_EXCP_INT_MASK 0x7fffffff 616 617 /* Interrupt causes */ 618 #define IRQ_U_SOFT 0 619 #define IRQ_S_SOFT 1 620 #define IRQ_VS_SOFT 2 621 #define IRQ_M_SOFT 3 622 #define IRQ_U_TIMER 4 623 #define IRQ_S_TIMER 5 624 #define IRQ_VS_TIMER 6 625 #define IRQ_M_TIMER 7 626 #define IRQ_U_EXT 8 627 #define IRQ_S_EXT 9 628 #define IRQ_VS_EXT 10 629 #define IRQ_M_EXT 11 630 #define IRQ_S_GEXT 12 631 #define IRQ_LOCAL_MAX 16 632 #define IRQ_LOCAL_GUEST_MAX (TARGET_LONG_BITS - 1) 633 634 /* mip masks */ 635 #define MIP_USIP (1 << IRQ_U_SOFT) 636 #define MIP_SSIP (1 << IRQ_S_SOFT) 637 #define MIP_VSSIP (1 << IRQ_VS_SOFT) 638 #define MIP_MSIP (1 << IRQ_M_SOFT) 639 #define MIP_UTIP (1 << IRQ_U_TIMER) 640 #define MIP_STIP (1 << IRQ_S_TIMER) 641 #define MIP_VSTIP (1 << IRQ_VS_TIMER) 642 #define MIP_MTIP (1 << IRQ_M_TIMER) 643 #define MIP_UEIP (1 << IRQ_U_EXT) 644 #define MIP_SEIP (1 << IRQ_S_EXT) 645 #define MIP_VSEIP (1 << IRQ_VS_EXT) 646 #define MIP_MEIP (1 << IRQ_M_EXT) 647 #define MIP_SGEIP (1 << IRQ_S_GEXT) 648 649 /* sip masks */ 650 #define SIP_SSIP MIP_SSIP 651 #define SIP_STIP MIP_STIP 652 #define SIP_SEIP MIP_SEIP 653 654 /* MIE masks */ 655 #define MIE_SEIE (1 << IRQ_S_EXT) 656 #define MIE_UEIE (1 << IRQ_U_EXT) 657 #define MIE_STIE (1 << IRQ_S_TIMER) 658 #define MIE_UTIE (1 << IRQ_U_TIMER) 659 #define MIE_SSIE (1 << IRQ_S_SOFT) 660 #define MIE_USIE (1 << IRQ_U_SOFT) 661 662 /* General PointerMasking CSR bits*/ 663 #define PM_ENABLE 0x00000001ULL 664 #define PM_CURRENT 0x00000002ULL 665 #define PM_INSN 0x00000004ULL 666 #define PM_XS_MASK 0x00000003ULL 667 668 /* PointerMasking XS bits values */ 669 #define PM_EXT_DISABLE 0x00000000ULL 670 #define PM_EXT_INITIAL 0x00000001ULL 671 #define PM_EXT_CLEAN 0x00000002ULL 672 #define PM_EXT_DIRTY 0x00000003ULL 673 674 /* Execution enviornment configuration bits */ 675 #define MENVCFG_FIOM BIT(0) 676 #define MENVCFG_CBIE (3UL << 4) 677 #define MENVCFG_CBCFE BIT(6) 678 #define MENVCFG_CBZE BIT(7) 679 #define MENVCFG_PBMTE (1ULL << 62) 680 #define MENVCFG_STCE (1ULL << 63) 681 682 /* For RV32 */ 683 #define MENVCFGH_PBMTE BIT(30) 684 #define MENVCFGH_STCE BIT(31) 685 686 #define SENVCFG_FIOM MENVCFG_FIOM 687 #define SENVCFG_CBIE MENVCFG_CBIE 688 #define SENVCFG_CBCFE MENVCFG_CBCFE 689 #define SENVCFG_CBZE MENVCFG_CBZE 690 691 #define HENVCFG_FIOM MENVCFG_FIOM 692 #define HENVCFG_CBIE MENVCFG_CBIE 693 #define HENVCFG_CBCFE MENVCFG_CBCFE 694 #define HENVCFG_CBZE MENVCFG_CBZE 695 #define HENVCFG_PBMTE MENVCFG_PBMTE 696 #define HENVCFG_STCE MENVCFG_STCE 697 698 /* For RV32 */ 699 #define HENVCFGH_PBMTE MENVCFGH_PBMTE 700 #define HENVCFGH_STCE MENVCFGH_STCE 701 702 /* Offsets for every pair of control bits per each priv level */ 703 #define XS_OFFSET 0ULL 704 #define U_OFFSET 2ULL 705 #define S_OFFSET 5ULL 706 #define M_OFFSET 8ULL 707 708 #define PM_XS_BITS (PM_XS_MASK << XS_OFFSET) 709 #define U_PM_ENABLE (PM_ENABLE << U_OFFSET) 710 #define U_PM_CURRENT (PM_CURRENT << U_OFFSET) 711 #define U_PM_INSN (PM_INSN << U_OFFSET) 712 #define S_PM_ENABLE (PM_ENABLE << S_OFFSET) 713 #define S_PM_CURRENT (PM_CURRENT << S_OFFSET) 714 #define S_PM_INSN (PM_INSN << S_OFFSET) 715 #define M_PM_ENABLE (PM_ENABLE << M_OFFSET) 716 #define M_PM_CURRENT (PM_CURRENT << M_OFFSET) 717 #define M_PM_INSN (PM_INSN << M_OFFSET) 718 719 /* mmte CSR bits */ 720 #define MMTE_PM_XS_BITS PM_XS_BITS 721 #define MMTE_U_PM_ENABLE U_PM_ENABLE 722 #define MMTE_U_PM_CURRENT U_PM_CURRENT 723 #define MMTE_U_PM_INSN U_PM_INSN 724 #define MMTE_S_PM_ENABLE S_PM_ENABLE 725 #define MMTE_S_PM_CURRENT S_PM_CURRENT 726 #define MMTE_S_PM_INSN S_PM_INSN 727 #define MMTE_M_PM_ENABLE M_PM_ENABLE 728 #define MMTE_M_PM_CURRENT M_PM_CURRENT 729 #define MMTE_M_PM_INSN M_PM_INSN 730 #define MMTE_MASK (MMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | MMTE_U_PM_INSN | \ 731 MMTE_S_PM_ENABLE | MMTE_S_PM_CURRENT | MMTE_S_PM_INSN | \ 732 MMTE_M_PM_ENABLE | MMTE_M_PM_CURRENT | MMTE_M_PM_INSN | \ 733 MMTE_PM_XS_BITS) 734 735 /* (v)smte CSR bits */ 736 #define SMTE_PM_XS_BITS PM_XS_BITS 737 #define SMTE_U_PM_ENABLE U_PM_ENABLE 738 #define SMTE_U_PM_CURRENT U_PM_CURRENT 739 #define SMTE_U_PM_INSN U_PM_INSN 740 #define SMTE_S_PM_ENABLE S_PM_ENABLE 741 #define SMTE_S_PM_CURRENT S_PM_CURRENT 742 #define SMTE_S_PM_INSN S_PM_INSN 743 #define SMTE_MASK (SMTE_U_PM_ENABLE | SMTE_U_PM_CURRENT | SMTE_U_PM_INSN | \ 744 SMTE_S_PM_ENABLE | SMTE_S_PM_CURRENT | SMTE_S_PM_INSN | \ 745 SMTE_PM_XS_BITS) 746 747 /* umte CSR bits */ 748 #define UMTE_U_PM_ENABLE U_PM_ENABLE 749 #define UMTE_U_PM_CURRENT U_PM_CURRENT 750 #define UMTE_U_PM_INSN U_PM_INSN 751 #define UMTE_MASK (UMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | UMTE_U_PM_INSN) 752 753 /* MISELECT, SISELECT, and VSISELECT bits (AIA) */ 754 #define ISELECT_IPRIO0 0x30 755 #define ISELECT_IPRIO15 0x3f 756 #define ISELECT_IMSIC_EIDELIVERY 0x70 757 #define ISELECT_IMSIC_EITHRESHOLD 0x72 758 #define ISELECT_IMSIC_EIP0 0x80 759 #define ISELECT_IMSIC_EIP63 0xbf 760 #define ISELECT_IMSIC_EIE0 0xc0 761 #define ISELECT_IMSIC_EIE63 0xff 762 #define ISELECT_IMSIC_FIRST ISELECT_IMSIC_EIDELIVERY 763 #define ISELECT_IMSIC_LAST ISELECT_IMSIC_EIE63 764 #define ISELECT_MASK 0x1ff 765 766 /* Dummy [M|S|VS]ISELECT value for emulating [M|S|VS]TOPEI CSRs */ 767 #define ISELECT_IMSIC_TOPEI (ISELECT_MASK + 1) 768 769 /* IMSIC bits (AIA) */ 770 #define IMSIC_TOPEI_IID_SHIFT 16 771 #define IMSIC_TOPEI_IID_MASK 0x7ff 772 #define IMSIC_TOPEI_IPRIO_MASK 0x7ff 773 #define IMSIC_EIPx_BITS 32 774 #define IMSIC_EIEx_BITS 32 775 776 /* MTOPI and STOPI bits (AIA) */ 777 #define TOPI_IID_SHIFT 16 778 #define TOPI_IID_MASK 0xfff 779 #define TOPI_IPRIO_MASK 0xff 780 781 /* Interrupt priority bits (AIA) */ 782 #define IPRIO_IRQ_BITS 8 783 #define IPRIO_MMAXIPRIO 255 784 #define IPRIO_DEFAULT_UPPER 4 785 #define IPRIO_DEFAULT_MIDDLE (IPRIO_DEFAULT_UPPER + 12) 786 #define IPRIO_DEFAULT_M IPRIO_DEFAULT_MIDDLE 787 #define IPRIO_DEFAULT_S (IPRIO_DEFAULT_M + 3) 788 #define IPRIO_DEFAULT_SGEXT (IPRIO_DEFAULT_S + 3) 789 #define IPRIO_DEFAULT_VS (IPRIO_DEFAULT_SGEXT + 1) 790 #define IPRIO_DEFAULT_LOWER (IPRIO_DEFAULT_VS + 3) 791 792 /* HVICTL bits (AIA) */ 793 #define HVICTL_VTI 0x40000000 794 #define HVICTL_IID 0x0fff0000 795 #define HVICTL_IPRIOM 0x00000100 796 #define HVICTL_IPRIO 0x000000ff 797 #define HVICTL_VALID_MASK \ 798 (HVICTL_VTI | HVICTL_IID | HVICTL_IPRIOM | HVICTL_IPRIO) 799 800 /* seed CSR bits */ 801 #define SEED_OPST (0b11 << 30) 802 #define SEED_OPST_BIST (0b00 << 30) 803 #define SEED_OPST_WAIT (0b01 << 30) 804 #define SEED_OPST_ES16 (0b10 << 30) 805 #define SEED_OPST_DEAD (0b11 << 30) 806 #endif 807