1 /* RISC-V ISA constants */ 2 3 #ifndef TARGET_RISCV_CPU_BITS_H 4 #define TARGET_RISCV_CPU_BITS_H 5 6 #define get_field(reg, mask) (((reg) & \ 7 (uint64_t)(mask)) / ((mask) & ~((mask) << 1))) 8 #define set_field(reg, mask, val) (((reg) & ~(uint64_t)(mask)) | \ 9 (((uint64_t)(val) * ((mask) & ~((mask) << 1))) & \ 10 (uint64_t)(mask))) 11 12 /* Extension context status mask */ 13 #define EXT_STATUS_MASK 0x3ULL 14 15 /* Floating point round mode */ 16 #define FSR_RD_SHIFT 5 17 #define FSR_RD (0x7 << FSR_RD_SHIFT) 18 19 /* Floating point accrued exception flags */ 20 #define FPEXC_NX 0x01 21 #define FPEXC_UF 0x02 22 #define FPEXC_OF 0x04 23 #define FPEXC_DZ 0x08 24 #define FPEXC_NV 0x10 25 26 /* Floating point status register bits */ 27 #define FSR_AEXC_SHIFT 0 28 #define FSR_NVA (FPEXC_NV << FSR_AEXC_SHIFT) 29 #define FSR_OFA (FPEXC_OF << FSR_AEXC_SHIFT) 30 #define FSR_UFA (FPEXC_UF << FSR_AEXC_SHIFT) 31 #define FSR_DZA (FPEXC_DZ << FSR_AEXC_SHIFT) 32 #define FSR_NXA (FPEXC_NX << FSR_AEXC_SHIFT) 33 #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA) 34 35 /* Control and Status Registers */ 36 37 /* User Trap Setup */ 38 #define CSR_USTATUS 0x000 39 #define CSR_UIE 0x004 40 #define CSR_UTVEC 0x005 41 42 /* User Trap Handling */ 43 #define CSR_USCRATCH 0x040 44 #define CSR_UEPC 0x041 45 #define CSR_UCAUSE 0x042 46 #define CSR_UTVAL 0x043 47 #define CSR_UIP 0x044 48 49 /* User Floating-Point CSRs */ 50 #define CSR_FFLAGS 0x001 51 #define CSR_FRM 0x002 52 #define CSR_FCSR 0x003 53 54 /* User Vector CSRs */ 55 #define CSR_VSTART 0x008 56 #define CSR_VXSAT 0x009 57 #define CSR_VXRM 0x00a 58 #define CSR_VCSR 0x00f 59 #define CSR_VL 0xc20 60 #define CSR_VTYPE 0xc21 61 #define CSR_VLENB 0xc22 62 63 /* VCSR fields */ 64 #define VCSR_VXSAT_SHIFT 0 65 #define VCSR_VXSAT (0x1 << VCSR_VXSAT_SHIFT) 66 #define VCSR_VXRM_SHIFT 1 67 #define VCSR_VXRM (0x3 << VCSR_VXRM_SHIFT) 68 69 /* User Timers and Counters */ 70 #define CSR_CYCLE 0xc00 71 #define CSR_TIME 0xc01 72 #define CSR_INSTRET 0xc02 73 #define CSR_HPMCOUNTER3 0xc03 74 #define CSR_HPMCOUNTER4 0xc04 75 #define CSR_HPMCOUNTER5 0xc05 76 #define CSR_HPMCOUNTER6 0xc06 77 #define CSR_HPMCOUNTER7 0xc07 78 #define CSR_HPMCOUNTER8 0xc08 79 #define CSR_HPMCOUNTER9 0xc09 80 #define CSR_HPMCOUNTER10 0xc0a 81 #define CSR_HPMCOUNTER11 0xc0b 82 #define CSR_HPMCOUNTER12 0xc0c 83 #define CSR_HPMCOUNTER13 0xc0d 84 #define CSR_HPMCOUNTER14 0xc0e 85 #define CSR_HPMCOUNTER15 0xc0f 86 #define CSR_HPMCOUNTER16 0xc10 87 #define CSR_HPMCOUNTER17 0xc11 88 #define CSR_HPMCOUNTER18 0xc12 89 #define CSR_HPMCOUNTER19 0xc13 90 #define CSR_HPMCOUNTER20 0xc14 91 #define CSR_HPMCOUNTER21 0xc15 92 #define CSR_HPMCOUNTER22 0xc16 93 #define CSR_HPMCOUNTER23 0xc17 94 #define CSR_HPMCOUNTER24 0xc18 95 #define CSR_HPMCOUNTER25 0xc19 96 #define CSR_HPMCOUNTER26 0xc1a 97 #define CSR_HPMCOUNTER27 0xc1b 98 #define CSR_HPMCOUNTER28 0xc1c 99 #define CSR_HPMCOUNTER29 0xc1d 100 #define CSR_HPMCOUNTER30 0xc1e 101 #define CSR_HPMCOUNTER31 0xc1f 102 #define CSR_CYCLEH 0xc80 103 #define CSR_TIMEH 0xc81 104 #define CSR_INSTRETH 0xc82 105 #define CSR_HPMCOUNTER3H 0xc83 106 #define CSR_HPMCOUNTER4H 0xc84 107 #define CSR_HPMCOUNTER5H 0xc85 108 #define CSR_HPMCOUNTER6H 0xc86 109 #define CSR_HPMCOUNTER7H 0xc87 110 #define CSR_HPMCOUNTER8H 0xc88 111 #define CSR_HPMCOUNTER9H 0xc89 112 #define CSR_HPMCOUNTER10H 0xc8a 113 #define CSR_HPMCOUNTER11H 0xc8b 114 #define CSR_HPMCOUNTER12H 0xc8c 115 #define CSR_HPMCOUNTER13H 0xc8d 116 #define CSR_HPMCOUNTER14H 0xc8e 117 #define CSR_HPMCOUNTER15H 0xc8f 118 #define CSR_HPMCOUNTER16H 0xc90 119 #define CSR_HPMCOUNTER17H 0xc91 120 #define CSR_HPMCOUNTER18H 0xc92 121 #define CSR_HPMCOUNTER19H 0xc93 122 #define CSR_HPMCOUNTER20H 0xc94 123 #define CSR_HPMCOUNTER21H 0xc95 124 #define CSR_HPMCOUNTER22H 0xc96 125 #define CSR_HPMCOUNTER23H 0xc97 126 #define CSR_HPMCOUNTER24H 0xc98 127 #define CSR_HPMCOUNTER25H 0xc99 128 #define CSR_HPMCOUNTER26H 0xc9a 129 #define CSR_HPMCOUNTER27H 0xc9b 130 #define CSR_HPMCOUNTER28H 0xc9c 131 #define CSR_HPMCOUNTER29H 0xc9d 132 #define CSR_HPMCOUNTER30H 0xc9e 133 #define CSR_HPMCOUNTER31H 0xc9f 134 135 /* Machine Timers and Counters */ 136 #define CSR_MCYCLE 0xb00 137 #define CSR_MINSTRET 0xb02 138 #define CSR_MCYCLEH 0xb80 139 #define CSR_MINSTRETH 0xb82 140 141 /* Machine Information Registers */ 142 #define CSR_MVENDORID 0xf11 143 #define CSR_MARCHID 0xf12 144 #define CSR_MIMPID 0xf13 145 #define CSR_MHARTID 0xf14 146 #define CSR_MCONFIGPTR 0xf15 147 148 /* Machine Trap Setup */ 149 #define CSR_MSTATUS 0x300 150 #define CSR_MISA 0x301 151 #define CSR_MEDELEG 0x302 152 #define CSR_MIDELEG 0x303 153 #define CSR_MIE 0x304 154 #define CSR_MTVEC 0x305 155 #define CSR_MCOUNTEREN 0x306 156 157 /* 32-bit only */ 158 #define CSR_MSTATUSH 0x310 159 #define CSR_MEDELEGH 0x312 160 #define CSR_HEDELEGH 0x612 161 162 /* Machine Trap Handling */ 163 #define CSR_MSCRATCH 0x340 164 #define CSR_MEPC 0x341 165 #define CSR_MCAUSE 0x342 166 #define CSR_MTVAL 0x343 167 #define CSR_MIP 0x344 168 169 /* Machine-Level Window to Indirectly Accessed Registers (AIA) */ 170 #define CSR_MISELECT 0x350 171 #define CSR_MIREG 0x351 172 173 /* Machine-Level Interrupts (AIA) */ 174 #define CSR_MTOPEI 0x35c 175 #define CSR_MTOPI 0xfb0 176 177 /* Virtual Interrupts for Supervisor Level (AIA) */ 178 #define CSR_MVIEN 0x308 179 #define CSR_MVIP 0x309 180 181 /* Machine-Level High-Half CSRs (AIA) */ 182 #define CSR_MIDELEGH 0x313 183 #define CSR_MIEH 0x314 184 #define CSR_MVIENH 0x318 185 #define CSR_MVIPH 0x319 186 #define CSR_MIPH 0x354 187 188 /* Supervisor Trap Setup */ 189 #define CSR_SSTATUS 0x100 190 #define CSR_SIE 0x104 191 #define CSR_STVEC 0x105 192 #define CSR_SCOUNTEREN 0x106 193 194 /* Supervisor Configuration CSRs */ 195 #define CSR_SENVCFG 0x10A 196 197 /* Supervisor state CSRs */ 198 #define CSR_SSTATEEN0 0x10C 199 #define CSR_SSTATEEN1 0x10D 200 #define CSR_SSTATEEN2 0x10E 201 #define CSR_SSTATEEN3 0x10F 202 203 /* Supervisor Trap Handling */ 204 #define CSR_SSCRATCH 0x140 205 #define CSR_SEPC 0x141 206 #define CSR_SCAUSE 0x142 207 #define CSR_STVAL 0x143 208 #define CSR_SIP 0x144 209 210 /* Sstc supervisor CSRs */ 211 #define CSR_STIMECMP 0x14D 212 #define CSR_STIMECMPH 0x15D 213 214 /* Supervisor Protection and Translation */ 215 #define CSR_SPTBR 0x180 216 #define CSR_SATP 0x180 217 218 /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */ 219 #define CSR_SISELECT 0x150 220 #define CSR_SIREG 0x151 221 222 /* Supervisor-Level Interrupts (AIA) */ 223 #define CSR_STOPEI 0x15c 224 #define CSR_STOPI 0xdb0 225 226 /* Supervisor-Level High-Half CSRs (AIA) */ 227 #define CSR_SIEH 0x114 228 #define CSR_SIPH 0x154 229 230 /* Hpervisor CSRs */ 231 #define CSR_HSTATUS 0x600 232 #define CSR_HEDELEG 0x602 233 #define CSR_HIDELEG 0x603 234 #define CSR_HIE 0x604 235 #define CSR_HCOUNTEREN 0x606 236 #define CSR_HGEIE 0x607 237 #define CSR_HTVAL 0x643 238 #define CSR_HVIP 0x645 239 #define CSR_HIP 0x644 240 #define CSR_HTINST 0x64A 241 #define CSR_HGEIP 0xE12 242 #define CSR_HGATP 0x680 243 #define CSR_HTIMEDELTA 0x605 244 #define CSR_HTIMEDELTAH 0x615 245 246 /* Hypervisor Configuration CSRs */ 247 #define CSR_HENVCFG 0x60A 248 #define CSR_HENVCFGH 0x61A 249 250 /* Hypervisor state CSRs */ 251 #define CSR_HSTATEEN0 0x60C 252 #define CSR_HSTATEEN0H 0x61C 253 #define CSR_HSTATEEN1 0x60D 254 #define CSR_HSTATEEN1H 0x61D 255 #define CSR_HSTATEEN2 0x60E 256 #define CSR_HSTATEEN2H 0x61E 257 #define CSR_HSTATEEN3 0x60F 258 #define CSR_HSTATEEN3H 0x61F 259 260 /* Virtual CSRs */ 261 #define CSR_VSSTATUS 0x200 262 #define CSR_VSIE 0x204 263 #define CSR_VSTVEC 0x205 264 #define CSR_VSSCRATCH 0x240 265 #define CSR_VSEPC 0x241 266 #define CSR_VSCAUSE 0x242 267 #define CSR_VSTVAL 0x243 268 #define CSR_VSIP 0x244 269 #define CSR_VSATP 0x280 270 271 /* Sstc virtual CSRs */ 272 #define CSR_VSTIMECMP 0x24D 273 #define CSR_VSTIMECMPH 0x25D 274 275 #define CSR_MTINST 0x34a 276 #define CSR_MTVAL2 0x34b 277 278 /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */ 279 #define CSR_HVIEN 0x608 280 #define CSR_HVICTL 0x609 281 #define CSR_HVIPRIO1 0x646 282 #define CSR_HVIPRIO2 0x647 283 284 /* VS-Level Window to Indirectly Accessed Registers (H-extension with AIA) */ 285 #define CSR_VSISELECT 0x250 286 #define CSR_VSIREG 0x251 287 288 /* VS-Level Interrupts (H-extension with AIA) */ 289 #define CSR_VSTOPEI 0x25c 290 #define CSR_VSTOPI 0xeb0 291 292 /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */ 293 #define CSR_HIDELEGH 0x613 294 #define CSR_HVIENH 0x618 295 #define CSR_HVIPH 0x655 296 #define CSR_HVIPRIO1H 0x656 297 #define CSR_HVIPRIO2H 0x657 298 #define CSR_VSIEH 0x214 299 #define CSR_VSIPH 0x254 300 301 /* Machine Configuration CSRs */ 302 #define CSR_MENVCFG 0x30A 303 #define CSR_MENVCFGH 0x31A 304 305 /* Machine state CSRs */ 306 #define CSR_MSTATEEN0 0x30C 307 #define CSR_MSTATEEN0H 0x31C 308 #define CSR_MSTATEEN1 0x30D 309 #define CSR_MSTATEEN1H 0x31D 310 #define CSR_MSTATEEN2 0x30E 311 #define CSR_MSTATEEN2H 0x31E 312 #define CSR_MSTATEEN3 0x30F 313 #define CSR_MSTATEEN3H 0x31F 314 315 /* Common defines for all smstateen */ 316 #define SMSTATEEN_MAX_COUNT 4 317 #define SMSTATEEN0_CS (1ULL << 0) 318 #define SMSTATEEN0_FCSR (1ULL << 1) 319 #define SMSTATEEN0_JVT (1ULL << 2) 320 #define SMSTATEEN0_P1P13 (1ULL << 56) 321 #define SMSTATEEN0_HSCONTXT (1ULL << 57) 322 #define SMSTATEEN0_IMSIC (1ULL << 58) 323 #define SMSTATEEN0_AIA (1ULL << 59) 324 #define SMSTATEEN0_SVSLCT (1ULL << 60) 325 #define SMSTATEEN0_HSENVCFG (1ULL << 62) 326 #define SMSTATEEN_STATEEN (1ULL << 63) 327 328 /* Enhanced Physical Memory Protection (ePMP) */ 329 #define CSR_MSECCFG 0x747 330 #define CSR_MSECCFGH 0x757 331 /* Physical Memory Protection */ 332 #define CSR_PMPCFG0 0x3a0 333 #define CSR_PMPCFG1 0x3a1 334 #define CSR_PMPCFG2 0x3a2 335 #define CSR_PMPCFG3 0x3a3 336 #define CSR_PMPADDR0 0x3b0 337 #define CSR_PMPADDR1 0x3b1 338 #define CSR_PMPADDR2 0x3b2 339 #define CSR_PMPADDR3 0x3b3 340 #define CSR_PMPADDR4 0x3b4 341 #define CSR_PMPADDR5 0x3b5 342 #define CSR_PMPADDR6 0x3b6 343 #define CSR_PMPADDR7 0x3b7 344 #define CSR_PMPADDR8 0x3b8 345 #define CSR_PMPADDR9 0x3b9 346 #define CSR_PMPADDR10 0x3ba 347 #define CSR_PMPADDR11 0x3bb 348 #define CSR_PMPADDR12 0x3bc 349 #define CSR_PMPADDR13 0x3bd 350 #define CSR_PMPADDR14 0x3be 351 #define CSR_PMPADDR15 0x3bf 352 353 /* Debug/Trace Registers (shared with Debug Mode) */ 354 #define CSR_TSELECT 0x7a0 355 #define CSR_TDATA1 0x7a1 356 #define CSR_TDATA2 0x7a2 357 #define CSR_TDATA3 0x7a3 358 #define CSR_TINFO 0x7a4 359 #define CSR_MCONTEXT 0x7a8 360 361 /* Debug Mode Registers */ 362 #define CSR_DCSR 0x7b0 363 #define CSR_DPC 0x7b1 364 #define CSR_DSCRATCH 0x7b2 365 366 /* Performance Counters */ 367 #define CSR_MHPMCOUNTER3 0xb03 368 #define CSR_MHPMCOUNTER4 0xb04 369 #define CSR_MHPMCOUNTER5 0xb05 370 #define CSR_MHPMCOUNTER6 0xb06 371 #define CSR_MHPMCOUNTER7 0xb07 372 #define CSR_MHPMCOUNTER8 0xb08 373 #define CSR_MHPMCOUNTER9 0xb09 374 #define CSR_MHPMCOUNTER10 0xb0a 375 #define CSR_MHPMCOUNTER11 0xb0b 376 #define CSR_MHPMCOUNTER12 0xb0c 377 #define CSR_MHPMCOUNTER13 0xb0d 378 #define CSR_MHPMCOUNTER14 0xb0e 379 #define CSR_MHPMCOUNTER15 0xb0f 380 #define CSR_MHPMCOUNTER16 0xb10 381 #define CSR_MHPMCOUNTER17 0xb11 382 #define CSR_MHPMCOUNTER18 0xb12 383 #define CSR_MHPMCOUNTER19 0xb13 384 #define CSR_MHPMCOUNTER20 0xb14 385 #define CSR_MHPMCOUNTER21 0xb15 386 #define CSR_MHPMCOUNTER22 0xb16 387 #define CSR_MHPMCOUNTER23 0xb17 388 #define CSR_MHPMCOUNTER24 0xb18 389 #define CSR_MHPMCOUNTER25 0xb19 390 #define CSR_MHPMCOUNTER26 0xb1a 391 #define CSR_MHPMCOUNTER27 0xb1b 392 #define CSR_MHPMCOUNTER28 0xb1c 393 #define CSR_MHPMCOUNTER29 0xb1d 394 #define CSR_MHPMCOUNTER30 0xb1e 395 #define CSR_MHPMCOUNTER31 0xb1f 396 397 /* Machine counter-inhibit register */ 398 #define CSR_MCOUNTINHIBIT 0x320 399 400 /* Machine counter configuration registers */ 401 #define CSR_MCYCLECFG 0x321 402 #define CSR_MINSTRETCFG 0x322 403 404 #define CSR_MHPMEVENT3 0x323 405 #define CSR_MHPMEVENT4 0x324 406 #define CSR_MHPMEVENT5 0x325 407 #define CSR_MHPMEVENT6 0x326 408 #define CSR_MHPMEVENT7 0x327 409 #define CSR_MHPMEVENT8 0x328 410 #define CSR_MHPMEVENT9 0x329 411 #define CSR_MHPMEVENT10 0x32a 412 #define CSR_MHPMEVENT11 0x32b 413 #define CSR_MHPMEVENT12 0x32c 414 #define CSR_MHPMEVENT13 0x32d 415 #define CSR_MHPMEVENT14 0x32e 416 #define CSR_MHPMEVENT15 0x32f 417 #define CSR_MHPMEVENT16 0x330 418 #define CSR_MHPMEVENT17 0x331 419 #define CSR_MHPMEVENT18 0x332 420 #define CSR_MHPMEVENT19 0x333 421 #define CSR_MHPMEVENT20 0x334 422 #define CSR_MHPMEVENT21 0x335 423 #define CSR_MHPMEVENT22 0x336 424 #define CSR_MHPMEVENT23 0x337 425 #define CSR_MHPMEVENT24 0x338 426 #define CSR_MHPMEVENT25 0x339 427 #define CSR_MHPMEVENT26 0x33a 428 #define CSR_MHPMEVENT27 0x33b 429 #define CSR_MHPMEVENT28 0x33c 430 #define CSR_MHPMEVENT29 0x33d 431 #define CSR_MHPMEVENT30 0x33e 432 #define CSR_MHPMEVENT31 0x33f 433 434 #define CSR_MCYCLECFGH 0x721 435 #define CSR_MINSTRETCFGH 0x722 436 437 #define CSR_MHPMEVENT3H 0x723 438 #define CSR_MHPMEVENT4H 0x724 439 #define CSR_MHPMEVENT5H 0x725 440 #define CSR_MHPMEVENT6H 0x726 441 #define CSR_MHPMEVENT7H 0x727 442 #define CSR_MHPMEVENT8H 0x728 443 #define CSR_MHPMEVENT9H 0x729 444 #define CSR_MHPMEVENT10H 0x72a 445 #define CSR_MHPMEVENT11H 0x72b 446 #define CSR_MHPMEVENT12H 0x72c 447 #define CSR_MHPMEVENT13H 0x72d 448 #define CSR_MHPMEVENT14H 0x72e 449 #define CSR_MHPMEVENT15H 0x72f 450 #define CSR_MHPMEVENT16H 0x730 451 #define CSR_MHPMEVENT17H 0x731 452 #define CSR_MHPMEVENT18H 0x732 453 #define CSR_MHPMEVENT19H 0x733 454 #define CSR_MHPMEVENT20H 0x734 455 #define CSR_MHPMEVENT21H 0x735 456 #define CSR_MHPMEVENT22H 0x736 457 #define CSR_MHPMEVENT23H 0x737 458 #define CSR_MHPMEVENT24H 0x738 459 #define CSR_MHPMEVENT25H 0x739 460 #define CSR_MHPMEVENT26H 0x73a 461 #define CSR_MHPMEVENT27H 0x73b 462 #define CSR_MHPMEVENT28H 0x73c 463 #define CSR_MHPMEVENT29H 0x73d 464 #define CSR_MHPMEVENT30H 0x73e 465 #define CSR_MHPMEVENT31H 0x73f 466 467 #define CSR_MHPMCOUNTER3H 0xb83 468 #define CSR_MHPMCOUNTER4H 0xb84 469 #define CSR_MHPMCOUNTER5H 0xb85 470 #define CSR_MHPMCOUNTER6H 0xb86 471 #define CSR_MHPMCOUNTER7H 0xb87 472 #define CSR_MHPMCOUNTER8H 0xb88 473 #define CSR_MHPMCOUNTER9H 0xb89 474 #define CSR_MHPMCOUNTER10H 0xb8a 475 #define CSR_MHPMCOUNTER11H 0xb8b 476 #define CSR_MHPMCOUNTER12H 0xb8c 477 #define CSR_MHPMCOUNTER13H 0xb8d 478 #define CSR_MHPMCOUNTER14H 0xb8e 479 #define CSR_MHPMCOUNTER15H 0xb8f 480 #define CSR_MHPMCOUNTER16H 0xb90 481 #define CSR_MHPMCOUNTER17H 0xb91 482 #define CSR_MHPMCOUNTER18H 0xb92 483 #define CSR_MHPMCOUNTER19H 0xb93 484 #define CSR_MHPMCOUNTER20H 0xb94 485 #define CSR_MHPMCOUNTER21H 0xb95 486 #define CSR_MHPMCOUNTER22H 0xb96 487 #define CSR_MHPMCOUNTER23H 0xb97 488 #define CSR_MHPMCOUNTER24H 0xb98 489 #define CSR_MHPMCOUNTER25H 0xb99 490 #define CSR_MHPMCOUNTER26H 0xb9a 491 #define CSR_MHPMCOUNTER27H 0xb9b 492 #define CSR_MHPMCOUNTER28H 0xb9c 493 #define CSR_MHPMCOUNTER29H 0xb9d 494 #define CSR_MHPMCOUNTER30H 0xb9e 495 #define CSR_MHPMCOUNTER31H 0xb9f 496 497 /* 498 * User PointerMasking registers 499 * NB: actual CSR numbers might be changed in future 500 */ 501 #define CSR_UMTE 0x4c0 502 #define CSR_UPMMASK 0x4c1 503 #define CSR_UPMBASE 0x4c2 504 505 /* 506 * Machine PointerMasking registers 507 * NB: actual CSR numbers might be changed in future 508 */ 509 #define CSR_MMTE 0x3c0 510 #define CSR_MPMMASK 0x3c1 511 #define CSR_MPMBASE 0x3c2 512 513 /* 514 * Supervisor PointerMaster registers 515 * NB: actual CSR numbers might be changed in future 516 */ 517 #define CSR_SMTE 0x1c0 518 #define CSR_SPMMASK 0x1c1 519 #define CSR_SPMBASE 0x1c2 520 521 /* 522 * Hypervisor PointerMaster registers 523 * NB: actual CSR numbers might be changed in future 524 */ 525 #define CSR_VSMTE 0x2c0 526 #define CSR_VSPMMASK 0x2c1 527 #define CSR_VSPMBASE 0x2c2 528 #define CSR_SCOUNTOVF 0xda0 529 530 /* Crypto Extension */ 531 #define CSR_SEED 0x015 532 533 /* Zcmt Extension */ 534 #define CSR_JVT 0x017 535 536 /* mstatus CSR bits */ 537 #define MSTATUS_UIE 0x00000001 538 #define MSTATUS_SIE 0x00000002 539 #define MSTATUS_MIE 0x00000008 540 #define MSTATUS_UPIE 0x00000010 541 #define MSTATUS_SPIE 0x00000020 542 #define MSTATUS_UBE 0x00000040 543 #define MSTATUS_MPIE 0x00000080 544 #define MSTATUS_SPP 0x00000100 545 #define MSTATUS_VS 0x00000600 546 #define MSTATUS_MPP 0x00001800 547 #define MSTATUS_FS 0x00006000 548 #define MSTATUS_XS 0x00018000 549 #define MSTATUS_MPRV 0x00020000 550 #define MSTATUS_SUM 0x00040000 /* since: priv-1.10 */ 551 #define MSTATUS_MXR 0x00080000 552 #define MSTATUS_TVM 0x00100000 /* since: priv-1.10 */ 553 #define MSTATUS_TW 0x00200000 /* since: priv-1.10 */ 554 #define MSTATUS_TSR 0x00400000 /* since: priv-1.10 */ 555 #define MSTATUS_GVA 0x4000000000ULL 556 #define MSTATUS_MPV 0x8000000000ULL 557 558 #define MSTATUS64_UXL 0x0000000300000000ULL 559 #define MSTATUS64_SXL 0x0000000C00000000ULL 560 561 #define MSTATUS32_SD 0x80000000 562 #define MSTATUS64_SD 0x8000000000000000ULL 563 #define MSTATUSH128_SD 0x8000000000000000ULL 564 565 #define MISA32_MXL 0xC0000000 566 #define MISA64_MXL 0xC000000000000000ULL 567 568 typedef enum { 569 MXL_RV32 = 1, 570 MXL_RV64 = 2, 571 MXL_RV128 = 3, 572 } RISCVMXL; 573 574 /* sstatus CSR bits */ 575 #define SSTATUS_UIE 0x00000001 576 #define SSTATUS_SIE 0x00000002 577 #define SSTATUS_UPIE 0x00000010 578 #define SSTATUS_SPIE 0x00000020 579 #define SSTATUS_SPP 0x00000100 580 #define SSTATUS_VS 0x00000600 581 #define SSTATUS_FS 0x00006000 582 #define SSTATUS_XS 0x00018000 583 #define SSTATUS_SUM 0x00040000 /* since: priv-1.10 */ 584 #define SSTATUS_MXR 0x00080000 585 586 #define SSTATUS64_UXL 0x0000000300000000ULL 587 588 #define SSTATUS32_SD 0x80000000 589 #define SSTATUS64_SD 0x8000000000000000ULL 590 591 /* hstatus CSR bits */ 592 #define HSTATUS_VSBE 0x00000020 593 #define HSTATUS_GVA 0x00000040 594 #define HSTATUS_SPV 0x00000080 595 #define HSTATUS_SPVP 0x00000100 596 #define HSTATUS_HU 0x00000200 597 #define HSTATUS_VGEIN 0x0003F000 598 #define HSTATUS_VTVM 0x00100000 599 #define HSTATUS_VTW 0x00200000 600 #define HSTATUS_VTSR 0x00400000 601 #define HSTATUS_VSXL 0x300000000 602 603 #define HSTATUS32_WPRI 0xFF8FF87E 604 #define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL 605 606 #define COUNTEREN_CY (1 << 0) 607 #define COUNTEREN_TM (1 << 1) 608 #define COUNTEREN_IR (1 << 2) 609 #define COUNTEREN_HPM3 (1 << 3) 610 611 /* vsstatus CSR bits */ 612 #define VSSTATUS64_UXL 0x0000000300000000ULL 613 614 /* Privilege modes */ 615 #define PRV_U 0 616 #define PRV_S 1 617 #define PRV_RESERVED 2 618 #define PRV_M 3 619 620 /* RV32 satp CSR field masks */ 621 #define SATP32_MODE 0x80000000 622 #define SATP32_ASID 0x7fc00000 623 #define SATP32_PPN 0x003fffff 624 625 /* RV64 satp CSR field masks */ 626 #define SATP64_MODE 0xF000000000000000ULL 627 #define SATP64_ASID 0x0FFFF00000000000ULL 628 #define SATP64_PPN 0x00000FFFFFFFFFFFULL 629 630 /* VM modes (satp.mode) privileged ISA 1.10 */ 631 #define VM_1_10_MBARE 0 632 #define VM_1_10_SV32 1 633 #define VM_1_10_SV39 8 634 #define VM_1_10_SV48 9 635 #define VM_1_10_SV57 10 636 #define VM_1_10_SV64 11 637 638 /* Page table entry (PTE) fields */ 639 #define PTE_V 0x001 /* Valid */ 640 #define PTE_R 0x002 /* Read */ 641 #define PTE_W 0x004 /* Write */ 642 #define PTE_X 0x008 /* Execute */ 643 #define PTE_U 0x010 /* User */ 644 #define PTE_G 0x020 /* Global */ 645 #define PTE_A 0x040 /* Accessed */ 646 #define PTE_D 0x080 /* Dirty */ 647 #define PTE_SOFT 0x300 /* Reserved for Software */ 648 #define PTE_PBMT 0x6000000000000000ULL /* Page-based memory types */ 649 #define PTE_N 0x8000000000000000ULL /* NAPOT translation */ 650 #define PTE_RESERVED 0x1FC0000000000000ULL /* Reserved bits */ 651 #define PTE_ATTR (PTE_N | PTE_PBMT) /* All attributes bits */ 652 653 /* Page table PPN shift amount */ 654 #define PTE_PPN_SHIFT 10 655 656 /* Page table PPN mask */ 657 #define PTE_PPN_MASK 0x3FFFFFFFFFFC00ULL 658 659 /* Leaf page shift amount */ 660 #define PGSHIFT 12 661 662 /* Default Reset Vector address */ 663 #define DEFAULT_RSTVEC 0x1000 664 665 /* Exception causes */ 666 typedef enum RISCVException { 667 RISCV_EXCP_NONE = -1, /* sentinel value */ 668 RISCV_EXCP_INST_ADDR_MIS = 0x0, 669 RISCV_EXCP_INST_ACCESS_FAULT = 0x1, 670 RISCV_EXCP_ILLEGAL_INST = 0x2, 671 RISCV_EXCP_BREAKPOINT = 0x3, 672 RISCV_EXCP_LOAD_ADDR_MIS = 0x4, 673 RISCV_EXCP_LOAD_ACCESS_FAULT = 0x5, 674 RISCV_EXCP_STORE_AMO_ADDR_MIS = 0x6, 675 RISCV_EXCP_STORE_AMO_ACCESS_FAULT = 0x7, 676 RISCV_EXCP_U_ECALL = 0x8, 677 RISCV_EXCP_S_ECALL = 0x9, 678 RISCV_EXCP_VS_ECALL = 0xa, 679 RISCV_EXCP_M_ECALL = 0xb, 680 RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */ 681 RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */ 682 RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */ 683 RISCV_EXCP_SW_CHECK = 0x12, /* since: priv-1.13.0 */ 684 RISCV_EXCP_HW_ERR = 0x13, /* since: priv-1.13.0 */ 685 RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14, 686 RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15, 687 RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16, 688 RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT = 0x17, 689 RISCV_EXCP_SEMIHOST = 0x3f, 690 } RISCVException; 691 692 #define RISCV_EXCP_INT_FLAG 0x80000000 693 #define RISCV_EXCP_INT_MASK 0x7fffffff 694 695 /* Interrupt causes */ 696 #define IRQ_U_SOFT 0 697 #define IRQ_S_SOFT 1 698 #define IRQ_VS_SOFT 2 699 #define IRQ_M_SOFT 3 700 #define IRQ_U_TIMER 4 701 #define IRQ_S_TIMER 5 702 #define IRQ_VS_TIMER 6 703 #define IRQ_M_TIMER 7 704 #define IRQ_U_EXT 8 705 #define IRQ_S_EXT 9 706 #define IRQ_VS_EXT 10 707 #define IRQ_M_EXT 11 708 #define IRQ_S_GEXT 12 709 #define IRQ_PMU_OVF 13 710 #define IRQ_LOCAL_MAX 64 711 /* -1 is due to bit zero of hgeip and hgeie being ROZ. */ 712 #define IRQ_LOCAL_GUEST_MAX (TARGET_LONG_BITS - 1) 713 714 /* mip masks */ 715 #define MIP_USIP (1 << IRQ_U_SOFT) 716 #define MIP_SSIP (1 << IRQ_S_SOFT) 717 #define MIP_VSSIP (1 << IRQ_VS_SOFT) 718 #define MIP_MSIP (1 << IRQ_M_SOFT) 719 #define MIP_UTIP (1 << IRQ_U_TIMER) 720 #define MIP_STIP (1 << IRQ_S_TIMER) 721 #define MIP_VSTIP (1 << IRQ_VS_TIMER) 722 #define MIP_MTIP (1 << IRQ_M_TIMER) 723 #define MIP_UEIP (1 << IRQ_U_EXT) 724 #define MIP_SEIP (1 << IRQ_S_EXT) 725 #define MIP_VSEIP (1 << IRQ_VS_EXT) 726 #define MIP_MEIP (1 << IRQ_M_EXT) 727 #define MIP_SGEIP (1 << IRQ_S_GEXT) 728 #define MIP_LCOFIP (1 << IRQ_PMU_OVF) 729 730 /* sip masks */ 731 #define SIP_SSIP MIP_SSIP 732 #define SIP_STIP MIP_STIP 733 #define SIP_SEIP MIP_SEIP 734 #define SIP_LCOFIP MIP_LCOFIP 735 736 /* MIE masks */ 737 #define MIE_SEIE (1 << IRQ_S_EXT) 738 #define MIE_UEIE (1 << IRQ_U_EXT) 739 #define MIE_STIE (1 << IRQ_S_TIMER) 740 #define MIE_UTIE (1 << IRQ_U_TIMER) 741 #define MIE_SSIE (1 << IRQ_S_SOFT) 742 #define MIE_USIE (1 << IRQ_U_SOFT) 743 744 /* Machine constants */ 745 #define M_MODE_INTERRUPTS ((uint64_t)(MIP_MSIP | MIP_MTIP | MIP_MEIP)) 746 #define S_MODE_INTERRUPTS ((uint64_t)(MIP_SSIP | MIP_STIP | MIP_SEIP)) 747 #define VS_MODE_INTERRUPTS ((uint64_t)(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)) 748 #define HS_MODE_INTERRUPTS ((uint64_t)(MIP_SGEIP | VS_MODE_INTERRUPTS)) 749 750 /* General PointerMasking CSR bits */ 751 #define PM_ENABLE 0x00000001ULL 752 #define PM_CURRENT 0x00000002ULL 753 #define PM_INSN 0x00000004ULL 754 755 /* Execution environment configuration bits */ 756 #define MENVCFG_FIOM BIT(0) 757 #define MENVCFG_CBIE (3UL << 4) 758 #define MENVCFG_CBCFE BIT(6) 759 #define MENVCFG_CBZE BIT(7) 760 #define MENVCFG_ADUE (1ULL << 61) 761 #define MENVCFG_PBMTE (1ULL << 62) 762 #define MENVCFG_STCE (1ULL << 63) 763 764 /* For RV32 */ 765 #define MENVCFGH_ADUE BIT(29) 766 #define MENVCFGH_PBMTE BIT(30) 767 #define MENVCFGH_STCE BIT(31) 768 769 #define SENVCFG_FIOM MENVCFG_FIOM 770 #define SENVCFG_CBIE MENVCFG_CBIE 771 #define SENVCFG_CBCFE MENVCFG_CBCFE 772 #define SENVCFG_CBZE MENVCFG_CBZE 773 774 #define HENVCFG_FIOM MENVCFG_FIOM 775 #define HENVCFG_CBIE MENVCFG_CBIE 776 #define HENVCFG_CBCFE MENVCFG_CBCFE 777 #define HENVCFG_CBZE MENVCFG_CBZE 778 #define HENVCFG_ADUE MENVCFG_ADUE 779 #define HENVCFG_PBMTE MENVCFG_PBMTE 780 #define HENVCFG_STCE MENVCFG_STCE 781 782 /* For RV32 */ 783 #define HENVCFGH_ADUE MENVCFGH_ADUE 784 #define HENVCFGH_PBMTE MENVCFGH_PBMTE 785 #define HENVCFGH_STCE MENVCFGH_STCE 786 787 /* Offsets for every pair of control bits per each priv level */ 788 #define XS_OFFSET 0ULL 789 #define U_OFFSET 2ULL 790 #define S_OFFSET 5ULL 791 #define M_OFFSET 8ULL 792 793 #define PM_XS_BITS (EXT_STATUS_MASK << XS_OFFSET) 794 #define U_PM_ENABLE (PM_ENABLE << U_OFFSET) 795 #define U_PM_CURRENT (PM_CURRENT << U_OFFSET) 796 #define U_PM_INSN (PM_INSN << U_OFFSET) 797 #define S_PM_ENABLE (PM_ENABLE << S_OFFSET) 798 #define S_PM_CURRENT (PM_CURRENT << S_OFFSET) 799 #define S_PM_INSN (PM_INSN << S_OFFSET) 800 #define M_PM_ENABLE (PM_ENABLE << M_OFFSET) 801 #define M_PM_CURRENT (PM_CURRENT << M_OFFSET) 802 #define M_PM_INSN (PM_INSN << M_OFFSET) 803 804 /* mmte CSR bits */ 805 #define MMTE_PM_XS_BITS PM_XS_BITS 806 #define MMTE_U_PM_ENABLE U_PM_ENABLE 807 #define MMTE_U_PM_CURRENT U_PM_CURRENT 808 #define MMTE_U_PM_INSN U_PM_INSN 809 #define MMTE_S_PM_ENABLE S_PM_ENABLE 810 #define MMTE_S_PM_CURRENT S_PM_CURRENT 811 #define MMTE_S_PM_INSN S_PM_INSN 812 #define MMTE_M_PM_ENABLE M_PM_ENABLE 813 #define MMTE_M_PM_CURRENT M_PM_CURRENT 814 #define MMTE_M_PM_INSN M_PM_INSN 815 #define MMTE_MASK (MMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | MMTE_U_PM_INSN | \ 816 MMTE_S_PM_ENABLE | MMTE_S_PM_CURRENT | MMTE_S_PM_INSN | \ 817 MMTE_M_PM_ENABLE | MMTE_M_PM_CURRENT | MMTE_M_PM_INSN | \ 818 MMTE_PM_XS_BITS) 819 820 /* (v)smte CSR bits */ 821 #define SMTE_PM_XS_BITS PM_XS_BITS 822 #define SMTE_U_PM_ENABLE U_PM_ENABLE 823 #define SMTE_U_PM_CURRENT U_PM_CURRENT 824 #define SMTE_U_PM_INSN U_PM_INSN 825 #define SMTE_S_PM_ENABLE S_PM_ENABLE 826 #define SMTE_S_PM_CURRENT S_PM_CURRENT 827 #define SMTE_S_PM_INSN S_PM_INSN 828 #define SMTE_MASK (SMTE_U_PM_ENABLE | SMTE_U_PM_CURRENT | SMTE_U_PM_INSN | \ 829 SMTE_S_PM_ENABLE | SMTE_S_PM_CURRENT | SMTE_S_PM_INSN | \ 830 SMTE_PM_XS_BITS) 831 832 /* umte CSR bits */ 833 #define UMTE_U_PM_ENABLE U_PM_ENABLE 834 #define UMTE_U_PM_CURRENT U_PM_CURRENT 835 #define UMTE_U_PM_INSN U_PM_INSN 836 #define UMTE_MASK (UMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | UMTE_U_PM_INSN) 837 838 /* MISELECT, SISELECT, and VSISELECT bits (AIA) */ 839 #define ISELECT_IPRIO0 0x30 840 #define ISELECT_IPRIO15 0x3f 841 #define ISELECT_IMSIC_EIDELIVERY 0x70 842 #define ISELECT_IMSIC_EITHRESHOLD 0x72 843 #define ISELECT_IMSIC_EIP0 0x80 844 #define ISELECT_IMSIC_EIP63 0xbf 845 #define ISELECT_IMSIC_EIE0 0xc0 846 #define ISELECT_IMSIC_EIE63 0xff 847 #define ISELECT_IMSIC_FIRST ISELECT_IMSIC_EIDELIVERY 848 #define ISELECT_IMSIC_LAST ISELECT_IMSIC_EIE63 849 #define ISELECT_MASK 0x1ff 850 851 /* Dummy [M|S|VS]ISELECT value for emulating [M|S|VS]TOPEI CSRs */ 852 #define ISELECT_IMSIC_TOPEI (ISELECT_MASK + 1) 853 854 /* IMSIC bits (AIA) */ 855 #define IMSIC_TOPEI_IID_SHIFT 16 856 #define IMSIC_TOPEI_IID_MASK 0x7ff 857 #define IMSIC_TOPEI_IPRIO_MASK 0x7ff 858 #define IMSIC_EIPx_BITS 32 859 #define IMSIC_EIEx_BITS 32 860 861 /* MTOPI and STOPI bits (AIA) */ 862 #define TOPI_IID_SHIFT 16 863 #define TOPI_IID_MASK 0xfff 864 #define TOPI_IPRIO_MASK 0xff 865 866 /* Interrupt priority bits (AIA) */ 867 #define IPRIO_IRQ_BITS 8 868 #define IPRIO_MMAXIPRIO 255 869 #define IPRIO_DEFAULT_UPPER 4 870 #define IPRIO_DEFAULT_MIDDLE (IPRIO_DEFAULT_UPPER + 12) 871 #define IPRIO_DEFAULT_M IPRIO_DEFAULT_MIDDLE 872 #define IPRIO_DEFAULT_S (IPRIO_DEFAULT_M + 3) 873 #define IPRIO_DEFAULT_SGEXT (IPRIO_DEFAULT_S + 3) 874 #define IPRIO_DEFAULT_VS (IPRIO_DEFAULT_SGEXT + 1) 875 #define IPRIO_DEFAULT_LOWER (IPRIO_DEFAULT_VS + 3) 876 877 /* HVICTL bits (AIA) */ 878 #define HVICTL_VTI 0x40000000 879 #define HVICTL_IID 0x0fff0000 880 #define HVICTL_IPRIOM 0x00000100 881 #define HVICTL_IPRIO 0x000000ff 882 #define HVICTL_VALID_MASK \ 883 (HVICTL_VTI | HVICTL_IID | HVICTL_IPRIOM | HVICTL_IPRIO) 884 885 /* seed CSR bits */ 886 #define SEED_OPST (0b11 << 30) 887 #define SEED_OPST_BIST (0b00 << 30) 888 #define SEED_OPST_WAIT (0b01 << 30) 889 #define SEED_OPST_ES16 (0b10 << 30) 890 #define SEED_OPST_DEAD (0b11 << 30) 891 /* PMU related bits */ 892 #define MIE_LCOFIE (1 << IRQ_PMU_OVF) 893 894 #define MCYCLECFG_BIT_MINH BIT_ULL(62) 895 #define MCYCLECFGH_BIT_MINH BIT(30) 896 #define MCYCLECFG_BIT_SINH BIT_ULL(61) 897 #define MCYCLECFGH_BIT_SINH BIT(29) 898 #define MCYCLECFG_BIT_UINH BIT_ULL(60) 899 #define MCYCLECFGH_BIT_UINH BIT(28) 900 #define MCYCLECFG_BIT_VSINH BIT_ULL(59) 901 #define MCYCLECFGH_BIT_VSINH BIT(27) 902 #define MCYCLECFG_BIT_VUINH BIT_ULL(58) 903 #define MCYCLECFGH_BIT_VUINH BIT(26) 904 905 #define MINSTRETCFG_BIT_MINH BIT_ULL(62) 906 #define MINSTRETCFGH_BIT_MINH BIT(30) 907 #define MINSTRETCFG_BIT_SINH BIT_ULL(61) 908 #define MINSTRETCFGH_BIT_SINH BIT(29) 909 #define MINSTRETCFG_BIT_UINH BIT_ULL(60) 910 #define MINSTRETCFGH_BIT_UINH BIT(28) 911 #define MINSTRETCFG_BIT_VSINH BIT_ULL(59) 912 #define MINSTRETCFGH_BIT_VSINH BIT(27) 913 #define MINSTRETCFG_BIT_VUINH BIT_ULL(58) 914 #define MINSTRETCFGH_BIT_VUINH BIT(26) 915 916 #define MHPMEVENT_BIT_OF BIT_ULL(63) 917 #define MHPMEVENTH_BIT_OF BIT(31) 918 #define MHPMEVENT_BIT_MINH BIT_ULL(62) 919 #define MHPMEVENTH_BIT_MINH BIT(30) 920 #define MHPMEVENT_BIT_SINH BIT_ULL(61) 921 #define MHPMEVENTH_BIT_SINH BIT(29) 922 #define MHPMEVENT_BIT_UINH BIT_ULL(60) 923 #define MHPMEVENTH_BIT_UINH BIT(28) 924 #define MHPMEVENT_BIT_VSINH BIT_ULL(59) 925 #define MHPMEVENTH_BIT_VSINH BIT(27) 926 #define MHPMEVENT_BIT_VUINH BIT_ULL(58) 927 #define MHPMEVENTH_BIT_VUINH BIT(26) 928 929 #define MHPMEVENT_FILTER_MASK (MHPMEVENT_BIT_MINH | \ 930 MHPMEVENT_BIT_SINH | \ 931 MHPMEVENT_BIT_UINH | \ 932 MHPMEVENT_BIT_VSINH | \ 933 MHPMEVENT_BIT_VUINH) 934 935 #define MHPMEVENTH_FILTER_MASK (MHPMEVENTH_BIT_MINH | \ 936 MHPMEVENTH_BIT_SINH | \ 937 MHPMEVENTH_BIT_UINH | \ 938 MHPMEVENTH_BIT_VSINH | \ 939 MHPMEVENTH_BIT_VUINH) 940 941 #define MHPMEVENT_SSCOF_MASK _ULL(0xFFFF000000000000) 942 #define MHPMEVENT_IDX_MASK 0xFFFFF 943 #define MHPMEVENT_SSCOF_RESVD 16 944 945 /* JVT CSR bits */ 946 #define JVT_MODE 0x3F 947 #define JVT_BASE (~0x3F) 948 949 /* Debug Sdtrig CSR masks */ 950 #define MCONTEXT32 0x0000003F 951 #define MCONTEXT64 0x0000000000001FFFULL 952 #define MCONTEXT32_HCONTEXT 0x0000007F 953 #define MCONTEXT64_HCONTEXT 0x0000000000003FFFULL 954 #endif 955