1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef RISCV_CPU_H 21 #define RISCV_CPU_H 22 23 #include "hw/core/cpu.h" 24 #include "hw/registerfields.h" 25 #include "hw/qdev-properties.h" 26 #include "exec/cpu-defs.h" 27 #include "qemu/cpu-float.h" 28 #include "qom/object.h" 29 #include "qemu/int128.h" 30 #include "cpu_bits.h" 31 #include "cpu_cfg.h" 32 #include "qapi/qapi-types-common.h" 33 #include "cpu-qom.h" 34 35 typedef struct CPUArchState CPURISCVState; 36 37 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU 38 39 #if defined(TARGET_RISCV32) 40 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 41 #elif defined(TARGET_RISCV64) 42 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 43 #endif 44 45 #define TCG_GUEST_DEFAULT_MO 0 46 47 /* 48 * RISC-V-specific extra insn start words: 49 * 1: Original instruction opcode 50 */ 51 #define TARGET_INSN_START_EXTRA_WORDS 1 52 53 #define RV(x) ((target_ulong)1 << (x - 'A')) 54 55 /* 56 * Update misa_bits[], misa_ext_info_arr[] and misa_ext_cfgs[] 57 * when adding new MISA bits here. 58 */ 59 #define RVI RV('I') 60 #define RVE RV('E') /* E and I are mutually exclusive */ 61 #define RVM RV('M') 62 #define RVA RV('A') 63 #define RVF RV('F') 64 #define RVD RV('D') 65 #define RVV RV('V') 66 #define RVC RV('C') 67 #define RVS RV('S') 68 #define RVU RV('U') 69 #define RVH RV('H') 70 #define RVJ RV('J') 71 #define RVG RV('G') 72 #define RVB RV('B') 73 74 extern const uint32_t misa_bits[]; 75 const char *riscv_get_misa_ext_name(uint32_t bit); 76 const char *riscv_get_misa_ext_description(uint32_t bit); 77 78 #define CPU_CFG_OFFSET(_prop) offsetof(struct RISCVCPUConfig, _prop) 79 80 typedef struct riscv_cpu_profile { 81 struct riscv_cpu_profile *parent; 82 const char *name; 83 uint32_t misa_ext; 84 bool enabled; 85 bool user_set; 86 int priv_spec; 87 int satp_mode; 88 const int32_t ext_offsets[]; 89 } RISCVCPUProfile; 90 91 #define RISCV_PROFILE_EXT_LIST_END -1 92 #define RISCV_PROFILE_ATTR_UNUSED -1 93 94 extern RISCVCPUProfile *riscv_profiles[]; 95 96 /* Privileged specification version */ 97 #define PRIV_VER_1_10_0_STR "v1.10.0" 98 #define PRIV_VER_1_11_0_STR "v1.11.0" 99 #define PRIV_VER_1_12_0_STR "v1.12.0" 100 enum { 101 PRIV_VERSION_1_10_0 = 0, 102 PRIV_VERSION_1_11_0, 103 PRIV_VERSION_1_12_0, 104 105 PRIV_VERSION_LATEST = PRIV_VERSION_1_12_0, 106 }; 107 108 #define VEXT_VERSION_1_00_0 0x00010000 109 110 enum { 111 TRANSLATE_SUCCESS, 112 TRANSLATE_FAIL, 113 TRANSLATE_PMP_FAIL, 114 TRANSLATE_G_STAGE_FAIL 115 }; 116 117 /* Extension context status */ 118 typedef enum { 119 EXT_STATUS_DISABLED = 0, 120 EXT_STATUS_INITIAL, 121 EXT_STATUS_CLEAN, 122 EXT_STATUS_DIRTY, 123 } RISCVExtStatus; 124 125 #define MMU_USER_IDX 3 126 127 #define MAX_RISCV_PMPS (16) 128 129 #if !defined(CONFIG_USER_ONLY) 130 #include "pmp.h" 131 #include "debug.h" 132 #endif 133 134 #define RV_VLEN_MAX 1024 135 #define RV_MAX_MHPMEVENTS 32 136 #define RV_MAX_MHPMCOUNTERS 32 137 138 FIELD(VTYPE, VLMUL, 0, 3) 139 FIELD(VTYPE, VSEW, 3, 3) 140 FIELD(VTYPE, VTA, 6, 1) 141 FIELD(VTYPE, VMA, 7, 1) 142 FIELD(VTYPE, VEDIV, 8, 2) 143 FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) 144 145 typedef struct PMUCTRState { 146 /* Current value of a counter */ 147 target_ulong mhpmcounter_val; 148 /* Current value of a counter in RV32 */ 149 target_ulong mhpmcounterh_val; 150 /* Snapshot values of counter */ 151 target_ulong mhpmcounter_prev; 152 /* Snapshort value of a counter in RV32 */ 153 target_ulong mhpmcounterh_prev; 154 bool started; 155 /* Value beyond UINT32_MAX/UINT64_MAX before overflow interrupt trigger */ 156 target_ulong irq_overflow_left; 157 } PMUCTRState; 158 159 struct CPUArchState { 160 target_ulong gpr[32]; 161 target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ 162 163 /* vector coprocessor state. */ 164 uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); 165 target_ulong vxrm; 166 target_ulong vxsat; 167 target_ulong vl; 168 target_ulong vstart; 169 target_ulong vtype; 170 bool vill; 171 172 target_ulong pc; 173 target_ulong load_res; 174 target_ulong load_val; 175 176 /* Floating-Point state */ 177 uint64_t fpr[32]; /* assume both F and D extensions */ 178 target_ulong frm; 179 float_status fp_status; 180 181 target_ulong badaddr; 182 target_ulong bins; 183 184 target_ulong guest_phys_fault_addr; 185 186 target_ulong priv_ver; 187 target_ulong vext_ver; 188 189 /* RISCVMXL, but uint32_t for vmstate migration */ 190 uint32_t misa_mxl; /* current mxl */ 191 uint32_t misa_mxl_max; /* max mxl for this cpu */ 192 uint32_t misa_ext; /* current extensions */ 193 uint32_t misa_ext_mask; /* max ext for this cpu */ 194 uint32_t xl; /* current xlen */ 195 196 /* 128-bit helpers upper part return value */ 197 target_ulong retxh; 198 199 target_ulong jvt; 200 201 #ifdef CONFIG_USER_ONLY 202 uint32_t elf_flags; 203 #endif 204 205 #ifndef CONFIG_USER_ONLY 206 target_ulong priv; 207 /* This contains QEMU specific information about the virt state. */ 208 bool virt_enabled; 209 target_ulong geilen; 210 uint64_t resetvec; 211 212 target_ulong mhartid; 213 /* 214 * For RV32 this is 32-bit mstatus and 32-bit mstatush. 215 * For RV64 this is a 64-bit mstatus. 216 */ 217 uint64_t mstatus; 218 219 uint64_t mip; 220 /* 221 * MIP contains the software writable version of SEIP ORed with the 222 * external interrupt value. The MIP register is always up-to-date. 223 * To keep track of the current source, we also save booleans of the values 224 * here. 225 */ 226 bool external_seip; 227 bool software_seip; 228 229 uint64_t miclaim; 230 231 uint64_t mie; 232 uint64_t mideleg; 233 234 /* 235 * When mideleg[i]=0 and mvien[i]=1, sie[i] is no more 236 * alias of mie[i] and needs to be maintained separately. 237 */ 238 uint64_t sie; 239 240 /* 241 * When hideleg[i]=0 and hvien[i]=1, vsie[i] is no more 242 * alias of sie[i] (mie[i]) and needs to be maintained separately. 243 */ 244 uint64_t vsie; 245 246 target_ulong satp; /* since: priv-1.10.0 */ 247 target_ulong stval; 248 target_ulong medeleg; 249 250 target_ulong stvec; 251 target_ulong sepc; 252 target_ulong scause; 253 254 target_ulong mtvec; 255 target_ulong mepc; 256 target_ulong mcause; 257 target_ulong mtval; /* since: priv-1.10.0 */ 258 259 /* Machine and Supervisor interrupt priorities */ 260 uint8_t miprio[64]; 261 uint8_t siprio[64]; 262 263 /* AIA CSRs */ 264 target_ulong miselect; 265 target_ulong siselect; 266 uint64_t mvien; 267 uint64_t mvip; 268 269 /* Hypervisor CSRs */ 270 target_ulong hstatus; 271 target_ulong hedeleg; 272 uint64_t hideleg; 273 target_ulong hcounteren; 274 target_ulong htval; 275 target_ulong htinst; 276 target_ulong hgatp; 277 target_ulong hgeie; 278 target_ulong hgeip; 279 uint64_t htimedelta; 280 uint64_t hvien; 281 282 /* 283 * Bits VSSIP, VSTIP and VSEIP in hvip are maintained in mip. Other bits 284 * from 0:12 are reserved. Bits 13:63 are not aliased and must be separately 285 * maintain in hvip. 286 */ 287 uint64_t hvip; 288 289 /* Hypervisor controlled virtual interrupt priorities */ 290 target_ulong hvictl; 291 uint8_t hviprio[64]; 292 293 /* Upper 64-bits of 128-bit CSRs */ 294 uint64_t mscratchh; 295 uint64_t sscratchh; 296 297 /* Virtual CSRs */ 298 /* 299 * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. 300 * For RV64 this is a 64-bit vsstatus. 301 */ 302 uint64_t vsstatus; 303 target_ulong vstvec; 304 target_ulong vsscratch; 305 target_ulong vsepc; 306 target_ulong vscause; 307 target_ulong vstval; 308 target_ulong vsatp; 309 310 /* AIA VS-mode CSRs */ 311 target_ulong vsiselect; 312 313 target_ulong mtval2; 314 target_ulong mtinst; 315 316 /* HS Backup CSRs */ 317 target_ulong stvec_hs; 318 target_ulong sscratch_hs; 319 target_ulong sepc_hs; 320 target_ulong scause_hs; 321 target_ulong stval_hs; 322 target_ulong satp_hs; 323 uint64_t mstatus_hs; 324 325 /* 326 * Signals whether the current exception occurred with two-stage address 327 * translation active. 328 */ 329 bool two_stage_lookup; 330 /* 331 * Signals whether the current exception occurred while doing two-stage 332 * address translation for the VS-stage page table walk. 333 */ 334 bool two_stage_indirect_lookup; 335 336 target_ulong scounteren; 337 target_ulong mcounteren; 338 339 target_ulong mcountinhibit; 340 341 /* PMU counter state */ 342 PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS]; 343 344 /* PMU event selector configured values. First three are unused */ 345 target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS]; 346 347 /* PMU event selector configured values for RV32 */ 348 target_ulong mhpmeventh_val[RV_MAX_MHPMEVENTS]; 349 350 target_ulong sscratch; 351 target_ulong mscratch; 352 353 /* Sstc CSRs */ 354 uint64_t stimecmp; 355 356 uint64_t vstimecmp; 357 358 /* physical memory protection */ 359 pmp_table_t pmp_state; 360 target_ulong mseccfg; 361 362 /* trigger module */ 363 target_ulong trigger_cur; 364 target_ulong tdata1[RV_MAX_TRIGGERS]; 365 target_ulong tdata2[RV_MAX_TRIGGERS]; 366 target_ulong tdata3[RV_MAX_TRIGGERS]; 367 struct CPUBreakpoint *cpu_breakpoint[RV_MAX_TRIGGERS]; 368 struct CPUWatchpoint *cpu_watchpoint[RV_MAX_TRIGGERS]; 369 QEMUTimer *itrigger_timer[RV_MAX_TRIGGERS]; 370 int64_t last_icount; 371 bool itrigger_enabled; 372 373 /* machine specific rdtime callback */ 374 uint64_t (*rdtime_fn)(void *); 375 void *rdtime_fn_arg; 376 377 /* machine specific AIA ireg read-modify-write callback */ 378 #define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \ 379 ((((__xlen) & 0xff) << 24) | \ 380 (((__vgein) & 0x3f) << 20) | \ 381 (((__virt) & 0x1) << 18) | \ 382 (((__priv) & 0x3) << 16) | \ 383 (__isel & 0xffff)) 384 #define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff) 385 #define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3) 386 #define AIA_IREG_VIRT(__ireg) (((__ireg) >> 18) & 0x1) 387 #define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 20) & 0x3f) 388 #define AIA_IREG_XLEN(__ireg) (((__ireg) >> 24) & 0xff) 389 int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg, 390 target_ulong *val, target_ulong new_val, target_ulong write_mask); 391 void *aia_ireg_rmw_fn_arg[4]; 392 393 /* True if in debugger mode. */ 394 bool debugger; 395 396 /* 397 * CSRs for PointerMasking extension 398 */ 399 target_ulong mmte; 400 target_ulong mpmmask; 401 target_ulong mpmbase; 402 target_ulong spmmask; 403 target_ulong spmbase; 404 target_ulong upmmask; 405 target_ulong upmbase; 406 407 /* CSRs for execution environment configuration */ 408 uint64_t menvcfg; 409 uint64_t mstateen[SMSTATEEN_MAX_COUNT]; 410 uint64_t hstateen[SMSTATEEN_MAX_COUNT]; 411 uint64_t sstateen[SMSTATEEN_MAX_COUNT]; 412 target_ulong senvcfg; 413 uint64_t henvcfg; 414 #endif 415 target_ulong cur_pmmask; 416 target_ulong cur_pmbase; 417 418 /* Fields from here on are preserved across CPU reset. */ 419 QEMUTimer *stimer; /* Internal timer for S-mode interrupt */ 420 QEMUTimer *vstimer; /* Internal timer for VS-mode interrupt */ 421 bool vstime_irq; 422 423 hwaddr kernel_addr; 424 hwaddr fdt_addr; 425 426 #ifdef CONFIG_KVM 427 /* kvm timer */ 428 bool kvm_timer_dirty; 429 uint64_t kvm_timer_time; 430 uint64_t kvm_timer_compare; 431 uint64_t kvm_timer_state; 432 uint64_t kvm_timer_frequency; 433 #endif /* CONFIG_KVM */ 434 }; 435 436 /* 437 * RISCVCPU: 438 * @env: #CPURISCVState 439 * 440 * A RISCV CPU. 441 */ 442 struct ArchCPU { 443 CPUState parent_obj; 444 445 CPURISCVState env; 446 447 char *dyn_csr_xml; 448 char *dyn_vreg_xml; 449 450 /* Configuration Settings */ 451 RISCVCPUConfig cfg; 452 453 QEMUTimer *pmu_timer; 454 /* A bitmask of Available programmable counters */ 455 uint32_t pmu_avail_ctrs; 456 /* Mapping of events to counters */ 457 GHashTable *pmu_event_ctr_map; 458 }; 459 460 /** 461 * RISCVCPUClass: 462 * @parent_realize: The parent class' realize handler. 463 * @parent_phases: The parent class' reset phase handlers. 464 * 465 * A RISCV CPU model. 466 */ 467 struct RISCVCPUClass { 468 CPUClass parent_class; 469 470 DeviceRealize parent_realize; 471 ResettablePhases parent_phases; 472 }; 473 474 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) 475 { 476 return (env->misa_ext & ext) != 0; 477 } 478 479 #include "cpu_user.h" 480 481 extern const char * const riscv_int_regnames[]; 482 extern const char * const riscv_int_regnamesh[]; 483 extern const char * const riscv_fpr_regnames[]; 484 485 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); 486 void riscv_cpu_do_interrupt(CPUState *cpu); 487 int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 488 int cpuid, DumpState *s); 489 int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 490 int cpuid, DumpState *s); 491 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 492 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 493 int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero); 494 uint8_t riscv_cpu_default_priority(int irq); 495 uint64_t riscv_cpu_all_pending(CPURISCVState *env); 496 int riscv_cpu_mirq_pending(CPURISCVState *env); 497 int riscv_cpu_sirq_pending(CPURISCVState *env); 498 int riscv_cpu_vsirq_pending(CPURISCVState *env); 499 bool riscv_cpu_fp_enabled(CPURISCVState *env); 500 target_ulong riscv_cpu_get_geilen(CPURISCVState *env); 501 void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); 502 bool riscv_cpu_vector_enabled(CPURISCVState *env); 503 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); 504 int riscv_env_mmu_index(CPURISCVState *env, bool ifetch); 505 G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 506 MMUAccessType access_type, 507 int mmu_idx, uintptr_t retaddr); 508 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 509 MMUAccessType access_type, int mmu_idx, 510 bool probe, uintptr_t retaddr); 511 char *riscv_isa_string(RISCVCPU *cpu); 512 513 #ifndef CONFIG_USER_ONLY 514 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 515 vaddr addr, unsigned size, 516 MMUAccessType access_type, 517 int mmu_idx, MemTxAttrs attrs, 518 MemTxResult response, uintptr_t retaddr); 519 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 520 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); 521 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); 522 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); 523 uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask, 524 uint64_t value); 525 void riscv_cpu_interrupt(CPURISCVState *env); 526 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ 527 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), 528 void *arg); 529 void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, 530 int (*rmw_fn)(void *arg, 531 target_ulong reg, 532 target_ulong *val, 533 target_ulong new_val, 534 target_ulong write_mask), 535 void *rmw_fn_arg); 536 537 RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit); 538 #endif 539 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); 540 541 void riscv_translate_init(void); 542 G_NORETURN void riscv_raise_exception(CPURISCVState *env, 543 uint32_t exception, uintptr_t pc); 544 545 target_ulong riscv_cpu_get_fflags(CPURISCVState *env); 546 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); 547 548 #include "exec/cpu-all.h" 549 550 FIELD(TB_FLAGS, MEM_IDX, 0, 3) 551 FIELD(TB_FLAGS, FS, 3, 2) 552 /* Vector flags */ 553 FIELD(TB_FLAGS, VS, 5, 2) 554 FIELD(TB_FLAGS, LMUL, 7, 3) 555 FIELD(TB_FLAGS, SEW, 10, 3) 556 FIELD(TB_FLAGS, VL_EQ_VLMAX, 13, 1) 557 FIELD(TB_FLAGS, VILL, 14, 1) 558 FIELD(TB_FLAGS, VSTART_EQ_ZERO, 15, 1) 559 /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ 560 FIELD(TB_FLAGS, XL, 16, 2) 561 /* If PointerMasking should be applied */ 562 FIELD(TB_FLAGS, PM_MASK_ENABLED, 18, 1) 563 FIELD(TB_FLAGS, PM_BASE_ENABLED, 19, 1) 564 FIELD(TB_FLAGS, VTA, 20, 1) 565 FIELD(TB_FLAGS, VMA, 21, 1) 566 /* Native debug itrigger */ 567 FIELD(TB_FLAGS, ITRIGGER, 22, 1) 568 /* Virtual mode enabled */ 569 FIELD(TB_FLAGS, VIRT_ENABLED, 23, 1) 570 FIELD(TB_FLAGS, PRIV, 24, 2) 571 FIELD(TB_FLAGS, AXL, 26, 2) 572 573 #ifdef TARGET_RISCV32 574 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) 575 #else 576 static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) 577 { 578 return env->misa_mxl; 579 } 580 #endif 581 #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env))) 582 583 static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURISCVState *env) 584 { 585 return &env_archcpu(env)->cfg; 586 } 587 588 #if !defined(CONFIG_USER_ONLY) 589 static inline int cpu_address_mode(CPURISCVState *env) 590 { 591 int mode = env->priv; 592 593 if (mode == PRV_M && get_field(env->mstatus, MSTATUS_MPRV)) { 594 mode = get_field(env->mstatus, MSTATUS_MPP); 595 } 596 return mode; 597 } 598 599 static inline RISCVMXL cpu_get_xl(CPURISCVState *env, target_ulong mode) 600 { 601 RISCVMXL xl = env->misa_mxl; 602 /* 603 * When emulating a 32-bit-only cpu, use RV32. 604 * When emulating a 64-bit cpu, and MXL has been reduced to RV32, 605 * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened 606 * back to RV64 for lower privs. 607 */ 608 if (xl != MXL_RV32) { 609 switch (mode) { 610 case PRV_M: 611 break; 612 case PRV_U: 613 xl = get_field(env->mstatus, MSTATUS64_UXL); 614 break; 615 default: /* PRV_S */ 616 xl = get_field(env->mstatus, MSTATUS64_SXL); 617 break; 618 } 619 } 620 return xl; 621 } 622 #endif 623 624 #if defined(TARGET_RISCV32) 625 #define cpu_recompute_xl(env) ((void)(env), MXL_RV32) 626 #else 627 static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) 628 { 629 #if !defined(CONFIG_USER_ONLY) 630 return cpu_get_xl(env, env->priv); 631 #else 632 return env->misa_mxl; 633 #endif 634 } 635 #endif 636 637 #if defined(TARGET_RISCV32) 638 #define cpu_address_xl(env) ((void)(env), MXL_RV32) 639 #else 640 static inline RISCVMXL cpu_address_xl(CPURISCVState *env) 641 { 642 #ifdef CONFIG_USER_ONLY 643 return env->xl; 644 #else 645 int mode = cpu_address_mode(env); 646 647 return cpu_get_xl(env, mode); 648 #endif 649 } 650 #endif 651 652 static inline int riscv_cpu_xlen(CPURISCVState *env) 653 { 654 return 16 << env->xl; 655 } 656 657 #ifdef TARGET_RISCV32 658 #define riscv_cpu_sxl(env) ((void)(env), MXL_RV32) 659 #else 660 static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env) 661 { 662 #ifdef CONFIG_USER_ONLY 663 return env->misa_mxl; 664 #else 665 return get_field(env->mstatus, MSTATUS64_SXL); 666 #endif 667 } 668 #endif 669 670 /* 671 * Encode LMUL to lmul as follows: 672 * LMUL vlmul lmul 673 * 1 000 0 674 * 2 001 1 675 * 4 010 2 676 * 8 011 3 677 * - 100 - 678 * 1/8 101 -3 679 * 1/4 110 -2 680 * 1/2 111 -1 681 * 682 * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul) 683 * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8 684 * => VLMAX = vlen >> (1 + 3 - (-3)) 685 * = 256 >> 7 686 * = 2 687 */ 688 static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) 689 { 690 uint8_t sew = FIELD_EX64(vtype, VTYPE, VSEW); 691 int8_t lmul = sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3); 692 return cpu->cfg.vlen >> (sew + 3 - lmul); 693 } 694 695 void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, 696 uint64_t *cs_base, uint32_t *pflags); 697 698 void riscv_cpu_update_mask(CPURISCVState *env); 699 bool riscv_cpu_is_32bit(RISCVCPU *cpu); 700 701 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, 702 target_ulong *ret_value, 703 target_ulong new_value, target_ulong write_mask); 704 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, 705 target_ulong *ret_value, 706 target_ulong new_value, 707 target_ulong write_mask); 708 709 static inline void riscv_csr_write(CPURISCVState *env, int csrno, 710 target_ulong val) 711 { 712 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); 713 } 714 715 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) 716 { 717 target_ulong val = 0; 718 riscv_csrrw(env, csrno, &val, 0, 0); 719 return val; 720 } 721 722 typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, 723 int csrno); 724 typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, 725 target_ulong *ret_value); 726 typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, 727 target_ulong new_value); 728 typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, 729 target_ulong *ret_value, 730 target_ulong new_value, 731 target_ulong write_mask); 732 733 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, 734 Int128 *ret_value, 735 Int128 new_value, Int128 write_mask); 736 737 typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno, 738 Int128 *ret_value); 739 typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int csrno, 740 Int128 new_value); 741 742 typedef struct { 743 const char *name; 744 riscv_csr_predicate_fn predicate; 745 riscv_csr_read_fn read; 746 riscv_csr_write_fn write; 747 riscv_csr_op_fn op; 748 riscv_csr_read128_fn read128; 749 riscv_csr_write128_fn write128; 750 /* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0) */ 751 uint32_t min_priv_ver; 752 } riscv_csr_operations; 753 754 /* CSR function table constants */ 755 enum { 756 CSR_TABLE_SIZE = 0x1000 757 }; 758 759 /* 760 * The event id are encoded based on the encoding specified in the 761 * SBI specification v0.3 762 */ 763 764 enum riscv_pmu_event_idx { 765 RISCV_PMU_EVENT_HW_CPU_CYCLES = 0x01, 766 RISCV_PMU_EVENT_HW_INSTRUCTIONS = 0x02, 767 RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS = 0x10019, 768 RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS = 0x1001B, 769 RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS = 0x10021, 770 }; 771 772 /* used by tcg/tcg-cpu.c*/ 773 void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en); 774 bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset); 775 void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext); 776 bool riscv_cpu_is_vendor(Object *cpu_obj); 777 778 typedef struct RISCVCPUMultiExtConfig { 779 const char *name; 780 uint32_t offset; 781 bool enabled; 782 } RISCVCPUMultiExtConfig; 783 784 extern const RISCVCPUMultiExtConfig riscv_cpu_extensions[]; 785 extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[]; 786 extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[]; 787 extern const RISCVCPUMultiExtConfig riscv_cpu_named_features[]; 788 extern const RISCVCPUMultiExtConfig riscv_cpu_deprecated_exts[]; 789 extern Property riscv_cpu_options[]; 790 791 typedef struct isa_ext_data { 792 const char *name; 793 int min_version; 794 int ext_enable_offset; 795 } RISCVIsaExtData; 796 extern const RISCVIsaExtData isa_edata_arr[]; 797 char *riscv_cpu_get_name(RISCVCPU *cpu); 798 799 void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp); 800 void riscv_add_satp_mode_properties(Object *obj); 801 bool riscv_cpu_accelerator_compatible(RISCVCPU *cpu); 802 803 /* CSR function table */ 804 extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; 805 806 extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[]; 807 808 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); 809 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); 810 811 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); 812 813 uint8_t satp_mode_max_from_map(uint32_t map); 814 const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); 815 816 #endif /* RISCV_CPU_H */ 817