1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef RISCV_CPU_H 21 #define RISCV_CPU_H 22 23 #include "hw/core/cpu.h" 24 #include "hw/registerfields.h" 25 #include "hw/qdev-properties.h" 26 #include "exec/cpu-defs.h" 27 #include "qemu/cpu-float.h" 28 #include "qom/object.h" 29 #include "qemu/int128.h" 30 #include "cpu_bits.h" 31 #include "cpu_cfg.h" 32 #include "qapi/qapi-types-common.h" 33 #include "cpu-qom.h" 34 35 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU 36 37 #if defined(TARGET_RISCV32) 38 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 39 #elif defined(TARGET_RISCV64) 40 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 41 #endif 42 43 #define TCG_GUEST_DEFAULT_MO 0 44 45 /* 46 * RISC-V-specific extra insn start words: 47 * 1: Original instruction opcode 48 */ 49 #define TARGET_INSN_START_EXTRA_WORDS 1 50 51 #define RV(x) ((target_ulong)1 << (x - 'A')) 52 53 /* 54 * Update misa_bits[], misa_ext_info_arr[] and misa_ext_cfgs[] 55 * when adding new MISA bits here. 56 */ 57 #define RVI RV('I') 58 #define RVE RV('E') /* E and I are mutually exclusive */ 59 #define RVM RV('M') 60 #define RVA RV('A') 61 #define RVF RV('F') 62 #define RVD RV('D') 63 #define RVV RV('V') 64 #define RVC RV('C') 65 #define RVS RV('S') 66 #define RVU RV('U') 67 #define RVH RV('H') 68 #define RVJ RV('J') 69 #define RVG RV('G') 70 71 extern const uint32_t misa_bits[]; 72 const char *riscv_get_misa_ext_name(uint32_t bit); 73 const char *riscv_get_misa_ext_description(uint32_t bit); 74 75 #define CPU_CFG_OFFSET(_prop) offsetof(struct RISCVCPUConfig, _prop) 76 77 /* Privileged specification version */ 78 enum { 79 PRIV_VERSION_1_10_0 = 0, 80 PRIV_VERSION_1_11_0, 81 PRIV_VERSION_1_12_0, 82 83 PRIV_VERSION_LATEST = PRIV_VERSION_1_12_0, 84 }; 85 86 #define VEXT_VERSION_1_00_0 0x00010000 87 88 enum { 89 TRANSLATE_SUCCESS, 90 TRANSLATE_FAIL, 91 TRANSLATE_PMP_FAIL, 92 TRANSLATE_G_STAGE_FAIL 93 }; 94 95 /* Extension context status */ 96 typedef enum { 97 EXT_STATUS_DISABLED = 0, 98 EXT_STATUS_INITIAL, 99 EXT_STATUS_CLEAN, 100 EXT_STATUS_DIRTY, 101 } RISCVExtStatus; 102 103 #define MMU_USER_IDX 3 104 105 #define MAX_RISCV_PMPS (16) 106 107 #if !defined(CONFIG_USER_ONLY) 108 #include "pmp.h" 109 #include "debug.h" 110 #endif 111 112 #define RV_VLEN_MAX 1024 113 #define RV_MAX_MHPMEVENTS 32 114 #define RV_MAX_MHPMCOUNTERS 32 115 116 FIELD(VTYPE, VLMUL, 0, 3) 117 FIELD(VTYPE, VSEW, 3, 3) 118 FIELD(VTYPE, VTA, 6, 1) 119 FIELD(VTYPE, VMA, 7, 1) 120 FIELD(VTYPE, VEDIV, 8, 2) 121 FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) 122 123 typedef struct PMUCTRState { 124 /* Current value of a counter */ 125 target_ulong mhpmcounter_val; 126 /* Current value of a counter in RV32 */ 127 target_ulong mhpmcounterh_val; 128 /* Snapshot values of counter */ 129 target_ulong mhpmcounter_prev; 130 /* Snapshort value of a counter in RV32 */ 131 target_ulong mhpmcounterh_prev; 132 bool started; 133 /* Value beyond UINT32_MAX/UINT64_MAX before overflow interrupt trigger */ 134 target_ulong irq_overflow_left; 135 } PMUCTRState; 136 137 struct CPUArchState { 138 target_ulong gpr[32]; 139 target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ 140 141 /* vector coprocessor state. */ 142 uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); 143 target_ulong vxrm; 144 target_ulong vxsat; 145 target_ulong vl; 146 target_ulong vstart; 147 target_ulong vtype; 148 bool vill; 149 150 target_ulong pc; 151 target_ulong load_res; 152 target_ulong load_val; 153 154 /* Floating-Point state */ 155 uint64_t fpr[32]; /* assume both F and D extensions */ 156 target_ulong frm; 157 float_status fp_status; 158 159 target_ulong badaddr; 160 target_ulong bins; 161 162 target_ulong guest_phys_fault_addr; 163 164 target_ulong priv_ver; 165 target_ulong bext_ver; 166 target_ulong vext_ver; 167 168 /* RISCVMXL, but uint32_t for vmstate migration */ 169 uint32_t misa_mxl; /* current mxl */ 170 uint32_t misa_mxl_max; /* max mxl for this cpu */ 171 uint32_t misa_ext; /* current extensions */ 172 uint32_t misa_ext_mask; /* max ext for this cpu */ 173 uint32_t xl; /* current xlen */ 174 175 /* 128-bit helpers upper part return value */ 176 target_ulong retxh; 177 178 target_ulong jvt; 179 180 #ifdef CONFIG_USER_ONLY 181 uint32_t elf_flags; 182 #endif 183 184 #ifndef CONFIG_USER_ONLY 185 target_ulong priv; 186 /* This contains QEMU specific information about the virt state. */ 187 bool virt_enabled; 188 target_ulong geilen; 189 uint64_t resetvec; 190 191 target_ulong mhartid; 192 /* 193 * For RV32 this is 32-bit mstatus and 32-bit mstatush. 194 * For RV64 this is a 64-bit mstatus. 195 */ 196 uint64_t mstatus; 197 198 uint64_t mip; 199 /* 200 * MIP contains the software writable version of SEIP ORed with the 201 * external interrupt value. The MIP register is always up-to-date. 202 * To keep track of the current source, we also save booleans of the values 203 * here. 204 */ 205 bool external_seip; 206 bool software_seip; 207 208 uint64_t miclaim; 209 210 uint64_t mie; 211 uint64_t mideleg; 212 213 /* 214 * When mideleg[i]=0 and mvien[i]=1, sie[i] is no more 215 * alias of mie[i] and needs to be maintained separatly. 216 */ 217 uint64_t sie; 218 219 /* 220 * When hideleg[i]=0 and hvien[i]=1, vsie[i] is no more 221 * alias of sie[i] (mie[i]) and needs to be maintained separatly. 222 */ 223 uint64_t vsie; 224 225 target_ulong satp; /* since: priv-1.10.0 */ 226 target_ulong stval; 227 target_ulong medeleg; 228 229 target_ulong stvec; 230 target_ulong sepc; 231 target_ulong scause; 232 233 target_ulong mtvec; 234 target_ulong mepc; 235 target_ulong mcause; 236 target_ulong mtval; /* since: priv-1.10.0 */ 237 238 /* Machine and Supervisor interrupt priorities */ 239 uint8_t miprio[64]; 240 uint8_t siprio[64]; 241 242 /* AIA CSRs */ 243 target_ulong miselect; 244 target_ulong siselect; 245 uint64_t mvien; 246 uint64_t mvip; 247 248 /* Hypervisor CSRs */ 249 target_ulong hstatus; 250 target_ulong hedeleg; 251 uint64_t hideleg; 252 target_ulong hcounteren; 253 target_ulong htval; 254 target_ulong htinst; 255 target_ulong hgatp; 256 target_ulong hgeie; 257 target_ulong hgeip; 258 uint64_t htimedelta; 259 uint64_t hvien; 260 261 /* 262 * Bits VSSIP, VSTIP and VSEIP in hvip are maintained in mip. Other bits 263 * from 0:12 are reserved. Bits 13:63 are not aliased and must be separately 264 * maintain in hvip. 265 */ 266 uint64_t hvip; 267 268 /* Hypervisor controlled virtual interrupt priorities */ 269 target_ulong hvictl; 270 uint8_t hviprio[64]; 271 272 /* Upper 64-bits of 128-bit CSRs */ 273 uint64_t mscratchh; 274 uint64_t sscratchh; 275 276 /* Virtual CSRs */ 277 /* 278 * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. 279 * For RV64 this is a 64-bit vsstatus. 280 */ 281 uint64_t vsstatus; 282 target_ulong vstvec; 283 target_ulong vsscratch; 284 target_ulong vsepc; 285 target_ulong vscause; 286 target_ulong vstval; 287 target_ulong vsatp; 288 289 /* AIA VS-mode CSRs */ 290 target_ulong vsiselect; 291 292 target_ulong mtval2; 293 target_ulong mtinst; 294 295 /* HS Backup CSRs */ 296 target_ulong stvec_hs; 297 target_ulong sscratch_hs; 298 target_ulong sepc_hs; 299 target_ulong scause_hs; 300 target_ulong stval_hs; 301 target_ulong satp_hs; 302 uint64_t mstatus_hs; 303 304 /* 305 * Signals whether the current exception occurred with two-stage address 306 * translation active. 307 */ 308 bool two_stage_lookup; 309 /* 310 * Signals whether the current exception occurred while doing two-stage 311 * address translation for the VS-stage page table walk. 312 */ 313 bool two_stage_indirect_lookup; 314 315 target_ulong scounteren; 316 target_ulong mcounteren; 317 318 target_ulong mcountinhibit; 319 320 /* PMU counter state */ 321 PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS]; 322 323 /* PMU event selector configured values. First three are unused */ 324 target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS]; 325 326 /* PMU event selector configured values for RV32 */ 327 target_ulong mhpmeventh_val[RV_MAX_MHPMEVENTS]; 328 329 target_ulong sscratch; 330 target_ulong mscratch; 331 332 /* Sstc CSRs */ 333 uint64_t stimecmp; 334 335 uint64_t vstimecmp; 336 337 /* physical memory protection */ 338 pmp_table_t pmp_state; 339 target_ulong mseccfg; 340 341 /* trigger module */ 342 target_ulong trigger_cur; 343 target_ulong tdata1[RV_MAX_TRIGGERS]; 344 target_ulong tdata2[RV_MAX_TRIGGERS]; 345 target_ulong tdata3[RV_MAX_TRIGGERS]; 346 struct CPUBreakpoint *cpu_breakpoint[RV_MAX_TRIGGERS]; 347 struct CPUWatchpoint *cpu_watchpoint[RV_MAX_TRIGGERS]; 348 QEMUTimer *itrigger_timer[RV_MAX_TRIGGERS]; 349 int64_t last_icount; 350 bool itrigger_enabled; 351 352 /* machine specific rdtime callback */ 353 uint64_t (*rdtime_fn)(void *); 354 void *rdtime_fn_arg; 355 356 /* machine specific AIA ireg read-modify-write callback */ 357 #define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \ 358 ((((__xlen) & 0xff) << 24) | \ 359 (((__vgein) & 0x3f) << 20) | \ 360 (((__virt) & 0x1) << 18) | \ 361 (((__priv) & 0x3) << 16) | \ 362 (__isel & 0xffff)) 363 #define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff) 364 #define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3) 365 #define AIA_IREG_VIRT(__ireg) (((__ireg) >> 18) & 0x1) 366 #define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 20) & 0x3f) 367 #define AIA_IREG_XLEN(__ireg) (((__ireg) >> 24) & 0xff) 368 int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg, 369 target_ulong *val, target_ulong new_val, target_ulong write_mask); 370 void *aia_ireg_rmw_fn_arg[4]; 371 372 /* True if in debugger mode. */ 373 bool debugger; 374 375 /* 376 * CSRs for PointerMasking extension 377 */ 378 target_ulong mmte; 379 target_ulong mpmmask; 380 target_ulong mpmbase; 381 target_ulong spmmask; 382 target_ulong spmbase; 383 target_ulong upmmask; 384 target_ulong upmbase; 385 386 /* CSRs for execution environment configuration */ 387 uint64_t menvcfg; 388 uint64_t mstateen[SMSTATEEN_MAX_COUNT]; 389 uint64_t hstateen[SMSTATEEN_MAX_COUNT]; 390 uint64_t sstateen[SMSTATEEN_MAX_COUNT]; 391 target_ulong senvcfg; 392 uint64_t henvcfg; 393 #endif 394 target_ulong cur_pmmask; 395 target_ulong cur_pmbase; 396 397 /* Fields from here on are preserved across CPU reset. */ 398 QEMUTimer *stimer; /* Internal timer for S-mode interrupt */ 399 QEMUTimer *vstimer; /* Internal timer for VS-mode interrupt */ 400 bool vstime_irq; 401 402 hwaddr kernel_addr; 403 hwaddr fdt_addr; 404 405 #ifdef CONFIG_KVM 406 /* kvm timer */ 407 bool kvm_timer_dirty; 408 uint64_t kvm_timer_time; 409 uint64_t kvm_timer_compare; 410 uint64_t kvm_timer_state; 411 uint64_t kvm_timer_frequency; 412 #endif /* CONFIG_KVM */ 413 }; 414 415 /* 416 * RISCVCPU: 417 * @env: #CPURISCVState 418 * 419 * A RISCV CPU. 420 */ 421 struct ArchCPU { 422 CPUState parent_obj; 423 424 CPURISCVState env; 425 426 char *dyn_csr_xml; 427 char *dyn_vreg_xml; 428 429 /* Configuration Settings */ 430 RISCVCPUConfig cfg; 431 432 QEMUTimer *pmu_timer; 433 /* A bitmask of Available programmable counters */ 434 uint32_t pmu_avail_ctrs; 435 /* Mapping of events to counters */ 436 GHashTable *pmu_event_ctr_map; 437 }; 438 439 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) 440 { 441 return (env->misa_ext & ext) != 0; 442 } 443 444 #include "cpu_user.h" 445 446 extern const char * const riscv_int_regnames[]; 447 extern const char * const riscv_int_regnamesh[]; 448 extern const char * const riscv_fpr_regnames[]; 449 450 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); 451 void riscv_cpu_do_interrupt(CPUState *cpu); 452 int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 453 int cpuid, DumpState *s); 454 int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 455 int cpuid, DumpState *s); 456 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 457 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 458 int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero); 459 uint8_t riscv_cpu_default_priority(int irq); 460 uint64_t riscv_cpu_all_pending(CPURISCVState *env); 461 int riscv_cpu_mirq_pending(CPURISCVState *env); 462 int riscv_cpu_sirq_pending(CPURISCVState *env); 463 int riscv_cpu_vsirq_pending(CPURISCVState *env); 464 bool riscv_cpu_fp_enabled(CPURISCVState *env); 465 target_ulong riscv_cpu_get_geilen(CPURISCVState *env); 466 void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); 467 bool riscv_cpu_vector_enabled(CPURISCVState *env); 468 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); 469 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); 470 G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 471 MMUAccessType access_type, 472 int mmu_idx, uintptr_t retaddr); 473 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 474 MMUAccessType access_type, int mmu_idx, 475 bool probe, uintptr_t retaddr); 476 char *riscv_isa_string(RISCVCPU *cpu); 477 void riscv_cpu_list(void); 478 479 #define cpu_list riscv_cpu_list 480 #define cpu_mmu_index riscv_cpu_mmu_index 481 482 #ifndef CONFIG_USER_ONLY 483 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 484 vaddr addr, unsigned size, 485 MMUAccessType access_type, 486 int mmu_idx, MemTxAttrs attrs, 487 MemTxResult response, uintptr_t retaddr); 488 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 489 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); 490 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); 491 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); 492 uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask, 493 uint64_t value); 494 void riscv_cpu_interrupt(CPURISCVState *env); 495 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ 496 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), 497 void *arg); 498 void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, 499 int (*rmw_fn)(void *arg, 500 target_ulong reg, 501 target_ulong *val, 502 target_ulong new_val, 503 target_ulong write_mask), 504 void *rmw_fn_arg); 505 506 RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit); 507 #endif 508 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); 509 510 void riscv_translate_init(void); 511 G_NORETURN void riscv_raise_exception(CPURISCVState *env, 512 uint32_t exception, uintptr_t pc); 513 514 target_ulong riscv_cpu_get_fflags(CPURISCVState *env); 515 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); 516 517 #include "exec/cpu-all.h" 518 519 FIELD(TB_FLAGS, MEM_IDX, 0, 3) 520 FIELD(TB_FLAGS, FS, 3, 2) 521 /* Vector flags */ 522 FIELD(TB_FLAGS, VS, 5, 2) 523 FIELD(TB_FLAGS, LMUL, 7, 3) 524 FIELD(TB_FLAGS, SEW, 10, 3) 525 FIELD(TB_FLAGS, VL_EQ_VLMAX, 13, 1) 526 FIELD(TB_FLAGS, VILL, 14, 1) 527 FIELD(TB_FLAGS, VSTART_EQ_ZERO, 15, 1) 528 /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ 529 FIELD(TB_FLAGS, XL, 16, 2) 530 /* If PointerMasking should be applied */ 531 FIELD(TB_FLAGS, PM_MASK_ENABLED, 18, 1) 532 FIELD(TB_FLAGS, PM_BASE_ENABLED, 19, 1) 533 FIELD(TB_FLAGS, VTA, 20, 1) 534 FIELD(TB_FLAGS, VMA, 21, 1) 535 /* Native debug itrigger */ 536 FIELD(TB_FLAGS, ITRIGGER, 22, 1) 537 /* Virtual mode enabled */ 538 FIELD(TB_FLAGS, VIRT_ENABLED, 23, 1) 539 FIELD(TB_FLAGS, PRIV, 24, 2) 540 FIELD(TB_FLAGS, AXL, 26, 2) 541 542 #ifdef TARGET_RISCV32 543 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) 544 #else 545 static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) 546 { 547 return env->misa_mxl; 548 } 549 #endif 550 #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env))) 551 552 static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURISCVState *env) 553 { 554 return &env_archcpu(env)->cfg; 555 } 556 557 #if !defined(CONFIG_USER_ONLY) 558 static inline int cpu_address_mode(CPURISCVState *env) 559 { 560 int mode = env->priv; 561 562 if (mode == PRV_M && get_field(env->mstatus, MSTATUS_MPRV)) { 563 mode = get_field(env->mstatus, MSTATUS_MPP); 564 } 565 return mode; 566 } 567 568 static inline RISCVMXL cpu_get_xl(CPURISCVState *env, target_ulong mode) 569 { 570 RISCVMXL xl = env->misa_mxl; 571 /* 572 * When emulating a 32-bit-only cpu, use RV32. 573 * When emulating a 64-bit cpu, and MXL has been reduced to RV32, 574 * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened 575 * back to RV64 for lower privs. 576 */ 577 if (xl != MXL_RV32) { 578 switch (mode) { 579 case PRV_M: 580 break; 581 case PRV_U: 582 xl = get_field(env->mstatus, MSTATUS64_UXL); 583 break; 584 default: /* PRV_S */ 585 xl = get_field(env->mstatus, MSTATUS64_SXL); 586 break; 587 } 588 } 589 return xl; 590 } 591 #endif 592 593 #if defined(TARGET_RISCV32) 594 #define cpu_recompute_xl(env) ((void)(env), MXL_RV32) 595 #else 596 static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) 597 { 598 #if !defined(CONFIG_USER_ONLY) 599 return cpu_get_xl(env, env->priv); 600 #else 601 return env->misa_mxl; 602 #endif 603 } 604 #endif 605 606 #if defined(TARGET_RISCV32) 607 #define cpu_address_xl(env) ((void)(env), MXL_RV32) 608 #else 609 static inline RISCVMXL cpu_address_xl(CPURISCVState *env) 610 { 611 #ifdef CONFIG_USER_ONLY 612 return env->xl; 613 #else 614 int mode = cpu_address_mode(env); 615 616 return cpu_get_xl(env, mode); 617 #endif 618 } 619 #endif 620 621 static inline int riscv_cpu_xlen(CPURISCVState *env) 622 { 623 return 16 << env->xl; 624 } 625 626 #ifdef TARGET_RISCV32 627 #define riscv_cpu_sxl(env) ((void)(env), MXL_RV32) 628 #else 629 static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env) 630 { 631 #ifdef CONFIG_USER_ONLY 632 return env->misa_mxl; 633 #else 634 return get_field(env->mstatus, MSTATUS64_SXL); 635 #endif 636 } 637 #endif 638 639 /* 640 * Encode LMUL to lmul as follows: 641 * LMUL vlmul lmul 642 * 1 000 0 643 * 2 001 1 644 * 4 010 2 645 * 8 011 3 646 * - 100 - 647 * 1/8 101 -3 648 * 1/4 110 -2 649 * 1/2 111 -1 650 * 651 * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul) 652 * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8 653 * => VLMAX = vlen >> (1 + 3 - (-3)) 654 * = 256 >> 7 655 * = 2 656 */ 657 static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) 658 { 659 uint8_t sew = FIELD_EX64(vtype, VTYPE, VSEW); 660 int8_t lmul = sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3); 661 return cpu->cfg.vlen >> (sew + 3 - lmul); 662 } 663 664 void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, 665 uint64_t *cs_base, uint32_t *pflags); 666 667 void riscv_cpu_update_mask(CPURISCVState *env); 668 669 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, 670 target_ulong *ret_value, 671 target_ulong new_value, target_ulong write_mask); 672 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, 673 target_ulong *ret_value, 674 target_ulong new_value, 675 target_ulong write_mask); 676 677 static inline void riscv_csr_write(CPURISCVState *env, int csrno, 678 target_ulong val) 679 { 680 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); 681 } 682 683 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) 684 { 685 target_ulong val = 0; 686 riscv_csrrw(env, csrno, &val, 0, 0); 687 return val; 688 } 689 690 typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, 691 int csrno); 692 typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, 693 target_ulong *ret_value); 694 typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, 695 target_ulong new_value); 696 typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, 697 target_ulong *ret_value, 698 target_ulong new_value, 699 target_ulong write_mask); 700 701 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, 702 Int128 *ret_value, 703 Int128 new_value, Int128 write_mask); 704 705 typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno, 706 Int128 *ret_value); 707 typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int csrno, 708 Int128 new_value); 709 710 typedef struct { 711 const char *name; 712 riscv_csr_predicate_fn predicate; 713 riscv_csr_read_fn read; 714 riscv_csr_write_fn write; 715 riscv_csr_op_fn op; 716 riscv_csr_read128_fn read128; 717 riscv_csr_write128_fn write128; 718 /* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0) */ 719 uint32_t min_priv_ver; 720 } riscv_csr_operations; 721 722 /* CSR function table constants */ 723 enum { 724 CSR_TABLE_SIZE = 0x1000 725 }; 726 727 /* 728 * The event id are encoded based on the encoding specified in the 729 * SBI specification v0.3 730 */ 731 732 enum riscv_pmu_event_idx { 733 RISCV_PMU_EVENT_HW_CPU_CYCLES = 0x01, 734 RISCV_PMU_EVENT_HW_INSTRUCTIONS = 0x02, 735 RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS = 0x10019, 736 RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS = 0x1001B, 737 RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS = 0x10021, 738 }; 739 740 /* used by tcg/tcg-cpu.c*/ 741 void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en); 742 bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset); 743 void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext); 744 745 typedef struct RISCVCPUMultiExtConfig { 746 const char *name; 747 uint32_t offset; 748 bool enabled; 749 } RISCVCPUMultiExtConfig; 750 751 extern const RISCVCPUMultiExtConfig riscv_cpu_extensions[]; 752 extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[]; 753 extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[]; 754 extern const RISCVCPUMultiExtConfig riscv_cpu_deprecated_exts[]; 755 extern Property riscv_cpu_options[]; 756 757 typedef struct isa_ext_data { 758 const char *name; 759 int min_version; 760 int ext_enable_offset; 761 } RISCVIsaExtData; 762 extern const RISCVIsaExtData isa_edata_arr[]; 763 char *riscv_cpu_get_name(RISCVCPU *cpu); 764 765 void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp); 766 void riscv_add_satp_mode_properties(Object *obj); 767 bool riscv_cpu_accelerator_compatible(RISCVCPU *cpu); 768 769 /* CSR function table */ 770 extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; 771 772 extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[]; 773 774 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); 775 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); 776 777 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); 778 779 uint8_t satp_mode_max_from_map(uint32_t map); 780 const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); 781 782 #endif /* RISCV_CPU_H */ 783