1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef RISCV_CPU_H 21 #define RISCV_CPU_H 22 23 #include "hw/core/cpu.h" 24 #include "hw/registerfields.h" 25 #include "exec/cpu-defs.h" 26 #include "fpu/softfloat-types.h" 27 #include "qom/object.h" 28 #include "cpu_bits.h" 29 30 #define TCG_GUEST_DEFAULT_MO 0 31 32 #define TYPE_RISCV_CPU "riscv-cpu" 33 34 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU 35 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) 36 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU 37 38 #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") 39 #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") 40 #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") 41 #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") 42 #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") 43 #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") 44 #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") 45 #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") 46 #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") 47 #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") 48 49 #if defined(TARGET_RISCV32) 50 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 51 #elif defined(TARGET_RISCV64) 52 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 53 #endif 54 55 #define RV(x) ((target_ulong)1 << (x - 'A')) 56 57 #define RVI RV('I') 58 #define RVE RV('E') /* E and I are mutually exclusive */ 59 #define RVM RV('M') 60 #define RVA RV('A') 61 #define RVF RV('F') 62 #define RVD RV('D') 63 #define RVV RV('V') 64 #define RVC RV('C') 65 #define RVS RV('S') 66 #define RVU RV('U') 67 #define RVH RV('H') 68 69 /* S extension denotes that Supervisor mode exists, however it is possible 70 to have a core that support S mode but does not have an MMU and there 71 is currently no bit in misa to indicate whether an MMU exists or not 72 so a cpu features bitfield is required, likewise for optional PMP support */ 73 enum { 74 RISCV_FEATURE_MMU, 75 RISCV_FEATURE_PMP, 76 RISCV_FEATURE_EPMP, 77 RISCV_FEATURE_MISA 78 }; 79 80 #define PRIV_VERSION_1_10_0 0x00011000 81 #define PRIV_VERSION_1_11_0 0x00011100 82 83 #define VEXT_VERSION_0_07_1 0x00000701 84 85 enum { 86 TRANSLATE_SUCCESS, 87 TRANSLATE_FAIL, 88 TRANSLATE_PMP_FAIL, 89 TRANSLATE_G_STAGE_FAIL 90 }; 91 92 #define MMU_USER_IDX 3 93 94 #define MAX_RISCV_PMPS (16) 95 96 typedef struct CPURISCVState CPURISCVState; 97 98 #if !defined(CONFIG_USER_ONLY) 99 #include "pmp.h" 100 #endif 101 102 #define RV_VLEN_MAX 256 103 104 FIELD(VTYPE, VLMUL, 0, 2) 105 FIELD(VTYPE, VSEW, 2, 3) 106 FIELD(VTYPE, VEDIV, 5, 2) 107 FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 9) 108 FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1) 109 110 struct CPURISCVState { 111 target_ulong gpr[32]; 112 uint64_t fpr[32]; /* assume both F and D extensions */ 113 114 /* vector coprocessor state. */ 115 uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); 116 target_ulong vxrm; 117 target_ulong vxsat; 118 target_ulong vl; 119 target_ulong vstart; 120 target_ulong vtype; 121 122 target_ulong pc; 123 target_ulong load_res; 124 target_ulong load_val; 125 126 target_ulong frm; 127 128 target_ulong badaddr; 129 target_ulong guest_phys_fault_addr; 130 131 target_ulong priv_ver; 132 target_ulong bext_ver; 133 target_ulong vext_ver; 134 135 /* RISCVMXL, but uint32_t for vmstate migration */ 136 uint32_t misa_mxl; /* current mxl */ 137 uint32_t misa_mxl_max; /* max mxl for this cpu */ 138 uint32_t misa_ext; /* current extensions */ 139 uint32_t misa_ext_mask; /* max ext for this cpu */ 140 141 uint32_t features; 142 143 #ifdef CONFIG_USER_ONLY 144 uint32_t elf_flags; 145 #endif 146 147 #ifndef CONFIG_USER_ONLY 148 target_ulong priv; 149 /* This contains QEMU specific information about the virt state. */ 150 target_ulong virt; 151 target_ulong resetvec; 152 153 target_ulong mhartid; 154 /* 155 * For RV32 this is 32-bit mstatus and 32-bit mstatush. 156 * For RV64 this is a 64-bit mstatus. 157 */ 158 uint64_t mstatus; 159 160 target_ulong mip; 161 162 uint32_t miclaim; 163 164 target_ulong mie; 165 target_ulong mideleg; 166 167 target_ulong satp; /* since: priv-1.10.0 */ 168 target_ulong stval; 169 target_ulong medeleg; 170 171 target_ulong stvec; 172 target_ulong sepc; 173 target_ulong scause; 174 175 target_ulong mtvec; 176 target_ulong mepc; 177 target_ulong mcause; 178 target_ulong mtval; /* since: priv-1.10.0 */ 179 180 /* Hypervisor CSRs */ 181 target_ulong hstatus; 182 target_ulong hedeleg; 183 target_ulong hideleg; 184 target_ulong hcounteren; 185 target_ulong htval; 186 target_ulong htinst; 187 target_ulong hgatp; 188 uint64_t htimedelta; 189 190 /* Virtual CSRs */ 191 /* 192 * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. 193 * For RV64 this is a 64-bit vsstatus. 194 */ 195 uint64_t vsstatus; 196 target_ulong vstvec; 197 target_ulong vsscratch; 198 target_ulong vsepc; 199 target_ulong vscause; 200 target_ulong vstval; 201 target_ulong vsatp; 202 203 target_ulong mtval2; 204 target_ulong mtinst; 205 206 /* HS Backup CSRs */ 207 target_ulong stvec_hs; 208 target_ulong sscratch_hs; 209 target_ulong sepc_hs; 210 target_ulong scause_hs; 211 target_ulong stval_hs; 212 target_ulong satp_hs; 213 uint64_t mstatus_hs; 214 215 /* Signals whether the current exception occurred with two-stage address 216 translation active. */ 217 bool two_stage_lookup; 218 219 target_ulong scounteren; 220 target_ulong mcounteren; 221 222 target_ulong sscratch; 223 target_ulong mscratch; 224 225 /* temporary htif regs */ 226 uint64_t mfromhost; 227 uint64_t mtohost; 228 uint64_t timecmp; 229 230 /* physical memory protection */ 231 pmp_table_t pmp_state; 232 target_ulong mseccfg; 233 234 /* machine specific rdtime callback */ 235 uint64_t (*rdtime_fn)(uint32_t); 236 uint32_t rdtime_fn_arg; 237 238 /* True if in debugger mode. */ 239 bool debugger; 240 #endif 241 242 float_status fp_status; 243 244 /* Fields from here on are preserved across CPU reset. */ 245 QEMUTimer *timer; /* Internal timer */ 246 }; 247 248 OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass, 249 RISCV_CPU) 250 251 /** 252 * RISCVCPUClass: 253 * @parent_realize: The parent class' realize handler. 254 * @parent_reset: The parent class' reset handler. 255 * 256 * A RISCV CPU model. 257 */ 258 struct RISCVCPUClass { 259 /*< private >*/ 260 CPUClass parent_class; 261 /*< public >*/ 262 DeviceRealize parent_realize; 263 DeviceReset parent_reset; 264 }; 265 266 /** 267 * RISCVCPU: 268 * @env: #CPURISCVState 269 * 270 * A RISCV CPU. 271 */ 272 struct RISCVCPU { 273 /*< private >*/ 274 CPUState parent_obj; 275 /*< public >*/ 276 CPUNegativeOffsetState neg; 277 CPURISCVState env; 278 279 char *dyn_csr_xml; 280 281 /* Configuration Settings */ 282 struct { 283 bool ext_i; 284 bool ext_e; 285 bool ext_g; 286 bool ext_m; 287 bool ext_a; 288 bool ext_f; 289 bool ext_d; 290 bool ext_c; 291 bool ext_s; 292 bool ext_u; 293 bool ext_h; 294 bool ext_v; 295 bool ext_zba; 296 bool ext_zbb; 297 bool ext_zbc; 298 bool ext_zbs; 299 bool ext_counters; 300 bool ext_ifencei; 301 bool ext_icsr; 302 303 char *priv_spec; 304 char *user_spec; 305 char *bext_spec; 306 char *vext_spec; 307 uint16_t vlen; 308 uint16_t elen; 309 bool mmu; 310 bool pmp; 311 bool epmp; 312 uint64_t resetvec; 313 } cfg; 314 }; 315 316 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) 317 { 318 return (env->misa_ext & ext) != 0; 319 } 320 321 static inline bool riscv_feature(CPURISCVState *env, int feature) 322 { 323 return env->features & (1ULL << feature); 324 } 325 326 #include "cpu_user.h" 327 328 extern const char * const riscv_int_regnames[]; 329 extern const char * const riscv_fpr_regnames[]; 330 331 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); 332 void riscv_cpu_do_interrupt(CPUState *cpu); 333 int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 334 int cpuid, void *opaque); 335 int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 336 int cpuid, void *opaque); 337 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 338 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 339 bool riscv_cpu_fp_enabled(CPURISCVState *env); 340 bool riscv_cpu_virt_enabled(CPURISCVState *env); 341 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); 342 bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env); 343 void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable); 344 bool riscv_cpu_two_stage_lookup(int mmu_idx); 345 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); 346 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 347 void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 348 MMUAccessType access_type, int mmu_idx, 349 uintptr_t retaddr) QEMU_NORETURN; 350 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 351 MMUAccessType access_type, int mmu_idx, 352 bool probe, uintptr_t retaddr); 353 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 354 vaddr addr, unsigned size, 355 MMUAccessType access_type, 356 int mmu_idx, MemTxAttrs attrs, 357 MemTxResult response, uintptr_t retaddr); 358 char *riscv_isa_string(RISCVCPU *cpu); 359 void riscv_cpu_list(void); 360 361 #define cpu_list riscv_cpu_list 362 #define cpu_mmu_index riscv_cpu_mmu_index 363 364 #ifndef CONFIG_USER_ONLY 365 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); 366 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); 367 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts); 368 uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value); 369 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ 370 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t), 371 uint32_t arg); 372 #endif 373 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); 374 375 void riscv_translate_init(void); 376 void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env, 377 uint32_t exception, uintptr_t pc); 378 379 target_ulong riscv_cpu_get_fflags(CPURISCVState *env); 380 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); 381 382 #define TB_FLAGS_PRIV_MMU_MASK 3 383 #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2) 384 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS 385 386 typedef CPURISCVState CPUArchState; 387 typedef RISCVCPU ArchCPU; 388 #include "exec/cpu-all.h" 389 390 FIELD(TB_FLAGS, MEM_IDX, 0, 3) 391 FIELD(TB_FLAGS, VL_EQ_VLMAX, 3, 1) 392 FIELD(TB_FLAGS, LMUL, 4, 2) 393 FIELD(TB_FLAGS, SEW, 6, 3) 394 FIELD(TB_FLAGS, VILL, 9, 1) 395 /* Is a Hypervisor instruction load/store allowed? */ 396 FIELD(TB_FLAGS, HLSX, 10, 1) 397 FIELD(TB_FLAGS, MSTATUS_HS_FS, 11, 2) 398 399 bool riscv_cpu_is_32bit(CPURISCVState *env); 400 401 /* 402 * A simplification for VLMAX 403 * = (1 << LMUL) * VLEN / (8 * (1 << SEW)) 404 * = (VLEN << LMUL) / (8 << SEW) 405 * = (VLEN << LMUL) >> (SEW + 3) 406 * = VLEN >> (SEW + 3 - LMUL) 407 */ 408 static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) 409 { 410 uint8_t sew, lmul; 411 412 sew = FIELD_EX64(vtype, VTYPE, VSEW); 413 lmul = FIELD_EX64(vtype, VTYPE, VLMUL); 414 return cpu->cfg.vlen >> (sew + 3 - lmul); 415 } 416 417 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 418 target_ulong *cs_base, uint32_t *pflags); 419 420 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, 421 target_ulong *ret_value, 422 target_ulong new_value, target_ulong write_mask); 423 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, 424 target_ulong *ret_value, 425 target_ulong new_value, 426 target_ulong write_mask); 427 428 static inline void riscv_csr_write(CPURISCVState *env, int csrno, 429 target_ulong val) 430 { 431 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); 432 } 433 434 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) 435 { 436 target_ulong val = 0; 437 riscv_csrrw(env, csrno, &val, 0, 0); 438 return val; 439 } 440 441 typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, 442 int csrno); 443 typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, 444 target_ulong *ret_value); 445 typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, 446 target_ulong new_value); 447 typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, 448 target_ulong *ret_value, 449 target_ulong new_value, 450 target_ulong write_mask); 451 452 typedef struct { 453 const char *name; 454 riscv_csr_predicate_fn predicate; 455 riscv_csr_read_fn read; 456 riscv_csr_write_fn write; 457 riscv_csr_op_fn op; 458 } riscv_csr_operations; 459 460 /* CSR function table constants */ 461 enum { 462 CSR_TABLE_SIZE = 0x1000 463 }; 464 465 /* CSR function table */ 466 extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; 467 468 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); 469 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); 470 471 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); 472 473 #endif /* RISCV_CPU_H */ 474