1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef RISCV_CPU_H 21 #define RISCV_CPU_H 22 23 #include "hw/core/cpu.h" 24 #include "hw/registerfields.h" 25 #include "exec/cpu-defs.h" 26 #include "fpu/softfloat-types.h" 27 #include "qom/object.h" 28 #include "qemu/int128.h" 29 #include "cpu_bits.h" 30 31 #define TCG_GUEST_DEFAULT_MO 0 32 33 #define TYPE_RISCV_CPU "riscv-cpu" 34 35 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU 36 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) 37 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU 38 39 #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") 40 #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") 41 #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") 42 #define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128") 43 #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") 44 #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") 45 #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") 46 #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") 47 #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") 48 #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") 49 #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") 50 51 #if defined(TARGET_RISCV32) 52 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 53 #elif defined(TARGET_RISCV64) 54 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 55 #endif 56 57 #define RV(x) ((target_ulong)1 << (x - 'A')) 58 59 #define RVI RV('I') 60 #define RVE RV('E') /* E and I are mutually exclusive */ 61 #define RVM RV('M') 62 #define RVA RV('A') 63 #define RVF RV('F') 64 #define RVD RV('D') 65 #define RVV RV('V') 66 #define RVC RV('C') 67 #define RVS RV('S') 68 #define RVU RV('U') 69 #define RVH RV('H') 70 #define RVJ RV('J') 71 72 /* S extension denotes that Supervisor mode exists, however it is possible 73 to have a core that support S mode but does not have an MMU and there 74 is currently no bit in misa to indicate whether an MMU exists or not 75 so a cpu features bitfield is required, likewise for optional PMP support */ 76 enum { 77 RISCV_FEATURE_MMU, 78 RISCV_FEATURE_PMP, 79 RISCV_FEATURE_EPMP, 80 RISCV_FEATURE_MISA 81 }; 82 83 #define PRIV_VERSION_1_10_0 0x00011000 84 #define PRIV_VERSION_1_11_0 0x00011100 85 86 #define VEXT_VERSION_1_00_0 0x00010000 87 88 enum { 89 TRANSLATE_SUCCESS, 90 TRANSLATE_FAIL, 91 TRANSLATE_PMP_FAIL, 92 TRANSLATE_G_STAGE_FAIL 93 }; 94 95 #define MMU_USER_IDX 3 96 97 #define MAX_RISCV_PMPS (16) 98 99 typedef struct CPURISCVState CPURISCVState; 100 101 #if !defined(CONFIG_USER_ONLY) 102 #include "pmp.h" 103 #endif 104 105 #define RV_VLEN_MAX 1024 106 107 FIELD(VTYPE, VLMUL, 0, 3) 108 FIELD(VTYPE, VSEW, 3, 3) 109 FIELD(VTYPE, VTA, 6, 1) 110 FIELD(VTYPE, VMA, 7, 1) 111 FIELD(VTYPE, VEDIV, 8, 2) 112 FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) 113 FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1) 114 115 struct CPURISCVState { 116 target_ulong gpr[32]; 117 target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ 118 uint64_t fpr[32]; /* assume both F and D extensions */ 119 120 /* vector coprocessor state. */ 121 uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); 122 target_ulong vxrm; 123 target_ulong vxsat; 124 target_ulong vl; 125 target_ulong vstart; 126 target_ulong vtype; 127 128 target_ulong pc; 129 target_ulong load_res; 130 target_ulong load_val; 131 132 target_ulong frm; 133 134 target_ulong badaddr; 135 uint32_t bins; 136 137 target_ulong guest_phys_fault_addr; 138 139 target_ulong priv_ver; 140 target_ulong bext_ver; 141 target_ulong vext_ver; 142 143 /* RISCVMXL, but uint32_t for vmstate migration */ 144 uint32_t misa_mxl; /* current mxl */ 145 uint32_t misa_mxl_max; /* max mxl for this cpu */ 146 uint32_t misa_ext; /* current extensions */ 147 uint32_t misa_ext_mask; /* max ext for this cpu */ 148 149 /* 128-bit helpers upper part return value */ 150 target_ulong retxh; 151 152 uint32_t features; 153 154 #ifdef CONFIG_USER_ONLY 155 uint32_t elf_flags; 156 #endif 157 158 #ifndef CONFIG_USER_ONLY 159 target_ulong priv; 160 /* This contains QEMU specific information about the virt state. */ 161 target_ulong virt; 162 target_ulong resetvec; 163 164 target_ulong mhartid; 165 /* 166 * For RV32 this is 32-bit mstatus and 32-bit mstatush. 167 * For RV64 this is a 64-bit mstatus. 168 */ 169 uint64_t mstatus; 170 171 target_ulong mip; 172 173 uint32_t miclaim; 174 175 target_ulong mie; 176 target_ulong mideleg; 177 178 target_ulong satp; /* since: priv-1.10.0 */ 179 target_ulong stval; 180 target_ulong medeleg; 181 182 target_ulong stvec; 183 target_ulong sepc; 184 target_ulong scause; 185 186 target_ulong mtvec; 187 target_ulong mepc; 188 target_ulong mcause; 189 target_ulong mtval; /* since: priv-1.10.0 */ 190 191 /* Hypervisor CSRs */ 192 target_ulong hstatus; 193 target_ulong hedeleg; 194 target_ulong hideleg; 195 target_ulong hcounteren; 196 target_ulong htval; 197 target_ulong htinst; 198 target_ulong hgatp; 199 uint64_t htimedelta; 200 201 /* Upper 64-bits of 128-bit CSRs */ 202 uint64_t mscratchh; 203 uint64_t sscratchh; 204 205 /* Virtual CSRs */ 206 /* 207 * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. 208 * For RV64 this is a 64-bit vsstatus. 209 */ 210 uint64_t vsstatus; 211 target_ulong vstvec; 212 target_ulong vsscratch; 213 target_ulong vsepc; 214 target_ulong vscause; 215 target_ulong vstval; 216 target_ulong vsatp; 217 218 target_ulong mtval2; 219 target_ulong mtinst; 220 221 /* HS Backup CSRs */ 222 target_ulong stvec_hs; 223 target_ulong sscratch_hs; 224 target_ulong sepc_hs; 225 target_ulong scause_hs; 226 target_ulong stval_hs; 227 target_ulong satp_hs; 228 uint64_t mstatus_hs; 229 230 /* Signals whether the current exception occurred with two-stage address 231 translation active. */ 232 bool two_stage_lookup; 233 234 target_ulong scounteren; 235 target_ulong mcounteren; 236 237 target_ulong sscratch; 238 target_ulong mscratch; 239 240 /* temporary htif regs */ 241 uint64_t mfromhost; 242 uint64_t mtohost; 243 uint64_t timecmp; 244 245 /* physical memory protection */ 246 pmp_table_t pmp_state; 247 target_ulong mseccfg; 248 249 /* machine specific rdtime callback */ 250 uint64_t (*rdtime_fn)(uint32_t); 251 uint32_t rdtime_fn_arg; 252 253 /* True if in debugger mode. */ 254 bool debugger; 255 256 /* 257 * CSRs for PointerMasking extension 258 */ 259 target_ulong mmte; 260 target_ulong mpmmask; 261 target_ulong mpmbase; 262 target_ulong spmmask; 263 target_ulong spmbase; 264 target_ulong upmmask; 265 target_ulong upmbase; 266 #endif 267 268 float_status fp_status; 269 270 /* Fields from here on are preserved across CPU reset. */ 271 QEMUTimer *timer; /* Internal timer */ 272 }; 273 274 OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass, 275 RISCV_CPU) 276 277 /** 278 * RISCVCPUClass: 279 * @parent_realize: The parent class' realize handler. 280 * @parent_reset: The parent class' reset handler. 281 * 282 * A RISCV CPU model. 283 */ 284 struct RISCVCPUClass { 285 /*< private >*/ 286 CPUClass parent_class; 287 /*< public >*/ 288 DeviceRealize parent_realize; 289 DeviceReset parent_reset; 290 }; 291 292 /** 293 * RISCVCPU: 294 * @env: #CPURISCVState 295 * 296 * A RISCV CPU. 297 */ 298 struct RISCVCPU { 299 /*< private >*/ 300 CPUState parent_obj; 301 /*< public >*/ 302 CPUNegativeOffsetState neg; 303 CPURISCVState env; 304 305 char *dyn_csr_xml; 306 char *dyn_vreg_xml; 307 308 /* Configuration Settings */ 309 struct { 310 bool ext_i; 311 bool ext_e; 312 bool ext_g; 313 bool ext_m; 314 bool ext_a; 315 bool ext_f; 316 bool ext_d; 317 bool ext_c; 318 bool ext_s; 319 bool ext_u; 320 bool ext_h; 321 bool ext_j; 322 bool ext_v; 323 bool ext_zba; 324 bool ext_zbb; 325 bool ext_zbc; 326 bool ext_zbs; 327 bool ext_counters; 328 bool ext_ifencei; 329 bool ext_icsr; 330 bool ext_zfh; 331 bool ext_zfhmin; 332 333 char *priv_spec; 334 char *user_spec; 335 char *bext_spec; 336 char *vext_spec; 337 uint16_t vlen; 338 uint16_t elen; 339 bool mmu; 340 bool pmp; 341 bool epmp; 342 uint64_t resetvec; 343 } cfg; 344 }; 345 346 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) 347 { 348 return (env->misa_ext & ext) != 0; 349 } 350 351 static inline bool riscv_feature(CPURISCVState *env, int feature) 352 { 353 return env->features & (1ULL << feature); 354 } 355 356 #include "cpu_user.h" 357 358 extern const char * const riscv_int_regnames[]; 359 extern const char * const riscv_int_regnamesh[]; 360 extern const char * const riscv_fpr_regnames[]; 361 362 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); 363 void riscv_cpu_do_interrupt(CPUState *cpu); 364 int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 365 int cpuid, void *opaque); 366 int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 367 int cpuid, void *opaque); 368 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 369 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 370 bool riscv_cpu_fp_enabled(CPURISCVState *env); 371 bool riscv_cpu_vector_enabled(CPURISCVState *env); 372 bool riscv_cpu_virt_enabled(CPURISCVState *env); 373 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); 374 bool riscv_cpu_two_stage_lookup(int mmu_idx); 375 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); 376 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 377 void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 378 MMUAccessType access_type, int mmu_idx, 379 uintptr_t retaddr) QEMU_NORETURN; 380 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 381 MMUAccessType access_type, int mmu_idx, 382 bool probe, uintptr_t retaddr); 383 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 384 vaddr addr, unsigned size, 385 MMUAccessType access_type, 386 int mmu_idx, MemTxAttrs attrs, 387 MemTxResult response, uintptr_t retaddr); 388 char *riscv_isa_string(RISCVCPU *cpu); 389 void riscv_cpu_list(void); 390 391 #define cpu_list riscv_cpu_list 392 #define cpu_mmu_index riscv_cpu_mmu_index 393 394 #ifndef CONFIG_USER_ONLY 395 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); 396 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); 397 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts); 398 uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value); 399 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ 400 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t), 401 uint32_t arg); 402 #endif 403 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); 404 405 void riscv_translate_init(void); 406 void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env, 407 uint32_t exception, uintptr_t pc); 408 409 target_ulong riscv_cpu_get_fflags(CPURISCVState *env); 410 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); 411 412 #define TB_FLAGS_PRIV_MMU_MASK 3 413 #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2) 414 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS 415 #define TB_FLAGS_MSTATUS_VS MSTATUS_VS 416 417 typedef CPURISCVState CPUArchState; 418 typedef RISCVCPU ArchCPU; 419 #include "exec/cpu-all.h" 420 421 FIELD(TB_FLAGS, MEM_IDX, 0, 3) 422 FIELD(TB_FLAGS, LMUL, 3, 3) 423 FIELD(TB_FLAGS, SEW, 6, 3) 424 /* Skip MSTATUS_VS (0x600) bits */ 425 FIELD(TB_FLAGS, VL_EQ_VLMAX, 11, 1) 426 FIELD(TB_FLAGS, VILL, 12, 1) 427 /* Skip MSTATUS_FS (0x6000) bits */ 428 /* Is a Hypervisor instruction load/store allowed? */ 429 FIELD(TB_FLAGS, HLSX, 15, 1) 430 FIELD(TB_FLAGS, MSTATUS_HS_FS, 16, 2) 431 FIELD(TB_FLAGS, MSTATUS_HS_VS, 18, 2) 432 /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ 433 FIELD(TB_FLAGS, XL, 20, 2) 434 /* If PointerMasking should be applied */ 435 FIELD(TB_FLAGS, PM_ENABLED, 22, 1) 436 437 #ifdef TARGET_RISCV32 438 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) 439 #else 440 static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) 441 { 442 return env->misa_mxl; 443 } 444 #endif 445 446 /* 447 * Encode LMUL to lmul as follows: 448 * LMUL vlmul lmul 449 * 1 000 0 450 * 2 001 1 451 * 4 010 2 452 * 8 011 3 453 * - 100 - 454 * 1/8 101 -3 455 * 1/4 110 -2 456 * 1/2 111 -1 457 * 458 * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul) 459 * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8 460 * => VLMAX = vlen >> (1 + 3 - (-3)) 461 * = 256 >> 7 462 * = 2 463 */ 464 static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) 465 { 466 uint8_t sew = FIELD_EX64(vtype, VTYPE, VSEW); 467 int8_t lmul = sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3); 468 return cpu->cfg.vlen >> (sew + 3 - lmul); 469 } 470 471 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 472 target_ulong *cs_base, uint32_t *pflags); 473 474 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, 475 target_ulong *ret_value, 476 target_ulong new_value, target_ulong write_mask); 477 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, 478 target_ulong *ret_value, 479 target_ulong new_value, 480 target_ulong write_mask); 481 482 static inline void riscv_csr_write(CPURISCVState *env, int csrno, 483 target_ulong val) 484 { 485 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); 486 } 487 488 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) 489 { 490 target_ulong val = 0; 491 riscv_csrrw(env, csrno, &val, 0, 0); 492 return val; 493 } 494 495 typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, 496 int csrno); 497 typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, 498 target_ulong *ret_value); 499 typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, 500 target_ulong new_value); 501 typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, 502 target_ulong *ret_value, 503 target_ulong new_value, 504 target_ulong write_mask); 505 506 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, 507 Int128 *ret_value, 508 Int128 new_value, Int128 write_mask); 509 510 typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno, 511 Int128 *ret_value); 512 typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int csrno, 513 Int128 new_value); 514 515 typedef struct { 516 const char *name; 517 riscv_csr_predicate_fn predicate; 518 riscv_csr_read_fn read; 519 riscv_csr_write_fn write; 520 riscv_csr_op_fn op; 521 riscv_csr_read128_fn read128; 522 riscv_csr_write128_fn write128; 523 } riscv_csr_operations; 524 525 /* CSR function table constants */ 526 enum { 527 CSR_TABLE_SIZE = 0x1000 528 }; 529 530 /* CSR function table */ 531 extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; 532 533 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); 534 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); 535 536 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); 537 538 #endif /* RISCV_CPU_H */ 539