1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef RISCV_CPU_H 21 #define RISCV_CPU_H 22 23 #include "hw/core/cpu.h" 24 #include "exec/cpu-defs.h" 25 #include "fpu/softfloat-types.h" 26 27 #define TCG_GUEST_DEFAULT_MO 0 28 29 #define TYPE_RISCV_CPU "riscv-cpu" 30 31 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU 32 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) 33 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU 34 35 #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") 36 #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") 37 #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") 38 #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") 39 #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") 40 #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") 41 #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") 42 /* Deprecated */ 43 #define TYPE_RISCV_CPU_RV32IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv32imacu-nommu") 44 #define TYPE_RISCV_CPU_RV32GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9.1") 45 #define TYPE_RISCV_CPU_RV32GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.10.0") 46 #define TYPE_RISCV_CPU_RV64IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv64imacu-nommu") 47 #define TYPE_RISCV_CPU_RV64GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.9.1") 48 #define TYPE_RISCV_CPU_RV64GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.10.0") 49 50 #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2)) 51 #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2)) 52 53 #if defined(TARGET_RISCV32) 54 #define RVXLEN RV32 55 #elif defined(TARGET_RISCV64) 56 #define RVXLEN RV64 57 #endif 58 59 #define RV(x) ((target_ulong)1 << (x - 'A')) 60 61 #define RVI RV('I') 62 #define RVE RV('E') /* E and I are mutually exclusive */ 63 #define RVM RV('M') 64 #define RVA RV('A') 65 #define RVF RV('F') 66 #define RVD RV('D') 67 #define RVC RV('C') 68 #define RVS RV('S') 69 #define RVU RV('U') 70 #define RVH RV('H') 71 72 /* S extension denotes that Supervisor mode exists, however it is possible 73 to have a core that support S mode but does not have an MMU and there 74 is currently no bit in misa to indicate whether an MMU exists or not 75 so a cpu features bitfield is required, likewise for optional PMP support */ 76 enum { 77 RISCV_FEATURE_MMU, 78 RISCV_FEATURE_PMP, 79 RISCV_FEATURE_MISA 80 }; 81 82 #define PRIV_VERSION_1_09_1 0x00010901 83 #define PRIV_VERSION_1_10_0 0x00011000 84 #define PRIV_VERSION_1_11_0 0x00011100 85 86 #define TRANSLATE_PMP_FAIL 2 87 #define TRANSLATE_FAIL 1 88 #define TRANSLATE_SUCCESS 0 89 #define MMU_USER_IDX 3 90 91 #define MAX_RISCV_PMPS (16) 92 93 typedef struct CPURISCVState CPURISCVState; 94 95 #include "pmp.h" 96 97 struct CPURISCVState { 98 target_ulong gpr[32]; 99 uint64_t fpr[32]; /* assume both F and D extensions */ 100 target_ulong pc; 101 target_ulong load_res; 102 target_ulong load_val; 103 104 target_ulong frm; 105 106 target_ulong badaddr; 107 108 target_ulong priv_ver; 109 target_ulong misa; 110 target_ulong misa_mask; 111 112 uint32_t features; 113 114 #ifdef CONFIG_USER_ONLY 115 uint32_t elf_flags; 116 #endif 117 118 #ifndef CONFIG_USER_ONLY 119 target_ulong priv; 120 /* This contains QEMU specific information about the virt state. */ 121 target_ulong virt; 122 target_ulong resetvec; 123 124 target_ulong mhartid; 125 target_ulong mstatus; 126 127 target_ulong mip; 128 129 uint32_t miclaim; 130 131 target_ulong mie; 132 target_ulong mideleg; 133 134 target_ulong sptbr; /* until: priv-1.9.1 */ 135 target_ulong satp; /* since: priv-1.10.0 */ 136 target_ulong sbadaddr; 137 target_ulong mbadaddr; 138 target_ulong medeleg; 139 140 target_ulong stvec; 141 target_ulong sepc; 142 target_ulong scause; 143 144 target_ulong mtvec; 145 target_ulong mepc; 146 target_ulong mcause; 147 target_ulong mtval; /* since: priv-1.10.0 */ 148 149 /* Hypervisor CSRs */ 150 target_ulong hstatus; 151 target_ulong hedeleg; 152 target_ulong hideleg; 153 target_ulong hcounteren; 154 target_ulong htval; 155 target_ulong htinst; 156 target_ulong hgatp; 157 158 /* Virtual CSRs */ 159 target_ulong vsstatus; 160 target_ulong vstvec; 161 target_ulong vsscratch; 162 target_ulong vsepc; 163 target_ulong vscause; 164 target_ulong vstval; 165 target_ulong vsatp; 166 167 target_ulong mtval2; 168 target_ulong mtinst; 169 170 /* HS Backup CSRs */ 171 target_ulong stvec_hs; 172 target_ulong sscratch_hs; 173 target_ulong sepc_hs; 174 target_ulong scause_hs; 175 target_ulong stval_hs; 176 target_ulong satp_hs; 177 target_ulong mstatus_hs; 178 179 target_ulong scounteren; 180 target_ulong mcounteren; 181 182 target_ulong sscratch; 183 target_ulong mscratch; 184 185 /* temporary htif regs */ 186 uint64_t mfromhost; 187 uint64_t mtohost; 188 uint64_t timecmp; 189 190 /* physical memory protection */ 191 pmp_table_t pmp_state; 192 193 /* True if in debugger mode. */ 194 bool debugger; 195 #endif 196 197 float_status fp_status; 198 199 /* Fields from here on are preserved across CPU reset. */ 200 QEMUTimer *timer; /* Internal timer */ 201 }; 202 203 #define RISCV_CPU_CLASS(klass) \ 204 OBJECT_CLASS_CHECK(RISCVCPUClass, (klass), TYPE_RISCV_CPU) 205 #define RISCV_CPU(obj) \ 206 OBJECT_CHECK(RISCVCPU, (obj), TYPE_RISCV_CPU) 207 #define RISCV_CPU_GET_CLASS(obj) \ 208 OBJECT_GET_CLASS(RISCVCPUClass, (obj), TYPE_RISCV_CPU) 209 210 /** 211 * RISCVCPUClass: 212 * @parent_realize: The parent class' realize handler. 213 * @parent_reset: The parent class' reset handler. 214 * 215 * A RISCV CPU model. 216 */ 217 typedef struct RISCVCPUClass { 218 /*< private >*/ 219 CPUClass parent_class; 220 /*< public >*/ 221 DeviceRealize parent_realize; 222 void (*parent_reset)(CPUState *cpu); 223 } RISCVCPUClass; 224 225 /** 226 * RISCVCPU: 227 * @env: #CPURISCVState 228 * 229 * A RISCV CPU. 230 */ 231 typedef struct RISCVCPU { 232 /*< private >*/ 233 CPUState parent_obj; 234 /*< public >*/ 235 CPUNegativeOffsetState neg; 236 CPURISCVState env; 237 238 /* Configuration Settings */ 239 struct { 240 bool ext_i; 241 bool ext_e; 242 bool ext_g; 243 bool ext_m; 244 bool ext_a; 245 bool ext_f; 246 bool ext_d; 247 bool ext_c; 248 bool ext_s; 249 bool ext_u; 250 bool ext_counters; 251 bool ext_ifencei; 252 bool ext_icsr; 253 254 char *priv_spec; 255 char *user_spec; 256 bool mmu; 257 bool pmp; 258 } cfg; 259 } RISCVCPU; 260 261 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) 262 { 263 return (env->misa & ext) != 0; 264 } 265 266 static inline bool riscv_feature(CPURISCVState *env, int feature) 267 { 268 return env->features & (1ULL << feature); 269 } 270 271 #include "cpu_user.h" 272 #include "cpu_bits.h" 273 274 extern const char * const riscv_int_regnames[]; 275 extern const char * const riscv_fpr_regnames[]; 276 extern const char * const riscv_excp_names[]; 277 extern const char * const riscv_intr_names[]; 278 279 void riscv_cpu_do_interrupt(CPUState *cpu); 280 int riscv_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 281 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 282 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); 283 bool riscv_cpu_fp_enabled(CPURISCVState *env); 284 bool riscv_cpu_virt_enabled(CPURISCVState *env); 285 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); 286 bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env); 287 void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable); 288 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); 289 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 290 void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 291 MMUAccessType access_type, int mmu_idx, 292 uintptr_t retaddr); 293 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 294 MMUAccessType access_type, int mmu_idx, 295 bool probe, uintptr_t retaddr); 296 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 297 vaddr addr, unsigned size, 298 MMUAccessType access_type, 299 int mmu_idx, MemTxAttrs attrs, 300 MemTxResult response, uintptr_t retaddr); 301 char *riscv_isa_string(RISCVCPU *cpu); 302 void riscv_cpu_list(void); 303 304 #define cpu_signal_handler riscv_cpu_signal_handler 305 #define cpu_list riscv_cpu_list 306 #define cpu_mmu_index riscv_cpu_mmu_index 307 308 #ifndef CONFIG_USER_ONLY 309 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); 310 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts); 311 uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value); 312 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ 313 #endif 314 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); 315 316 void riscv_translate_init(void); 317 int riscv_cpu_signal_handler(int host_signum, void *pinfo, void *puc); 318 void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env, 319 uint32_t exception, uintptr_t pc); 320 321 target_ulong riscv_cpu_get_fflags(CPURISCVState *env); 322 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); 323 324 #define TB_FLAGS_MMU_MASK 3 325 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS 326 327 static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 328 target_ulong *cs_base, uint32_t *flags) 329 { 330 *pc = env->pc; 331 *cs_base = 0; 332 #ifdef CONFIG_USER_ONLY 333 *flags = TB_FLAGS_MSTATUS_FS; 334 #else 335 *flags = cpu_mmu_index(env, 0); 336 if (riscv_cpu_fp_enabled(env)) { 337 *flags |= env->mstatus & MSTATUS_FS; 338 } 339 #endif 340 } 341 342 int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, 343 target_ulong new_value, target_ulong write_mask); 344 int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value, 345 target_ulong new_value, target_ulong write_mask); 346 347 static inline void riscv_csr_write(CPURISCVState *env, int csrno, 348 target_ulong val) 349 { 350 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); 351 } 352 353 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) 354 { 355 target_ulong val = 0; 356 riscv_csrrw(env, csrno, &val, 0, 0); 357 return val; 358 } 359 360 typedef int (*riscv_csr_predicate_fn)(CPURISCVState *env, int csrno); 361 typedef int (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, 362 target_ulong *ret_value); 363 typedef int (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, 364 target_ulong new_value); 365 typedef int (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, 366 target_ulong *ret_value, target_ulong new_value, target_ulong write_mask); 367 368 typedef struct { 369 riscv_csr_predicate_fn predicate; 370 riscv_csr_read_fn read; 371 riscv_csr_write_fn write; 372 riscv_csr_op_fn op; 373 } riscv_csr_operations; 374 375 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); 376 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); 377 378 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); 379 380 typedef CPURISCVState CPUArchState; 381 typedef RISCVCPU ArchCPU; 382 383 #include "exec/cpu-all.h" 384 385 #endif /* RISCV_CPU_H */ 386