1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef RISCV_CPU_H 21 #define RISCV_CPU_H 22 23 #include "hw/core/cpu.h" 24 #include "hw/registerfields.h" 25 #include "exec/cpu-defs.h" 26 #include "qemu/cpu-float.h" 27 #include "qom/object.h" 28 #include "qemu/int128.h" 29 #include "cpu_bits.h" 30 31 #define TCG_GUEST_DEFAULT_MO 0 32 33 /* 34 * RISC-V-specific extra insn start words: 35 * 1: Original instruction opcode 36 */ 37 #define TARGET_INSN_START_EXTRA_WORDS 1 38 39 #define TYPE_RISCV_CPU "riscv-cpu" 40 41 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU 42 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) 43 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU 44 45 #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") 46 #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") 47 #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") 48 #define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128") 49 #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") 50 #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") 51 #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") 52 #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") 53 #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") 54 #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") 55 #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") 56 #define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906") 57 #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") 58 59 #if defined(TARGET_RISCV32) 60 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 61 #elif defined(TARGET_RISCV64) 62 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 63 #endif 64 65 #define RV(x) ((target_ulong)1 << (x - 'A')) 66 67 /* 68 * Consider updating register_cpu_props() when adding 69 * new MISA bits here. 70 */ 71 #define RVI RV('I') 72 #define RVE RV('E') /* E and I are mutually exclusive */ 73 #define RVM RV('M') 74 #define RVA RV('A') 75 #define RVF RV('F') 76 #define RVD RV('D') 77 #define RVV RV('V') 78 #define RVC RV('C') 79 #define RVS RV('S') 80 #define RVU RV('U') 81 #define RVH RV('H') 82 #define RVJ RV('J') 83 84 85 /* Privileged specification version */ 86 enum { 87 PRIV_VERSION_1_10_0 = 0, 88 PRIV_VERSION_1_11_0, 89 PRIV_VERSION_1_12_0, 90 }; 91 92 #define VEXT_VERSION_1_00_0 0x00010000 93 94 enum { 95 TRANSLATE_SUCCESS, 96 TRANSLATE_FAIL, 97 TRANSLATE_PMP_FAIL, 98 TRANSLATE_G_STAGE_FAIL 99 }; 100 101 #define MMU_USER_IDX 3 102 103 #define MAX_RISCV_PMPS (16) 104 105 typedef struct CPUArchState CPURISCVState; 106 107 #if !defined(CONFIG_USER_ONLY) 108 #include "pmp.h" 109 #include "debug.h" 110 #endif 111 112 #define RV_VLEN_MAX 1024 113 #define RV_MAX_MHPMEVENTS 32 114 #define RV_MAX_MHPMCOUNTERS 32 115 116 FIELD(VTYPE, VLMUL, 0, 3) 117 FIELD(VTYPE, VSEW, 3, 3) 118 FIELD(VTYPE, VTA, 6, 1) 119 FIELD(VTYPE, VMA, 7, 1) 120 FIELD(VTYPE, VEDIV, 8, 2) 121 FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) 122 123 typedef struct PMUCTRState { 124 /* Current value of a counter */ 125 target_ulong mhpmcounter_val; 126 /* Current value of a counter in RV32*/ 127 target_ulong mhpmcounterh_val; 128 /* Snapshot values of counter */ 129 target_ulong mhpmcounter_prev; 130 /* Snapshort value of a counter in RV32 */ 131 target_ulong mhpmcounterh_prev; 132 bool started; 133 /* Value beyond UINT32_MAX/UINT64_MAX before overflow interrupt trigger */ 134 target_ulong irq_overflow_left; 135 } PMUCTRState; 136 137 struct CPUArchState { 138 target_ulong gpr[32]; 139 target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ 140 141 /* vector coprocessor state. */ 142 uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); 143 target_ulong vxrm; 144 target_ulong vxsat; 145 target_ulong vl; 146 target_ulong vstart; 147 target_ulong vtype; 148 bool vill; 149 150 target_ulong pc; 151 target_ulong load_res; 152 target_ulong load_val; 153 154 /* Floating-Point state */ 155 uint64_t fpr[32]; /* assume both F and D extensions */ 156 target_ulong frm; 157 float_status fp_status; 158 159 target_ulong badaddr; 160 target_ulong bins; 161 162 target_ulong guest_phys_fault_addr; 163 164 target_ulong priv_ver; 165 target_ulong bext_ver; 166 target_ulong vext_ver; 167 168 /* RISCVMXL, but uint32_t for vmstate migration */ 169 uint32_t misa_mxl; /* current mxl */ 170 uint32_t misa_mxl_max; /* max mxl for this cpu */ 171 uint32_t misa_ext; /* current extensions */ 172 uint32_t misa_ext_mask; /* max ext for this cpu */ 173 uint32_t xl; /* current xlen */ 174 175 /* 128-bit helpers upper part return value */ 176 target_ulong retxh; 177 178 uint32_t features; 179 180 #ifdef CONFIG_USER_ONLY 181 uint32_t elf_flags; 182 #endif 183 184 #ifndef CONFIG_USER_ONLY 185 target_ulong priv; 186 /* This contains QEMU specific information about the virt state. */ 187 target_ulong virt; 188 target_ulong geilen; 189 uint64_t resetvec; 190 191 target_ulong mhartid; 192 /* 193 * For RV32 this is 32-bit mstatus and 32-bit mstatush. 194 * For RV64 this is a 64-bit mstatus. 195 */ 196 uint64_t mstatus; 197 198 uint64_t mip; 199 /* 200 * MIP contains the software writable version of SEIP ORed with the 201 * external interrupt value. The MIP register is always up-to-date. 202 * To keep track of the current source, we also save booleans of the values 203 * here. 204 */ 205 bool external_seip; 206 bool software_seip; 207 208 uint64_t miclaim; 209 210 uint64_t mie; 211 uint64_t mideleg; 212 213 target_ulong satp; /* since: priv-1.10.0 */ 214 target_ulong stval; 215 target_ulong medeleg; 216 217 target_ulong stvec; 218 target_ulong sepc; 219 target_ulong scause; 220 221 target_ulong mtvec; 222 target_ulong mepc; 223 target_ulong mcause; 224 target_ulong mtval; /* since: priv-1.10.0 */ 225 226 /* Machine and Supervisor interrupt priorities */ 227 uint8_t miprio[64]; 228 uint8_t siprio[64]; 229 230 /* AIA CSRs */ 231 target_ulong miselect; 232 target_ulong siselect; 233 234 /* Hypervisor CSRs */ 235 target_ulong hstatus; 236 target_ulong hedeleg; 237 uint64_t hideleg; 238 target_ulong hcounteren; 239 target_ulong htval; 240 target_ulong htinst; 241 target_ulong hgatp; 242 target_ulong hgeie; 243 target_ulong hgeip; 244 uint64_t htimedelta; 245 246 /* Hypervisor controlled virtual interrupt priorities */ 247 target_ulong hvictl; 248 uint8_t hviprio[64]; 249 250 /* Upper 64-bits of 128-bit CSRs */ 251 uint64_t mscratchh; 252 uint64_t sscratchh; 253 254 /* Virtual CSRs */ 255 /* 256 * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. 257 * For RV64 this is a 64-bit vsstatus. 258 */ 259 uint64_t vsstatus; 260 target_ulong vstvec; 261 target_ulong vsscratch; 262 target_ulong vsepc; 263 target_ulong vscause; 264 target_ulong vstval; 265 target_ulong vsatp; 266 267 /* AIA VS-mode CSRs */ 268 target_ulong vsiselect; 269 270 target_ulong mtval2; 271 target_ulong mtinst; 272 273 /* HS Backup CSRs */ 274 target_ulong stvec_hs; 275 target_ulong sscratch_hs; 276 target_ulong sepc_hs; 277 target_ulong scause_hs; 278 target_ulong stval_hs; 279 target_ulong satp_hs; 280 uint64_t mstatus_hs; 281 282 /* Signals whether the current exception occurred with two-stage address 283 translation active. */ 284 bool two_stage_lookup; 285 /* 286 * Signals whether the current exception occurred while doing two-stage 287 * address translation for the VS-stage page table walk. 288 */ 289 bool two_stage_indirect_lookup; 290 291 target_ulong scounteren; 292 target_ulong mcounteren; 293 294 target_ulong mcountinhibit; 295 296 /* PMU counter state */ 297 PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS]; 298 299 /* PMU event selector configured values. First three are unused*/ 300 target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS]; 301 302 /* PMU event selector configured values for RV32*/ 303 target_ulong mhpmeventh_val[RV_MAX_MHPMEVENTS]; 304 305 target_ulong sscratch; 306 target_ulong mscratch; 307 308 /* Sstc CSRs */ 309 uint64_t stimecmp; 310 311 uint64_t vstimecmp; 312 313 /* physical memory protection */ 314 pmp_table_t pmp_state; 315 target_ulong mseccfg; 316 317 /* trigger module */ 318 target_ulong trigger_cur; 319 target_ulong tdata1[RV_MAX_TRIGGERS]; 320 target_ulong tdata2[RV_MAX_TRIGGERS]; 321 target_ulong tdata3[RV_MAX_TRIGGERS]; 322 struct CPUBreakpoint *cpu_breakpoint[RV_MAX_TRIGGERS]; 323 struct CPUWatchpoint *cpu_watchpoint[RV_MAX_TRIGGERS]; 324 QEMUTimer *itrigger_timer[RV_MAX_TRIGGERS]; 325 int64_t last_icount; 326 bool itrigger_enabled; 327 328 /* machine specific rdtime callback */ 329 uint64_t (*rdtime_fn)(void *); 330 void *rdtime_fn_arg; 331 332 /* machine specific AIA ireg read-modify-write callback */ 333 #define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \ 334 ((((__xlen) & 0xff) << 24) | \ 335 (((__vgein) & 0x3f) << 20) | \ 336 (((__virt) & 0x1) << 18) | \ 337 (((__priv) & 0x3) << 16) | \ 338 (__isel & 0xffff)) 339 #define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff) 340 #define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3) 341 #define AIA_IREG_VIRT(__ireg) (((__ireg) >> 18) & 0x1) 342 #define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 20) & 0x3f) 343 #define AIA_IREG_XLEN(__ireg) (((__ireg) >> 24) & 0xff) 344 int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg, 345 target_ulong *val, target_ulong new_val, target_ulong write_mask); 346 void *aia_ireg_rmw_fn_arg[4]; 347 348 /* True if in debugger mode. */ 349 bool debugger; 350 351 /* 352 * CSRs for PointerMasking extension 353 */ 354 target_ulong mmte; 355 target_ulong mpmmask; 356 target_ulong mpmbase; 357 target_ulong spmmask; 358 target_ulong spmbase; 359 target_ulong upmmask; 360 target_ulong upmbase; 361 362 /* CSRs for execution enviornment configuration */ 363 uint64_t menvcfg; 364 uint64_t mstateen[SMSTATEEN_MAX_COUNT]; 365 uint64_t hstateen[SMSTATEEN_MAX_COUNT]; 366 uint64_t sstateen[SMSTATEEN_MAX_COUNT]; 367 target_ulong senvcfg; 368 uint64_t henvcfg; 369 #endif 370 target_ulong cur_pmmask; 371 target_ulong cur_pmbase; 372 373 /* Fields from here on are preserved across CPU reset. */ 374 QEMUTimer *stimer; /* Internal timer for S-mode interrupt */ 375 QEMUTimer *vstimer; /* Internal timer for VS-mode interrupt */ 376 bool vstime_irq; 377 378 hwaddr kernel_addr; 379 hwaddr fdt_addr; 380 381 /* kvm timer */ 382 bool kvm_timer_dirty; 383 uint64_t kvm_timer_time; 384 uint64_t kvm_timer_compare; 385 uint64_t kvm_timer_state; 386 uint64_t kvm_timer_frequency; 387 }; 388 389 OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) 390 391 /** 392 * RISCVCPUClass: 393 * @parent_realize: The parent class' realize handler. 394 * @parent_phases: The parent class' reset phase handlers. 395 * 396 * A RISCV CPU model. 397 */ 398 struct RISCVCPUClass { 399 /*< private >*/ 400 CPUClass parent_class; 401 /*< public >*/ 402 DeviceRealize parent_realize; 403 ResettablePhases parent_phases; 404 }; 405 406 struct RISCVCPUConfig { 407 bool ext_i; 408 bool ext_e; 409 bool ext_g; 410 bool ext_m; 411 bool ext_a; 412 bool ext_f; 413 bool ext_d; 414 bool ext_c; 415 bool ext_s; 416 bool ext_u; 417 bool ext_h; 418 bool ext_j; 419 bool ext_v; 420 bool ext_zba; 421 bool ext_zbb; 422 bool ext_zbc; 423 bool ext_zbkb; 424 bool ext_zbkc; 425 bool ext_zbkx; 426 bool ext_zbs; 427 bool ext_zk; 428 bool ext_zkn; 429 bool ext_zknd; 430 bool ext_zkne; 431 bool ext_zknh; 432 bool ext_zkr; 433 bool ext_zks; 434 bool ext_zksed; 435 bool ext_zksh; 436 bool ext_zkt; 437 bool ext_ifencei; 438 bool ext_icsr; 439 bool ext_zihintpause; 440 bool ext_smstateen; 441 bool ext_sstc; 442 bool ext_svinval; 443 bool ext_svnapot; 444 bool ext_svpbmt; 445 bool ext_zdinx; 446 bool ext_zawrs; 447 bool ext_zfh; 448 bool ext_zfhmin; 449 bool ext_zfinx; 450 bool ext_zhinx; 451 bool ext_zhinxmin; 452 bool ext_zve32f; 453 bool ext_zve64f; 454 bool ext_zmmul; 455 bool ext_smaia; 456 bool ext_ssaia; 457 bool ext_sscofpmf; 458 bool rvv_ta_all_1s; 459 bool rvv_ma_all_1s; 460 461 uint32_t mvendorid; 462 uint64_t marchid; 463 uint64_t mimpid; 464 465 /* Vendor-specific custom extensions */ 466 bool ext_xtheadba; 467 bool ext_xtheadbb; 468 bool ext_xtheadbs; 469 bool ext_xtheadcmo; 470 bool ext_xtheadcondmov; 471 bool ext_xtheadfmemidx; 472 bool ext_xtheadfmv; 473 bool ext_xtheadmac; 474 bool ext_xtheadmemidx; 475 bool ext_xtheadmempair; 476 bool ext_xtheadsync; 477 bool ext_XVentanaCondOps; 478 479 uint8_t pmu_num; 480 char *priv_spec; 481 char *user_spec; 482 char *bext_spec; 483 char *vext_spec; 484 uint16_t vlen; 485 uint16_t elen; 486 bool mmu; 487 bool pmp; 488 bool epmp; 489 bool debug; 490 bool misa_w; 491 492 bool short_isa_string; 493 }; 494 495 typedef struct RISCVCPUConfig RISCVCPUConfig; 496 497 /** 498 * RISCVCPU: 499 * @env: #CPURISCVState 500 * 501 * A RISCV CPU. 502 */ 503 struct ArchCPU { 504 /*< private >*/ 505 CPUState parent_obj; 506 /*< public >*/ 507 CPUNegativeOffsetState neg; 508 CPURISCVState env; 509 510 char *dyn_csr_xml; 511 char *dyn_vreg_xml; 512 513 /* Configuration Settings */ 514 RISCVCPUConfig cfg; 515 516 QEMUTimer *pmu_timer; 517 /* A bitmask of Available programmable counters */ 518 uint32_t pmu_avail_ctrs; 519 /* Mapping of events to counters */ 520 GHashTable *pmu_event_ctr_map; 521 }; 522 523 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) 524 { 525 return (env->misa_ext & ext) != 0; 526 } 527 528 static inline bool riscv_feature(CPURISCVState *env, int feature) 529 { 530 return env->features & (1ULL << feature); 531 } 532 533 static inline void riscv_set_feature(CPURISCVState *env, int feature) 534 { 535 env->features |= (1ULL << feature); 536 } 537 538 #include "cpu_user.h" 539 540 extern const char * const riscv_int_regnames[]; 541 extern const char * const riscv_int_regnamesh[]; 542 extern const char * const riscv_fpr_regnames[]; 543 544 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); 545 void riscv_cpu_do_interrupt(CPUState *cpu); 546 int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 547 int cpuid, DumpState *s); 548 int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 549 int cpuid, DumpState *s); 550 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 551 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 552 int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero); 553 uint8_t riscv_cpu_default_priority(int irq); 554 uint64_t riscv_cpu_all_pending(CPURISCVState *env); 555 int riscv_cpu_mirq_pending(CPURISCVState *env); 556 int riscv_cpu_sirq_pending(CPURISCVState *env); 557 int riscv_cpu_vsirq_pending(CPURISCVState *env); 558 bool riscv_cpu_fp_enabled(CPURISCVState *env); 559 target_ulong riscv_cpu_get_geilen(CPURISCVState *env); 560 void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); 561 bool riscv_cpu_vector_enabled(CPURISCVState *env); 562 bool riscv_cpu_virt_enabled(CPURISCVState *env); 563 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); 564 bool riscv_cpu_two_stage_lookup(int mmu_idx); 565 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); 566 G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 567 MMUAccessType access_type, int mmu_idx, 568 uintptr_t retaddr); 569 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 570 MMUAccessType access_type, int mmu_idx, 571 bool probe, uintptr_t retaddr); 572 char *riscv_isa_string(RISCVCPU *cpu); 573 void riscv_cpu_list(void); 574 575 #define cpu_list riscv_cpu_list 576 #define cpu_mmu_index riscv_cpu_mmu_index 577 578 #ifndef CONFIG_USER_ONLY 579 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 580 vaddr addr, unsigned size, 581 MMUAccessType access_type, 582 int mmu_idx, MemTxAttrs attrs, 583 MemTxResult response, uintptr_t retaddr); 584 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 585 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); 586 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); 587 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); 588 uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value); 589 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ 590 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), 591 void *arg); 592 void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, 593 int (*rmw_fn)(void *arg, 594 target_ulong reg, 595 target_ulong *val, 596 target_ulong new_val, 597 target_ulong write_mask), 598 void *rmw_fn_arg); 599 #endif 600 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); 601 602 void riscv_translate_init(void); 603 G_NORETURN void riscv_raise_exception(CPURISCVState *env, 604 uint32_t exception, uintptr_t pc); 605 606 target_ulong riscv_cpu_get_fflags(CPURISCVState *env); 607 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); 608 609 #define TB_FLAGS_PRIV_MMU_MASK 3 610 #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2) 611 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS 612 #define TB_FLAGS_MSTATUS_VS MSTATUS_VS 613 614 #include "exec/cpu-all.h" 615 616 FIELD(TB_FLAGS, MEM_IDX, 0, 3) 617 FIELD(TB_FLAGS, LMUL, 3, 3) 618 FIELD(TB_FLAGS, SEW, 6, 3) 619 /* Skip MSTATUS_VS (0x600) bits */ 620 FIELD(TB_FLAGS, VL_EQ_VLMAX, 11, 1) 621 FIELD(TB_FLAGS, VILL, 12, 1) 622 /* Skip MSTATUS_FS (0x6000) bits */ 623 /* Is a Hypervisor instruction load/store allowed? */ 624 FIELD(TB_FLAGS, HLSX, 15, 1) 625 FIELD(TB_FLAGS, MSTATUS_HS_FS, 16, 2) 626 FIELD(TB_FLAGS, MSTATUS_HS_VS, 18, 2) 627 /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ 628 FIELD(TB_FLAGS, XL, 20, 2) 629 /* If PointerMasking should be applied */ 630 FIELD(TB_FLAGS, PM_MASK_ENABLED, 22, 1) 631 FIELD(TB_FLAGS, PM_BASE_ENABLED, 23, 1) 632 FIELD(TB_FLAGS, VTA, 24, 1) 633 FIELD(TB_FLAGS, VMA, 25, 1) 634 /* Native debug itrigger */ 635 FIELD(TB_FLAGS, ITRIGGER, 26, 1) 636 637 #ifdef TARGET_RISCV32 638 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) 639 #else 640 static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) 641 { 642 return env->misa_mxl; 643 } 644 #endif 645 #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env))) 646 647 static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURISCVState *env) 648 { 649 return &env_archcpu(env)->cfg; 650 } 651 652 #if defined(TARGET_RISCV32) 653 #define cpu_recompute_xl(env) ((void)(env), MXL_RV32) 654 #else 655 static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) 656 { 657 RISCVMXL xl = env->misa_mxl; 658 #if !defined(CONFIG_USER_ONLY) 659 /* 660 * When emulating a 32-bit-only cpu, use RV32. 661 * When emulating a 64-bit cpu, and MXL has been reduced to RV32, 662 * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened 663 * back to RV64 for lower privs. 664 */ 665 if (xl != MXL_RV32) { 666 switch (env->priv) { 667 case PRV_M: 668 break; 669 case PRV_U: 670 xl = get_field(env->mstatus, MSTATUS64_UXL); 671 break; 672 default: /* PRV_S | PRV_H */ 673 xl = get_field(env->mstatus, MSTATUS64_SXL); 674 break; 675 } 676 } 677 #endif 678 return xl; 679 } 680 #endif 681 682 static inline int riscv_cpu_xlen(CPURISCVState *env) 683 { 684 return 16 << env->xl; 685 } 686 687 #ifdef TARGET_RISCV32 688 #define riscv_cpu_sxl(env) ((void)(env), MXL_RV32) 689 #else 690 static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env) 691 { 692 #ifdef CONFIG_USER_ONLY 693 return env->misa_mxl; 694 #else 695 return get_field(env->mstatus, MSTATUS64_SXL); 696 #endif 697 } 698 #endif 699 700 /* 701 * Encode LMUL to lmul as follows: 702 * LMUL vlmul lmul 703 * 1 000 0 704 * 2 001 1 705 * 4 010 2 706 * 8 011 3 707 * - 100 - 708 * 1/8 101 -3 709 * 1/4 110 -2 710 * 1/2 111 -1 711 * 712 * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul) 713 * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8 714 * => VLMAX = vlen >> (1 + 3 - (-3)) 715 * = 256 >> 7 716 * = 2 717 */ 718 static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) 719 { 720 uint8_t sew = FIELD_EX64(vtype, VTYPE, VSEW); 721 int8_t lmul = sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3); 722 return cpu->cfg.vlen >> (sew + 3 - lmul); 723 } 724 725 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 726 target_ulong *cs_base, uint32_t *pflags); 727 728 void riscv_cpu_update_mask(CPURISCVState *env); 729 730 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, 731 target_ulong *ret_value, 732 target_ulong new_value, target_ulong write_mask); 733 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, 734 target_ulong *ret_value, 735 target_ulong new_value, 736 target_ulong write_mask); 737 738 static inline void riscv_csr_write(CPURISCVState *env, int csrno, 739 target_ulong val) 740 { 741 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); 742 } 743 744 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) 745 { 746 target_ulong val = 0; 747 riscv_csrrw(env, csrno, &val, 0, 0); 748 return val; 749 } 750 751 typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, 752 int csrno); 753 typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, 754 target_ulong *ret_value); 755 typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, 756 target_ulong new_value); 757 typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, 758 target_ulong *ret_value, 759 target_ulong new_value, 760 target_ulong write_mask); 761 762 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, 763 Int128 *ret_value, 764 Int128 new_value, Int128 write_mask); 765 766 typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno, 767 Int128 *ret_value); 768 typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int csrno, 769 Int128 new_value); 770 771 typedef struct { 772 const char *name; 773 riscv_csr_predicate_fn predicate; 774 riscv_csr_read_fn read; 775 riscv_csr_write_fn write; 776 riscv_csr_op_fn op; 777 riscv_csr_read128_fn read128; 778 riscv_csr_write128_fn write128; 779 /* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0) */ 780 uint32_t min_priv_ver; 781 } riscv_csr_operations; 782 783 /* CSR function table constants */ 784 enum { 785 CSR_TABLE_SIZE = 0x1000 786 }; 787 788 /** 789 * The event id are encoded based on the encoding specified in the 790 * SBI specification v0.3 791 */ 792 793 enum riscv_pmu_event_idx { 794 RISCV_PMU_EVENT_HW_CPU_CYCLES = 0x01, 795 RISCV_PMU_EVENT_HW_INSTRUCTIONS = 0x02, 796 RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS = 0x10019, 797 RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS = 0x1001B, 798 RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS = 0x10021, 799 }; 800 801 /* CSR function table */ 802 extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; 803 804 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); 805 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); 806 807 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); 808 809 #endif /* RISCV_CPU_H */ 810