1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef RISCV_CPU_H 21 #define RISCV_CPU_H 22 23 #include "hw/core/cpu.h" 24 #include "hw/registerfields.h" 25 #include "exec/cpu-defs.h" 26 #include "fpu/softfloat-types.h" 27 #include "qom/object.h" 28 29 #define TCG_GUEST_DEFAULT_MO 0 30 31 #define TYPE_RISCV_CPU "riscv-cpu" 32 33 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU 34 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) 35 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU 36 37 #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") 38 #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") 39 #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") 40 #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") 41 #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") 42 #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") 43 #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") 44 #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") 45 #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") 46 #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") 47 48 #if defined(TARGET_RISCV32) 49 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 50 #elif defined(TARGET_RISCV64) 51 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 52 #endif 53 54 #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2)) 55 #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2)) 56 57 #define RV(x) ((target_ulong)1 << (x - 'A')) 58 59 #define RVI RV('I') 60 #define RVE RV('E') /* E and I are mutually exclusive */ 61 #define RVM RV('M') 62 #define RVA RV('A') 63 #define RVF RV('F') 64 #define RVD RV('D') 65 #define RVV RV('V') 66 #define RVC RV('C') 67 #define RVS RV('S') 68 #define RVU RV('U') 69 #define RVH RV('H') 70 #define RVB RV('B') 71 72 /* S extension denotes that Supervisor mode exists, however it is possible 73 to have a core that support S mode but does not have an MMU and there 74 is currently no bit in misa to indicate whether an MMU exists or not 75 so a cpu features bitfield is required, likewise for optional PMP support */ 76 enum { 77 RISCV_FEATURE_MMU, 78 RISCV_FEATURE_PMP, 79 RISCV_FEATURE_EPMP, 80 RISCV_FEATURE_MISA 81 }; 82 83 #define PRIV_VERSION_1_10_0 0x00011000 84 #define PRIV_VERSION_1_11_0 0x00011100 85 86 #define VEXT_VERSION_0_07_1 0x00000701 87 88 enum { 89 TRANSLATE_SUCCESS, 90 TRANSLATE_FAIL, 91 TRANSLATE_PMP_FAIL, 92 TRANSLATE_G_STAGE_FAIL 93 }; 94 95 #define MMU_USER_IDX 3 96 97 #define MAX_RISCV_PMPS (16) 98 99 typedef struct CPURISCVState CPURISCVState; 100 101 #if !defined(CONFIG_USER_ONLY) 102 #include "pmp.h" 103 #endif 104 105 #define RV_VLEN_MAX 256 106 107 FIELD(VTYPE, VLMUL, 0, 2) 108 FIELD(VTYPE, VSEW, 2, 3) 109 FIELD(VTYPE, VEDIV, 5, 2) 110 FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 9) 111 FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1) 112 113 struct CPURISCVState { 114 target_ulong gpr[32]; 115 uint64_t fpr[32]; /* assume both F and D extensions */ 116 117 /* vector coprocessor state. */ 118 uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); 119 target_ulong vxrm; 120 target_ulong vxsat; 121 target_ulong vl; 122 target_ulong vstart; 123 target_ulong vtype; 124 125 target_ulong pc; 126 target_ulong load_res; 127 target_ulong load_val; 128 129 target_ulong frm; 130 131 target_ulong badaddr; 132 target_ulong guest_phys_fault_addr; 133 134 target_ulong priv_ver; 135 target_ulong vext_ver; 136 target_ulong misa; 137 target_ulong misa_mask; 138 139 uint32_t features; 140 141 #ifdef CONFIG_USER_ONLY 142 uint32_t elf_flags; 143 #endif 144 145 #ifndef CONFIG_USER_ONLY 146 target_ulong priv; 147 /* This contains QEMU specific information about the virt state. */ 148 target_ulong virt; 149 target_ulong resetvec; 150 151 target_ulong mhartid; 152 /* 153 * For RV32 this is 32-bit mstatus and 32-bit mstatush. 154 * For RV64 this is a 64-bit mstatus. 155 */ 156 uint64_t mstatus; 157 158 target_ulong mip; 159 160 uint32_t miclaim; 161 162 target_ulong mie; 163 target_ulong mideleg; 164 165 target_ulong satp; /* since: priv-1.10.0 */ 166 target_ulong stval; 167 target_ulong medeleg; 168 169 target_ulong stvec; 170 target_ulong sepc; 171 target_ulong scause; 172 173 target_ulong mtvec; 174 target_ulong mepc; 175 target_ulong mcause; 176 target_ulong mtval; /* since: priv-1.10.0 */ 177 178 /* Hypervisor CSRs */ 179 target_ulong hstatus; 180 target_ulong hedeleg; 181 target_ulong hideleg; 182 target_ulong hcounteren; 183 target_ulong htval; 184 target_ulong htinst; 185 target_ulong hgatp; 186 uint64_t htimedelta; 187 188 /* Virtual CSRs */ 189 /* 190 * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. 191 * For RV64 this is a 64-bit vsstatus. 192 */ 193 uint64_t vsstatus; 194 target_ulong vstvec; 195 target_ulong vsscratch; 196 target_ulong vsepc; 197 target_ulong vscause; 198 target_ulong vstval; 199 target_ulong vsatp; 200 201 target_ulong mtval2; 202 target_ulong mtinst; 203 204 /* HS Backup CSRs */ 205 target_ulong stvec_hs; 206 target_ulong sscratch_hs; 207 target_ulong sepc_hs; 208 target_ulong scause_hs; 209 target_ulong stval_hs; 210 target_ulong satp_hs; 211 uint64_t mstatus_hs; 212 213 /* Signals whether the current exception occurred with two-stage address 214 translation active. */ 215 bool two_stage_lookup; 216 217 target_ulong scounteren; 218 target_ulong mcounteren; 219 220 target_ulong sscratch; 221 target_ulong mscratch; 222 223 /* temporary htif regs */ 224 uint64_t mfromhost; 225 uint64_t mtohost; 226 uint64_t timecmp; 227 228 /* physical memory protection */ 229 pmp_table_t pmp_state; 230 target_ulong mseccfg; 231 232 /* machine specific rdtime callback */ 233 uint64_t (*rdtime_fn)(uint32_t); 234 uint32_t rdtime_fn_arg; 235 236 /* True if in debugger mode. */ 237 bool debugger; 238 #endif 239 240 float_status fp_status; 241 242 /* Fields from here on are preserved across CPU reset. */ 243 QEMUTimer *timer; /* Internal timer */ 244 }; 245 246 OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass, 247 RISCV_CPU) 248 249 /** 250 * RISCVCPUClass: 251 * @parent_realize: The parent class' realize handler. 252 * @parent_reset: The parent class' reset handler. 253 * 254 * A RISCV CPU model. 255 */ 256 struct RISCVCPUClass { 257 /*< private >*/ 258 CPUClass parent_class; 259 /*< public >*/ 260 DeviceRealize parent_realize; 261 DeviceReset parent_reset; 262 }; 263 264 /** 265 * RISCVCPU: 266 * @env: #CPURISCVState 267 * 268 * A RISCV CPU. 269 */ 270 struct RISCVCPU { 271 /*< private >*/ 272 CPUState parent_obj; 273 /*< public >*/ 274 CPUNegativeOffsetState neg; 275 CPURISCVState env; 276 277 char *dyn_csr_xml; 278 279 /* Configuration Settings */ 280 struct { 281 bool ext_i; 282 bool ext_e; 283 bool ext_g; 284 bool ext_m; 285 bool ext_a; 286 bool ext_f; 287 bool ext_d; 288 bool ext_c; 289 bool ext_b; 290 bool ext_s; 291 bool ext_u; 292 bool ext_h; 293 bool ext_v; 294 bool ext_counters; 295 bool ext_ifencei; 296 bool ext_icsr; 297 298 char *priv_spec; 299 char *user_spec; 300 char *vext_spec; 301 uint16_t vlen; 302 uint16_t elen; 303 bool mmu; 304 bool pmp; 305 bool epmp; 306 uint64_t resetvec; 307 } cfg; 308 }; 309 310 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) 311 { 312 return (env->misa & ext) != 0; 313 } 314 315 static inline bool riscv_feature(CPURISCVState *env, int feature) 316 { 317 return env->features & (1ULL << feature); 318 } 319 320 #include "cpu_user.h" 321 #include "cpu_bits.h" 322 323 extern const char * const riscv_int_regnames[]; 324 extern const char * const riscv_fpr_regnames[]; 325 326 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); 327 void riscv_cpu_do_interrupt(CPUState *cpu); 328 int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 329 int cpuid, void *opaque); 330 int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 331 int cpuid, void *opaque); 332 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 333 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 334 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); 335 bool riscv_cpu_fp_enabled(CPURISCVState *env); 336 bool riscv_cpu_virt_enabled(CPURISCVState *env); 337 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); 338 bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env); 339 void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable); 340 bool riscv_cpu_two_stage_lookup(int mmu_idx); 341 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); 342 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 343 void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 344 MMUAccessType access_type, int mmu_idx, 345 uintptr_t retaddr); 346 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 347 MMUAccessType access_type, int mmu_idx, 348 bool probe, uintptr_t retaddr); 349 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 350 vaddr addr, unsigned size, 351 MMUAccessType access_type, 352 int mmu_idx, MemTxAttrs attrs, 353 MemTxResult response, uintptr_t retaddr); 354 char *riscv_isa_string(RISCVCPU *cpu); 355 void riscv_cpu_list(void); 356 357 #define cpu_signal_handler riscv_cpu_signal_handler 358 #define cpu_list riscv_cpu_list 359 #define cpu_mmu_index riscv_cpu_mmu_index 360 361 #ifndef CONFIG_USER_ONLY 362 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); 363 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts); 364 uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value); 365 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ 366 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t), 367 uint32_t arg); 368 #endif 369 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); 370 371 void riscv_translate_init(void); 372 int riscv_cpu_signal_handler(int host_signum, void *pinfo, void *puc); 373 void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env, 374 uint32_t exception, uintptr_t pc); 375 376 target_ulong riscv_cpu_get_fflags(CPURISCVState *env); 377 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); 378 379 #define TB_FLAGS_MMU_MASK 7 380 #define TB_FLAGS_PRIV_MMU_MASK 3 381 #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2) 382 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS 383 384 typedef CPURISCVState CPUArchState; 385 typedef RISCVCPU ArchCPU; 386 #include "exec/cpu-all.h" 387 388 FIELD(TB_FLAGS, VL_EQ_VLMAX, 2, 1) 389 FIELD(TB_FLAGS, LMUL, 3, 2) 390 FIELD(TB_FLAGS, SEW, 5, 3) 391 FIELD(TB_FLAGS, VILL, 8, 1) 392 /* Is a Hypervisor instruction load/store allowed? */ 393 FIELD(TB_FLAGS, HLSX, 9, 1) 394 395 bool riscv_cpu_is_32bit(CPURISCVState *env); 396 397 /* 398 * A simplification for VLMAX 399 * = (1 << LMUL) * VLEN / (8 * (1 << SEW)) 400 * = (VLEN << LMUL) / (8 << SEW) 401 * = (VLEN << LMUL) >> (SEW + 3) 402 * = VLEN >> (SEW + 3 - LMUL) 403 */ 404 static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) 405 { 406 uint8_t sew, lmul; 407 408 sew = FIELD_EX64(vtype, VTYPE, VSEW); 409 lmul = FIELD_EX64(vtype, VTYPE, VLMUL); 410 return cpu->cfg.vlen >> (sew + 3 - lmul); 411 } 412 413 static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 414 target_ulong *cs_base, uint32_t *pflags) 415 { 416 uint32_t flags = 0; 417 418 *pc = env->pc; 419 *cs_base = 0; 420 421 if (riscv_has_ext(env, RVV)) { 422 uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype); 423 bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl); 424 flags = FIELD_DP32(flags, TB_FLAGS, VILL, 425 FIELD_EX64(env->vtype, VTYPE, VILL)); 426 flags = FIELD_DP32(flags, TB_FLAGS, SEW, 427 FIELD_EX64(env->vtype, VTYPE, VSEW)); 428 flags = FIELD_DP32(flags, TB_FLAGS, LMUL, 429 FIELD_EX64(env->vtype, VTYPE, VLMUL)); 430 flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); 431 } else { 432 flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1); 433 } 434 435 #ifdef CONFIG_USER_ONLY 436 flags |= TB_FLAGS_MSTATUS_FS; 437 #else 438 flags |= cpu_mmu_index(env, 0); 439 if (riscv_cpu_fp_enabled(env)) { 440 flags |= env->mstatus & MSTATUS_FS; 441 } 442 443 if (riscv_has_ext(env, RVH)) { 444 if (env->priv == PRV_M || 445 (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || 446 (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) && 447 get_field(env->hstatus, HSTATUS_HU))) { 448 flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1); 449 } 450 } 451 #endif 452 453 *pflags = flags; 454 } 455 456 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, 457 target_ulong *ret_value, 458 target_ulong new_value, target_ulong write_mask); 459 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, 460 target_ulong *ret_value, 461 target_ulong new_value, 462 target_ulong write_mask); 463 464 static inline void riscv_csr_write(CPURISCVState *env, int csrno, 465 target_ulong val) 466 { 467 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); 468 } 469 470 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) 471 { 472 target_ulong val = 0; 473 riscv_csrrw(env, csrno, &val, 0, 0); 474 return val; 475 } 476 477 typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, 478 int csrno); 479 typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, 480 target_ulong *ret_value); 481 typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, 482 target_ulong new_value); 483 typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, 484 target_ulong *ret_value, 485 target_ulong new_value, 486 target_ulong write_mask); 487 488 typedef struct { 489 const char *name; 490 riscv_csr_predicate_fn predicate; 491 riscv_csr_read_fn read; 492 riscv_csr_write_fn write; 493 riscv_csr_op_fn op; 494 } riscv_csr_operations; 495 496 /* CSR function table constants */ 497 enum { 498 CSR_TABLE_SIZE = 0x1000 499 }; 500 501 /* CSR function table */ 502 extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; 503 504 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); 505 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); 506 507 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); 508 509 #endif /* RISCV_CPU_H */ 510