1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef RISCV_CPU_H 21 #define RISCV_CPU_H 22 23 #include "hw/core/cpu.h" 24 #include "hw/registerfields.h" 25 #include "exec/cpu-defs.h" 26 #include "qemu/cpu-float.h" 27 #include "qom/object.h" 28 #include "qemu/int128.h" 29 #include "cpu_bits.h" 30 #include "cpu_cfg.h" 31 #include "qapi/qapi-types-common.h" 32 #include "cpu-qom.h" 33 34 #define TCG_GUEST_DEFAULT_MO 0 35 36 /* 37 * RISC-V-specific extra insn start words: 38 * 1: Original instruction opcode 39 */ 40 #define TARGET_INSN_START_EXTRA_WORDS 1 41 42 #define RV(x) ((target_ulong)1 << (x - 'A')) 43 44 /* 45 * Consider updating misa_ext_info_arr[] and misa_ext_cfgs[] 46 * when adding new MISA bits here. 47 */ 48 #define RVI RV('I') 49 #define RVE RV('E') /* E and I are mutually exclusive */ 50 #define RVM RV('M') 51 #define RVA RV('A') 52 #define RVF RV('F') 53 #define RVD RV('D') 54 #define RVV RV('V') 55 #define RVC RV('C') 56 #define RVS RV('S') 57 #define RVU RV('U') 58 #define RVH RV('H') 59 #define RVJ RV('J') 60 #define RVG RV('G') 61 62 const char *riscv_get_misa_ext_name(uint32_t bit); 63 const char *riscv_get_misa_ext_description(uint32_t bit); 64 65 #define CPU_CFG_OFFSET(_prop) offsetof(struct RISCVCPUConfig, _prop) 66 67 /* Privileged specification version */ 68 enum { 69 PRIV_VERSION_1_10_0 = 0, 70 PRIV_VERSION_1_11_0, 71 PRIV_VERSION_1_12_0, 72 73 PRIV_VERSION_LATEST = PRIV_VERSION_1_12_0, 74 }; 75 76 #define VEXT_VERSION_1_00_0 0x00010000 77 78 enum { 79 TRANSLATE_SUCCESS, 80 TRANSLATE_FAIL, 81 TRANSLATE_PMP_FAIL, 82 TRANSLATE_G_STAGE_FAIL 83 }; 84 85 /* Extension context status */ 86 typedef enum { 87 EXT_STATUS_DISABLED = 0, 88 EXT_STATUS_INITIAL, 89 EXT_STATUS_CLEAN, 90 EXT_STATUS_DIRTY, 91 } RISCVExtStatus; 92 93 #define MMU_USER_IDX 3 94 95 #define MAX_RISCV_PMPS (16) 96 97 #if !defined(CONFIG_USER_ONLY) 98 #include "pmp.h" 99 #include "debug.h" 100 #endif 101 102 #define RV_VLEN_MAX 1024 103 #define RV_MAX_MHPMEVENTS 32 104 #define RV_MAX_MHPMCOUNTERS 32 105 106 FIELD(VTYPE, VLMUL, 0, 3) 107 FIELD(VTYPE, VSEW, 3, 3) 108 FIELD(VTYPE, VTA, 6, 1) 109 FIELD(VTYPE, VMA, 7, 1) 110 FIELD(VTYPE, VEDIV, 8, 2) 111 FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) 112 113 typedef struct PMUCTRState { 114 /* Current value of a counter */ 115 target_ulong mhpmcounter_val; 116 /* Current value of a counter in RV32 */ 117 target_ulong mhpmcounterh_val; 118 /* Snapshot values of counter */ 119 target_ulong mhpmcounter_prev; 120 /* Snapshort value of a counter in RV32 */ 121 target_ulong mhpmcounterh_prev; 122 bool started; 123 /* Value beyond UINT32_MAX/UINT64_MAX before overflow interrupt trigger */ 124 target_ulong irq_overflow_left; 125 } PMUCTRState; 126 127 struct CPUArchState { 128 target_ulong gpr[32]; 129 target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ 130 131 /* vector coprocessor state. */ 132 uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); 133 target_ulong vxrm; 134 target_ulong vxsat; 135 target_ulong vl; 136 target_ulong vstart; 137 target_ulong vtype; 138 bool vill; 139 140 target_ulong pc; 141 target_ulong load_res; 142 target_ulong load_val; 143 144 /* Floating-Point state */ 145 uint64_t fpr[32]; /* assume both F and D extensions */ 146 target_ulong frm; 147 float_status fp_status; 148 149 target_ulong badaddr; 150 target_ulong bins; 151 152 target_ulong guest_phys_fault_addr; 153 154 target_ulong priv_ver; 155 target_ulong bext_ver; 156 target_ulong vext_ver; 157 158 /* RISCVMXL, but uint32_t for vmstate migration */ 159 uint32_t misa_mxl; /* current mxl */ 160 uint32_t misa_mxl_max; /* max mxl for this cpu */ 161 uint32_t misa_ext; /* current extensions */ 162 uint32_t misa_ext_mask; /* max ext for this cpu */ 163 uint32_t xl; /* current xlen */ 164 165 /* 128-bit helpers upper part return value */ 166 target_ulong retxh; 167 168 target_ulong jvt; 169 170 #ifdef CONFIG_USER_ONLY 171 uint32_t elf_flags; 172 #endif 173 174 #ifndef CONFIG_USER_ONLY 175 target_ulong priv; 176 /* This contains QEMU specific information about the virt state. */ 177 bool virt_enabled; 178 target_ulong geilen; 179 uint64_t resetvec; 180 181 target_ulong mhartid; 182 /* 183 * For RV32 this is 32-bit mstatus and 32-bit mstatush. 184 * For RV64 this is a 64-bit mstatus. 185 */ 186 uint64_t mstatus; 187 188 uint64_t mip; 189 /* 190 * MIP contains the software writable version of SEIP ORed with the 191 * external interrupt value. The MIP register is always up-to-date. 192 * To keep track of the current source, we also save booleans of the values 193 * here. 194 */ 195 bool external_seip; 196 bool software_seip; 197 198 uint64_t miclaim; 199 200 uint64_t mie; 201 uint64_t mideleg; 202 203 target_ulong satp; /* since: priv-1.10.0 */ 204 target_ulong stval; 205 target_ulong medeleg; 206 207 target_ulong stvec; 208 target_ulong sepc; 209 target_ulong scause; 210 211 target_ulong mtvec; 212 target_ulong mepc; 213 target_ulong mcause; 214 target_ulong mtval; /* since: priv-1.10.0 */ 215 216 /* Machine and Supervisor interrupt priorities */ 217 uint8_t miprio[64]; 218 uint8_t siprio[64]; 219 220 /* AIA CSRs */ 221 target_ulong miselect; 222 target_ulong siselect; 223 224 /* Hypervisor CSRs */ 225 target_ulong hstatus; 226 target_ulong hedeleg; 227 uint64_t hideleg; 228 target_ulong hcounteren; 229 target_ulong htval; 230 target_ulong htinst; 231 target_ulong hgatp; 232 target_ulong hgeie; 233 target_ulong hgeip; 234 uint64_t htimedelta; 235 236 /* Hypervisor controlled virtual interrupt priorities */ 237 target_ulong hvictl; 238 uint8_t hviprio[64]; 239 240 /* Upper 64-bits of 128-bit CSRs */ 241 uint64_t mscratchh; 242 uint64_t sscratchh; 243 244 /* Virtual CSRs */ 245 /* 246 * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. 247 * For RV64 this is a 64-bit vsstatus. 248 */ 249 uint64_t vsstatus; 250 target_ulong vstvec; 251 target_ulong vsscratch; 252 target_ulong vsepc; 253 target_ulong vscause; 254 target_ulong vstval; 255 target_ulong vsatp; 256 257 /* AIA VS-mode CSRs */ 258 target_ulong vsiselect; 259 260 target_ulong mtval2; 261 target_ulong mtinst; 262 263 /* HS Backup CSRs */ 264 target_ulong stvec_hs; 265 target_ulong sscratch_hs; 266 target_ulong sepc_hs; 267 target_ulong scause_hs; 268 target_ulong stval_hs; 269 target_ulong satp_hs; 270 uint64_t mstatus_hs; 271 272 /* 273 * Signals whether the current exception occurred with two-stage address 274 * translation active. 275 */ 276 bool two_stage_lookup; 277 /* 278 * Signals whether the current exception occurred while doing two-stage 279 * address translation for the VS-stage page table walk. 280 */ 281 bool two_stage_indirect_lookup; 282 283 target_ulong scounteren; 284 target_ulong mcounteren; 285 286 target_ulong mcountinhibit; 287 288 /* PMU counter state */ 289 PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS]; 290 291 /* PMU event selector configured values. First three are unused */ 292 target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS]; 293 294 /* PMU event selector configured values for RV32 */ 295 target_ulong mhpmeventh_val[RV_MAX_MHPMEVENTS]; 296 297 target_ulong sscratch; 298 target_ulong mscratch; 299 300 /* Sstc CSRs */ 301 uint64_t stimecmp; 302 303 uint64_t vstimecmp; 304 305 /* physical memory protection */ 306 pmp_table_t pmp_state; 307 target_ulong mseccfg; 308 309 /* trigger module */ 310 target_ulong trigger_cur; 311 target_ulong tdata1[RV_MAX_TRIGGERS]; 312 target_ulong tdata2[RV_MAX_TRIGGERS]; 313 target_ulong tdata3[RV_MAX_TRIGGERS]; 314 struct CPUBreakpoint *cpu_breakpoint[RV_MAX_TRIGGERS]; 315 struct CPUWatchpoint *cpu_watchpoint[RV_MAX_TRIGGERS]; 316 QEMUTimer *itrigger_timer[RV_MAX_TRIGGERS]; 317 int64_t last_icount; 318 bool itrigger_enabled; 319 320 /* machine specific rdtime callback */ 321 uint64_t (*rdtime_fn)(void *); 322 void *rdtime_fn_arg; 323 324 /* machine specific AIA ireg read-modify-write callback */ 325 #define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \ 326 ((((__xlen) & 0xff) << 24) | \ 327 (((__vgein) & 0x3f) << 20) | \ 328 (((__virt) & 0x1) << 18) | \ 329 (((__priv) & 0x3) << 16) | \ 330 (__isel & 0xffff)) 331 #define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff) 332 #define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3) 333 #define AIA_IREG_VIRT(__ireg) (((__ireg) >> 18) & 0x1) 334 #define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 20) & 0x3f) 335 #define AIA_IREG_XLEN(__ireg) (((__ireg) >> 24) & 0xff) 336 int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg, 337 target_ulong *val, target_ulong new_val, target_ulong write_mask); 338 void *aia_ireg_rmw_fn_arg[4]; 339 340 /* True if in debugger mode. */ 341 bool debugger; 342 343 /* 344 * CSRs for PointerMasking extension 345 */ 346 target_ulong mmte; 347 target_ulong mpmmask; 348 target_ulong mpmbase; 349 target_ulong spmmask; 350 target_ulong spmbase; 351 target_ulong upmmask; 352 target_ulong upmbase; 353 354 /* CSRs for execution environment configuration */ 355 uint64_t menvcfg; 356 uint64_t mstateen[SMSTATEEN_MAX_COUNT]; 357 uint64_t hstateen[SMSTATEEN_MAX_COUNT]; 358 uint64_t sstateen[SMSTATEEN_MAX_COUNT]; 359 target_ulong senvcfg; 360 uint64_t henvcfg; 361 #endif 362 target_ulong cur_pmmask; 363 target_ulong cur_pmbase; 364 365 /* Fields from here on are preserved across CPU reset. */ 366 QEMUTimer *stimer; /* Internal timer for S-mode interrupt */ 367 QEMUTimer *vstimer; /* Internal timer for VS-mode interrupt */ 368 bool vstime_irq; 369 370 hwaddr kernel_addr; 371 hwaddr fdt_addr; 372 373 #ifdef CONFIG_KVM 374 /* kvm timer */ 375 bool kvm_timer_dirty; 376 uint64_t kvm_timer_time; 377 uint64_t kvm_timer_compare; 378 uint64_t kvm_timer_state; 379 uint64_t kvm_timer_frequency; 380 #endif /* CONFIG_KVM */ 381 }; 382 383 /* 384 * RISCVCPU: 385 * @env: #CPURISCVState 386 * 387 * A RISCV CPU. 388 */ 389 struct ArchCPU { 390 /* < private > */ 391 CPUState parent_obj; 392 /* < public > */ 393 394 CPURISCVState env; 395 396 char *dyn_csr_xml; 397 char *dyn_vreg_xml; 398 399 /* Configuration Settings */ 400 RISCVCPUConfig cfg; 401 402 QEMUTimer *pmu_timer; 403 /* A bitmask of Available programmable counters */ 404 uint32_t pmu_avail_ctrs; 405 /* Mapping of events to counters */ 406 GHashTable *pmu_event_ctr_map; 407 }; 408 409 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) 410 { 411 return (env->misa_ext & ext) != 0; 412 } 413 414 #include "cpu_user.h" 415 416 extern const char * const riscv_int_regnames[]; 417 extern const char * const riscv_int_regnamesh[]; 418 extern const char * const riscv_fpr_regnames[]; 419 420 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); 421 void riscv_cpu_do_interrupt(CPUState *cpu); 422 int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 423 int cpuid, DumpState *s); 424 int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 425 int cpuid, DumpState *s); 426 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 427 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 428 int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero); 429 uint8_t riscv_cpu_default_priority(int irq); 430 uint64_t riscv_cpu_all_pending(CPURISCVState *env); 431 int riscv_cpu_mirq_pending(CPURISCVState *env); 432 int riscv_cpu_sirq_pending(CPURISCVState *env); 433 int riscv_cpu_vsirq_pending(CPURISCVState *env); 434 bool riscv_cpu_fp_enabled(CPURISCVState *env); 435 target_ulong riscv_cpu_get_geilen(CPURISCVState *env); 436 void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); 437 bool riscv_cpu_vector_enabled(CPURISCVState *env); 438 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); 439 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); 440 G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 441 MMUAccessType access_type, 442 int mmu_idx, uintptr_t retaddr); 443 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 444 MMUAccessType access_type, int mmu_idx, 445 bool probe, uintptr_t retaddr); 446 char *riscv_isa_string(RISCVCPU *cpu); 447 void riscv_cpu_list(void); 448 void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp); 449 450 #define cpu_list riscv_cpu_list 451 #define cpu_mmu_index riscv_cpu_mmu_index 452 453 #ifndef CONFIG_USER_ONLY 454 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 455 vaddr addr, unsigned size, 456 MMUAccessType access_type, 457 int mmu_idx, MemTxAttrs attrs, 458 MemTxResult response, uintptr_t retaddr); 459 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 460 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); 461 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); 462 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); 463 uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask, 464 uint64_t value); 465 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ 466 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), 467 void *arg); 468 void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, 469 int (*rmw_fn)(void *arg, 470 target_ulong reg, 471 target_ulong *val, 472 target_ulong new_val, 473 target_ulong write_mask), 474 void *rmw_fn_arg); 475 476 RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit); 477 #endif 478 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); 479 480 void riscv_translate_init(void); 481 G_NORETURN void riscv_raise_exception(CPURISCVState *env, 482 uint32_t exception, uintptr_t pc); 483 484 target_ulong riscv_cpu_get_fflags(CPURISCVState *env); 485 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); 486 487 #include "exec/cpu-all.h" 488 489 FIELD(TB_FLAGS, MEM_IDX, 0, 3) 490 FIELD(TB_FLAGS, FS, 3, 2) 491 /* Vector flags */ 492 FIELD(TB_FLAGS, VS, 5, 2) 493 FIELD(TB_FLAGS, LMUL, 7, 3) 494 FIELD(TB_FLAGS, SEW, 10, 3) 495 FIELD(TB_FLAGS, VL_EQ_VLMAX, 13, 1) 496 FIELD(TB_FLAGS, VILL, 14, 1) 497 FIELD(TB_FLAGS, VSTART_EQ_ZERO, 15, 1) 498 /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ 499 FIELD(TB_FLAGS, XL, 16, 2) 500 /* If PointerMasking should be applied */ 501 FIELD(TB_FLAGS, PM_MASK_ENABLED, 18, 1) 502 FIELD(TB_FLAGS, PM_BASE_ENABLED, 19, 1) 503 FIELD(TB_FLAGS, VTA, 20, 1) 504 FIELD(TB_FLAGS, VMA, 21, 1) 505 /* Native debug itrigger */ 506 FIELD(TB_FLAGS, ITRIGGER, 22, 1) 507 /* Virtual mode enabled */ 508 FIELD(TB_FLAGS, VIRT_ENABLED, 23, 1) 509 FIELD(TB_FLAGS, PRIV, 24, 2) 510 FIELD(TB_FLAGS, AXL, 26, 2) 511 512 #ifdef TARGET_RISCV32 513 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) 514 #else 515 static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) 516 { 517 return env->misa_mxl; 518 } 519 #endif 520 #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env))) 521 522 static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURISCVState *env) 523 { 524 return &env_archcpu(env)->cfg; 525 } 526 527 #if !defined(CONFIG_USER_ONLY) 528 static inline int cpu_address_mode(CPURISCVState *env) 529 { 530 int mode = env->priv; 531 532 if (mode == PRV_M && get_field(env->mstatus, MSTATUS_MPRV)) { 533 mode = get_field(env->mstatus, MSTATUS_MPP); 534 } 535 return mode; 536 } 537 538 static inline RISCVMXL cpu_get_xl(CPURISCVState *env, target_ulong mode) 539 { 540 RISCVMXL xl = env->misa_mxl; 541 /* 542 * When emulating a 32-bit-only cpu, use RV32. 543 * When emulating a 64-bit cpu, and MXL has been reduced to RV32, 544 * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened 545 * back to RV64 for lower privs. 546 */ 547 if (xl != MXL_RV32) { 548 switch (mode) { 549 case PRV_M: 550 break; 551 case PRV_U: 552 xl = get_field(env->mstatus, MSTATUS64_UXL); 553 break; 554 default: /* PRV_S */ 555 xl = get_field(env->mstatus, MSTATUS64_SXL); 556 break; 557 } 558 } 559 return xl; 560 } 561 #endif 562 563 #if defined(TARGET_RISCV32) 564 #define cpu_recompute_xl(env) ((void)(env), MXL_RV32) 565 #else 566 static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) 567 { 568 #if !defined(CONFIG_USER_ONLY) 569 return cpu_get_xl(env, env->priv); 570 #else 571 return env->misa_mxl; 572 #endif 573 } 574 #endif 575 576 #if defined(TARGET_RISCV32) 577 #define cpu_address_xl(env) ((void)(env), MXL_RV32) 578 #else 579 static inline RISCVMXL cpu_address_xl(CPURISCVState *env) 580 { 581 #ifdef CONFIG_USER_ONLY 582 return env->xl; 583 #else 584 int mode = cpu_address_mode(env); 585 586 return cpu_get_xl(env, mode); 587 #endif 588 } 589 #endif 590 591 static inline int riscv_cpu_xlen(CPURISCVState *env) 592 { 593 return 16 << env->xl; 594 } 595 596 #ifdef TARGET_RISCV32 597 #define riscv_cpu_sxl(env) ((void)(env), MXL_RV32) 598 #else 599 static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env) 600 { 601 #ifdef CONFIG_USER_ONLY 602 return env->misa_mxl; 603 #else 604 return get_field(env->mstatus, MSTATUS64_SXL); 605 #endif 606 } 607 #endif 608 609 /* 610 * Encode LMUL to lmul as follows: 611 * LMUL vlmul lmul 612 * 1 000 0 613 * 2 001 1 614 * 4 010 2 615 * 8 011 3 616 * - 100 - 617 * 1/8 101 -3 618 * 1/4 110 -2 619 * 1/2 111 -1 620 * 621 * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul) 622 * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8 623 * => VLMAX = vlen >> (1 + 3 - (-3)) 624 * = 256 >> 7 625 * = 2 626 */ 627 static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) 628 { 629 uint8_t sew = FIELD_EX64(vtype, VTYPE, VSEW); 630 int8_t lmul = sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3); 631 return cpu->cfg.vlen >> (sew + 3 - lmul); 632 } 633 634 void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, 635 uint64_t *cs_base, uint32_t *pflags); 636 637 void riscv_cpu_update_mask(CPURISCVState *env); 638 639 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, 640 target_ulong *ret_value, 641 target_ulong new_value, target_ulong write_mask); 642 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, 643 target_ulong *ret_value, 644 target_ulong new_value, 645 target_ulong write_mask); 646 647 static inline void riscv_csr_write(CPURISCVState *env, int csrno, 648 target_ulong val) 649 { 650 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); 651 } 652 653 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) 654 { 655 target_ulong val = 0; 656 riscv_csrrw(env, csrno, &val, 0, 0); 657 return val; 658 } 659 660 typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, 661 int csrno); 662 typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, 663 target_ulong *ret_value); 664 typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, 665 target_ulong new_value); 666 typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, 667 target_ulong *ret_value, 668 target_ulong new_value, 669 target_ulong write_mask); 670 671 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, 672 Int128 *ret_value, 673 Int128 new_value, Int128 write_mask); 674 675 typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno, 676 Int128 *ret_value); 677 typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int csrno, 678 Int128 new_value); 679 680 typedef struct { 681 const char *name; 682 riscv_csr_predicate_fn predicate; 683 riscv_csr_read_fn read; 684 riscv_csr_write_fn write; 685 riscv_csr_op_fn op; 686 riscv_csr_read128_fn read128; 687 riscv_csr_write128_fn write128; 688 /* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0) */ 689 uint32_t min_priv_ver; 690 } riscv_csr_operations; 691 692 /* CSR function table constants */ 693 enum { 694 CSR_TABLE_SIZE = 0x1000 695 }; 696 697 /* 698 * The event id are encoded based on the encoding specified in the 699 * SBI specification v0.3 700 */ 701 702 enum riscv_pmu_event_idx { 703 RISCV_PMU_EVENT_HW_CPU_CYCLES = 0x01, 704 RISCV_PMU_EVENT_HW_INSTRUCTIONS = 0x02, 705 RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS = 0x10019, 706 RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS = 0x1001B, 707 RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS = 0x10021, 708 }; 709 710 /* CSR function table */ 711 extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; 712 713 extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[]; 714 715 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); 716 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); 717 718 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); 719 720 uint8_t satp_mode_max_from_map(uint32_t map); 721 const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); 722 723 #endif /* RISCV_CPU_H */ 724