1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef RISCV_CPU_H 21 #define RISCV_CPU_H 22 23 #include "hw/core/cpu.h" 24 #include "hw/registerfields.h" 25 #include "hw/qdev-properties.h" 26 #include "exec/cpu-defs.h" 27 #include "exec/gdbstub.h" 28 #include "qemu/cpu-float.h" 29 #include "qom/object.h" 30 #include "qemu/int128.h" 31 #include "cpu_bits.h" 32 #include "cpu_cfg.h" 33 #include "qapi/qapi-types-common.h" 34 #include "cpu-qom.h" 35 36 typedef struct CPUArchState CPURISCVState; 37 38 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU 39 40 #if defined(TARGET_RISCV32) 41 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 42 #elif defined(TARGET_RISCV64) 43 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 44 #endif 45 46 /* 47 * RISC-V-specific extra insn start words: 48 * 1: Original instruction opcode 49 */ 50 #define TARGET_INSN_START_EXTRA_WORDS 1 51 52 #define RV(x) ((target_ulong)1 << (x - 'A')) 53 54 /* 55 * Update misa_bits[], misa_ext_info_arr[] and misa_ext_cfgs[] 56 * when adding new MISA bits here. 57 */ 58 #define RVI RV('I') 59 #define RVE RV('E') /* E and I are mutually exclusive */ 60 #define RVM RV('M') 61 #define RVA RV('A') 62 #define RVF RV('F') 63 #define RVD RV('D') 64 #define RVV RV('V') 65 #define RVC RV('C') 66 #define RVS RV('S') 67 #define RVU RV('U') 68 #define RVH RV('H') 69 #define RVJ RV('J') 70 #define RVG RV('G') 71 #define RVB RV('B') 72 73 extern const uint32_t misa_bits[]; 74 const char *riscv_get_misa_ext_name(uint32_t bit); 75 const char *riscv_get_misa_ext_description(uint32_t bit); 76 77 #define CPU_CFG_OFFSET(_prop) offsetof(struct RISCVCPUConfig, _prop) 78 79 typedef struct riscv_cpu_profile { 80 struct riscv_cpu_profile *parent; 81 const char *name; 82 uint32_t misa_ext; 83 bool enabled; 84 bool user_set; 85 int priv_spec; 86 int satp_mode; 87 const int32_t ext_offsets[]; 88 } RISCVCPUProfile; 89 90 #define RISCV_PROFILE_EXT_LIST_END -1 91 #define RISCV_PROFILE_ATTR_UNUSED -1 92 93 extern RISCVCPUProfile *riscv_profiles[]; 94 95 /* Privileged specification version */ 96 #define PRIV_VER_1_10_0_STR "v1.10.0" 97 #define PRIV_VER_1_11_0_STR "v1.11.0" 98 #define PRIV_VER_1_12_0_STR "v1.12.0" 99 #define PRIV_VER_1_13_0_STR "v1.13.0" 100 enum { 101 PRIV_VERSION_1_10_0 = 0, 102 PRIV_VERSION_1_11_0, 103 PRIV_VERSION_1_12_0, 104 PRIV_VERSION_1_13_0, 105 106 PRIV_VERSION_LATEST = PRIV_VERSION_1_13_0, 107 }; 108 109 #define VEXT_VERSION_1_00_0 0x00010000 110 #define VEXT_VER_1_00_0_STR "v1.0" 111 112 enum { 113 TRANSLATE_SUCCESS, 114 TRANSLATE_FAIL, 115 TRANSLATE_PMP_FAIL, 116 TRANSLATE_G_STAGE_FAIL 117 }; 118 119 /* Extension context status */ 120 typedef enum { 121 EXT_STATUS_DISABLED = 0, 122 EXT_STATUS_INITIAL, 123 EXT_STATUS_CLEAN, 124 EXT_STATUS_DIRTY, 125 } RISCVExtStatus; 126 127 typedef struct riscv_cpu_implied_exts_rule { 128 #ifndef CONFIG_USER_ONLY 129 /* 130 * Bitmask indicates the rule enabled status for the harts. 131 * This enhancement is only available in system-mode QEMU, 132 * as we don't have a good way (e.g. mhartid) to distinguish 133 * the SMP cores in user-mode QEMU. 134 */ 135 unsigned long *enabled; 136 #endif 137 /* True if this is a MISA implied rule. */ 138 bool is_misa; 139 /* ext is MISA bit if is_misa flag is true, else multi extension offset. */ 140 const uint32_t ext; 141 const uint32_t implied_misa_exts; 142 const uint32_t implied_multi_exts[]; 143 } RISCVCPUImpliedExtsRule; 144 145 extern RISCVCPUImpliedExtsRule *riscv_misa_ext_implied_rules[]; 146 extern RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[]; 147 148 #define RISCV_IMPLIED_EXTS_RULE_END -1 149 150 #define MMU_USER_IDX 3 151 152 #define MAX_RISCV_PMPS (16) 153 154 #if !defined(CONFIG_USER_ONLY) 155 #include "pmp.h" 156 #include "debug.h" 157 #endif 158 159 #define RV_VLEN_MAX 1024 160 #define RV_MAX_MHPMEVENTS 32 161 #define RV_MAX_MHPMCOUNTERS 32 162 163 FIELD(VTYPE, VLMUL, 0, 3) 164 FIELD(VTYPE, VSEW, 3, 3) 165 FIELD(VTYPE, VTA, 6, 1) 166 FIELD(VTYPE, VMA, 7, 1) 167 FIELD(VTYPE, VEDIV, 8, 2) 168 FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) 169 170 typedef struct PMUCTRState { 171 /* Current value of a counter */ 172 target_ulong mhpmcounter_val; 173 /* Current value of a counter in RV32 */ 174 target_ulong mhpmcounterh_val; 175 /* Snapshot values of counter */ 176 target_ulong mhpmcounter_prev; 177 /* Snapshort value of a counter in RV32 */ 178 target_ulong mhpmcounterh_prev; 179 bool started; 180 /* Value beyond UINT32_MAX/UINT64_MAX before overflow interrupt trigger */ 181 target_ulong irq_overflow_left; 182 } PMUCTRState; 183 184 struct CPUArchState { 185 target_ulong gpr[32]; 186 target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ 187 188 /* vector coprocessor state. */ 189 uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); 190 target_ulong vxrm; 191 target_ulong vxsat; 192 target_ulong vl; 193 target_ulong vstart; 194 target_ulong vtype; 195 bool vill; 196 197 target_ulong pc; 198 target_ulong load_res; 199 target_ulong load_val; 200 201 /* Floating-Point state */ 202 uint64_t fpr[32]; /* assume both F and D extensions */ 203 target_ulong frm; 204 float_status fp_status; 205 206 target_ulong badaddr; 207 target_ulong bins; 208 209 target_ulong guest_phys_fault_addr; 210 211 target_ulong priv_ver; 212 target_ulong vext_ver; 213 214 /* RISCVMXL, but uint32_t for vmstate migration */ 215 uint32_t misa_mxl; /* current mxl */ 216 uint32_t misa_ext; /* current extensions */ 217 uint32_t misa_ext_mask; /* max ext for this cpu */ 218 uint32_t xl; /* current xlen */ 219 220 /* 128-bit helpers upper part return value */ 221 target_ulong retxh; 222 223 target_ulong jvt; 224 225 #ifdef CONFIG_USER_ONLY 226 uint32_t elf_flags; 227 #endif 228 229 #ifndef CONFIG_USER_ONLY 230 target_ulong priv; 231 /* This contains QEMU specific information about the virt state. */ 232 bool virt_enabled; 233 target_ulong geilen; 234 uint64_t resetvec; 235 236 target_ulong mhartid; 237 /* 238 * For RV32 this is 32-bit mstatus and 32-bit mstatush. 239 * For RV64 this is a 64-bit mstatus. 240 */ 241 uint64_t mstatus; 242 243 uint64_t mip; 244 /* 245 * MIP contains the software writable version of SEIP ORed with the 246 * external interrupt value. The MIP register is always up-to-date. 247 * To keep track of the current source, we also save booleans of the values 248 * here. 249 */ 250 bool external_seip; 251 bool software_seip; 252 253 uint64_t miclaim; 254 255 uint64_t mie; 256 uint64_t mideleg; 257 258 /* 259 * When mideleg[i]=0 and mvien[i]=1, sie[i] is no more 260 * alias of mie[i] and needs to be maintained separately. 261 */ 262 uint64_t sie; 263 264 /* 265 * When hideleg[i]=0 and hvien[i]=1, vsie[i] is no more 266 * alias of sie[i] (mie[i]) and needs to be maintained separately. 267 */ 268 uint64_t vsie; 269 270 target_ulong satp; /* since: priv-1.10.0 */ 271 target_ulong stval; 272 target_ulong medeleg; 273 274 target_ulong stvec; 275 target_ulong sepc; 276 target_ulong scause; 277 278 target_ulong mtvec; 279 target_ulong mepc; 280 target_ulong mcause; 281 target_ulong mtval; /* since: priv-1.10.0 */ 282 283 /* Machine and Supervisor interrupt priorities */ 284 uint8_t miprio[64]; 285 uint8_t siprio[64]; 286 287 /* AIA CSRs */ 288 target_ulong miselect; 289 target_ulong siselect; 290 uint64_t mvien; 291 uint64_t mvip; 292 293 /* Hypervisor CSRs */ 294 target_ulong hstatus; 295 target_ulong hedeleg; 296 uint64_t hideleg; 297 uint32_t hcounteren; 298 target_ulong htval; 299 target_ulong htinst; 300 target_ulong hgatp; 301 target_ulong hgeie; 302 target_ulong hgeip; 303 uint64_t htimedelta; 304 uint64_t hvien; 305 306 /* 307 * Bits VSSIP, VSTIP and VSEIP in hvip are maintained in mip. Other bits 308 * from 0:12 are reserved. Bits 13:63 are not aliased and must be separately 309 * maintain in hvip. 310 */ 311 uint64_t hvip; 312 313 /* Hypervisor controlled virtual interrupt priorities */ 314 target_ulong hvictl; 315 uint8_t hviprio[64]; 316 317 /* Upper 64-bits of 128-bit CSRs */ 318 uint64_t mscratchh; 319 uint64_t sscratchh; 320 321 /* Virtual CSRs */ 322 /* 323 * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. 324 * For RV64 this is a 64-bit vsstatus. 325 */ 326 uint64_t vsstatus; 327 target_ulong vstvec; 328 target_ulong vsscratch; 329 target_ulong vsepc; 330 target_ulong vscause; 331 target_ulong vstval; 332 target_ulong vsatp; 333 334 /* AIA VS-mode CSRs */ 335 target_ulong vsiselect; 336 337 target_ulong mtval2; 338 target_ulong mtinst; 339 340 /* HS Backup CSRs */ 341 target_ulong stvec_hs; 342 target_ulong sscratch_hs; 343 target_ulong sepc_hs; 344 target_ulong scause_hs; 345 target_ulong stval_hs; 346 target_ulong satp_hs; 347 uint64_t mstatus_hs; 348 349 /* 350 * Signals whether the current exception occurred with two-stage address 351 * translation active. 352 */ 353 bool two_stage_lookup; 354 /* 355 * Signals whether the current exception occurred while doing two-stage 356 * address translation for the VS-stage page table walk. 357 */ 358 bool two_stage_indirect_lookup; 359 360 uint32_t scounteren; 361 uint32_t mcounteren; 362 363 uint32_t mcountinhibit; 364 365 /* PMU counter state */ 366 PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS]; 367 368 /* PMU event selector configured values. First three are unused */ 369 target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS]; 370 371 /* PMU event selector configured values for RV32 */ 372 target_ulong mhpmeventh_val[RV_MAX_MHPMEVENTS]; 373 374 target_ulong sscratch; 375 target_ulong mscratch; 376 377 /* Sstc CSRs */ 378 uint64_t stimecmp; 379 380 uint64_t vstimecmp; 381 382 /* physical memory protection */ 383 pmp_table_t pmp_state; 384 target_ulong mseccfg; 385 386 /* trigger module */ 387 target_ulong trigger_cur; 388 target_ulong tdata1[RV_MAX_TRIGGERS]; 389 target_ulong tdata2[RV_MAX_TRIGGERS]; 390 target_ulong tdata3[RV_MAX_TRIGGERS]; 391 target_ulong mcontext; 392 struct CPUBreakpoint *cpu_breakpoint[RV_MAX_TRIGGERS]; 393 struct CPUWatchpoint *cpu_watchpoint[RV_MAX_TRIGGERS]; 394 QEMUTimer *itrigger_timer[RV_MAX_TRIGGERS]; 395 int64_t last_icount; 396 bool itrigger_enabled; 397 398 /* machine specific rdtime callback */ 399 uint64_t (*rdtime_fn)(void *); 400 void *rdtime_fn_arg; 401 402 /* machine specific AIA ireg read-modify-write callback */ 403 #define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \ 404 ((((__xlen) & 0xff) << 24) | \ 405 (((__vgein) & 0x3f) << 20) | \ 406 (((__virt) & 0x1) << 18) | \ 407 (((__priv) & 0x3) << 16) | \ 408 (__isel & 0xffff)) 409 #define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff) 410 #define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3) 411 #define AIA_IREG_VIRT(__ireg) (((__ireg) >> 18) & 0x1) 412 #define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 20) & 0x3f) 413 #define AIA_IREG_XLEN(__ireg) (((__ireg) >> 24) & 0xff) 414 int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg, 415 target_ulong *val, target_ulong new_val, target_ulong write_mask); 416 void *aia_ireg_rmw_fn_arg[4]; 417 418 /* True if in debugger mode. */ 419 bool debugger; 420 421 /* 422 * CSRs for PointerMasking extension 423 */ 424 target_ulong mmte; 425 target_ulong mpmmask; 426 target_ulong mpmbase; 427 target_ulong spmmask; 428 target_ulong spmbase; 429 target_ulong upmmask; 430 target_ulong upmbase; 431 432 /* CSRs for execution environment configuration */ 433 uint64_t menvcfg; 434 uint64_t mstateen[SMSTATEEN_MAX_COUNT]; 435 uint64_t hstateen[SMSTATEEN_MAX_COUNT]; 436 uint64_t sstateen[SMSTATEEN_MAX_COUNT]; 437 target_ulong senvcfg; 438 uint64_t henvcfg; 439 #endif 440 target_ulong cur_pmmask; 441 target_ulong cur_pmbase; 442 443 /* Fields from here on are preserved across CPU reset. */ 444 QEMUTimer *stimer; /* Internal timer for S-mode interrupt */ 445 QEMUTimer *vstimer; /* Internal timer for VS-mode interrupt */ 446 bool vstime_irq; 447 448 hwaddr kernel_addr; 449 hwaddr fdt_addr; 450 451 #ifdef CONFIG_KVM 452 /* kvm timer */ 453 bool kvm_timer_dirty; 454 uint64_t kvm_timer_time; 455 uint64_t kvm_timer_compare; 456 uint64_t kvm_timer_state; 457 uint64_t kvm_timer_frequency; 458 #endif /* CONFIG_KVM */ 459 }; 460 461 /* 462 * RISCVCPU: 463 * @env: #CPURISCVState 464 * 465 * A RISCV CPU. 466 */ 467 struct ArchCPU { 468 CPUState parent_obj; 469 470 CPURISCVState env; 471 472 GDBFeature dyn_csr_feature; 473 GDBFeature dyn_vreg_feature; 474 475 /* Configuration Settings */ 476 RISCVCPUConfig cfg; 477 478 QEMUTimer *pmu_timer; 479 /* A bitmask of Available programmable counters */ 480 uint32_t pmu_avail_ctrs; 481 /* Mapping of events to counters */ 482 GHashTable *pmu_event_ctr_map; 483 const GPtrArray *decoders; 484 }; 485 486 /** 487 * RISCVCPUClass: 488 * @parent_realize: The parent class' realize handler. 489 * @parent_phases: The parent class' reset phase handlers. 490 * 491 * A RISCV CPU model. 492 */ 493 struct RISCVCPUClass { 494 CPUClass parent_class; 495 496 DeviceRealize parent_realize; 497 ResettablePhases parent_phases; 498 uint32_t misa_mxl_max; /* max mxl for this cpu */ 499 }; 500 501 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) 502 { 503 return (env->misa_ext & ext) != 0; 504 } 505 506 #include "cpu_user.h" 507 508 extern const char * const riscv_int_regnames[]; 509 extern const char * const riscv_int_regnamesh[]; 510 extern const char * const riscv_fpr_regnames[]; 511 512 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); 513 int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 514 int cpuid, DumpState *s); 515 int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 516 int cpuid, DumpState *s); 517 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 518 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 519 int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero); 520 uint8_t riscv_cpu_default_priority(int irq); 521 uint64_t riscv_cpu_all_pending(CPURISCVState *env); 522 int riscv_cpu_mirq_pending(CPURISCVState *env); 523 int riscv_cpu_sirq_pending(CPURISCVState *env); 524 int riscv_cpu_vsirq_pending(CPURISCVState *env); 525 bool riscv_cpu_fp_enabled(CPURISCVState *env); 526 target_ulong riscv_cpu_get_geilen(CPURISCVState *env); 527 void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); 528 bool riscv_cpu_vector_enabled(CPURISCVState *env); 529 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); 530 int riscv_env_mmu_index(CPURISCVState *env, bool ifetch); 531 G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 532 MMUAccessType access_type, 533 int mmu_idx, uintptr_t retaddr); 534 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 535 MMUAccessType access_type, int mmu_idx, 536 bool probe, uintptr_t retaddr); 537 char *riscv_isa_string(RISCVCPU *cpu); 538 int riscv_cpu_max_xlen(RISCVCPUClass *mcc); 539 bool riscv_cpu_option_set(const char *optname); 540 541 #ifndef CONFIG_USER_ONLY 542 void riscv_cpu_do_interrupt(CPUState *cpu); 543 void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename); 544 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 545 vaddr addr, unsigned size, 546 MMUAccessType access_type, 547 int mmu_idx, MemTxAttrs attrs, 548 MemTxResult response, uintptr_t retaddr); 549 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 550 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); 551 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); 552 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); 553 uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask, 554 uint64_t value); 555 void riscv_cpu_interrupt(CPURISCVState *env); 556 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ 557 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), 558 void *arg); 559 void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, 560 int (*rmw_fn)(void *arg, 561 target_ulong reg, 562 target_ulong *val, 563 target_ulong new_val, 564 target_ulong write_mask), 565 void *rmw_fn_arg); 566 567 RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit); 568 #endif /* !CONFIG_USER_ONLY */ 569 570 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); 571 572 void riscv_translate_init(void); 573 G_NORETURN void riscv_raise_exception(CPURISCVState *env, 574 uint32_t exception, uintptr_t pc); 575 576 target_ulong riscv_cpu_get_fflags(CPURISCVState *env); 577 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); 578 579 #include "exec/cpu-all.h" 580 581 FIELD(TB_FLAGS, MEM_IDX, 0, 3) 582 FIELD(TB_FLAGS, FS, 3, 2) 583 /* Vector flags */ 584 FIELD(TB_FLAGS, VS, 5, 2) 585 FIELD(TB_FLAGS, LMUL, 7, 3) 586 FIELD(TB_FLAGS, SEW, 10, 3) 587 FIELD(TB_FLAGS, VL_EQ_VLMAX, 13, 1) 588 FIELD(TB_FLAGS, VILL, 14, 1) 589 FIELD(TB_FLAGS, VSTART_EQ_ZERO, 15, 1) 590 /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ 591 FIELD(TB_FLAGS, XL, 16, 2) 592 /* If PointerMasking should be applied */ 593 FIELD(TB_FLAGS, PM_MASK_ENABLED, 18, 1) 594 FIELD(TB_FLAGS, PM_BASE_ENABLED, 19, 1) 595 FIELD(TB_FLAGS, VTA, 20, 1) 596 FIELD(TB_FLAGS, VMA, 21, 1) 597 /* Native debug itrigger */ 598 FIELD(TB_FLAGS, ITRIGGER, 22, 1) 599 /* Virtual mode enabled */ 600 FIELD(TB_FLAGS, VIRT_ENABLED, 23, 1) 601 FIELD(TB_FLAGS, PRIV, 24, 2) 602 FIELD(TB_FLAGS, AXL, 26, 2) 603 604 #ifdef TARGET_RISCV32 605 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) 606 #else 607 static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) 608 { 609 return env->misa_mxl; 610 } 611 #endif 612 #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env))) 613 614 static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURISCVState *env) 615 { 616 return &env_archcpu(env)->cfg; 617 } 618 619 #if !defined(CONFIG_USER_ONLY) 620 static inline int cpu_address_mode(CPURISCVState *env) 621 { 622 int mode = env->priv; 623 624 if (mode == PRV_M && get_field(env->mstatus, MSTATUS_MPRV)) { 625 mode = get_field(env->mstatus, MSTATUS_MPP); 626 } 627 return mode; 628 } 629 630 static inline RISCVMXL cpu_get_xl(CPURISCVState *env, target_ulong mode) 631 { 632 RISCVMXL xl = env->misa_mxl; 633 /* 634 * When emulating a 32-bit-only cpu, use RV32. 635 * When emulating a 64-bit cpu, and MXL has been reduced to RV32, 636 * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened 637 * back to RV64 for lower privs. 638 */ 639 if (xl != MXL_RV32) { 640 switch (mode) { 641 case PRV_M: 642 break; 643 case PRV_U: 644 xl = get_field(env->mstatus, MSTATUS64_UXL); 645 break; 646 default: /* PRV_S */ 647 xl = get_field(env->mstatus, MSTATUS64_SXL); 648 break; 649 } 650 } 651 return xl; 652 } 653 #endif 654 655 #if defined(TARGET_RISCV32) 656 #define cpu_recompute_xl(env) ((void)(env), MXL_RV32) 657 #else 658 static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) 659 { 660 #if !defined(CONFIG_USER_ONLY) 661 return cpu_get_xl(env, env->priv); 662 #else 663 return env->misa_mxl; 664 #endif 665 } 666 #endif 667 668 #if defined(TARGET_RISCV32) 669 #define cpu_address_xl(env) ((void)(env), MXL_RV32) 670 #else 671 static inline RISCVMXL cpu_address_xl(CPURISCVState *env) 672 { 673 #ifdef CONFIG_USER_ONLY 674 return env->xl; 675 #else 676 int mode = cpu_address_mode(env); 677 678 return cpu_get_xl(env, mode); 679 #endif 680 } 681 #endif 682 683 static inline int riscv_cpu_xlen(CPURISCVState *env) 684 { 685 return 16 << env->xl; 686 } 687 688 #ifdef TARGET_RISCV32 689 #define riscv_cpu_sxl(env) ((void)(env), MXL_RV32) 690 #else 691 static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env) 692 { 693 #ifdef CONFIG_USER_ONLY 694 return env->misa_mxl; 695 #else 696 return get_field(env->mstatus, MSTATUS64_SXL); 697 #endif 698 } 699 #endif 700 701 /* 702 * Encode LMUL to lmul as follows: 703 * LMUL vlmul lmul 704 * 1 000 0 705 * 2 001 1 706 * 4 010 2 707 * 8 011 3 708 * - 100 - 709 * 1/8 101 -3 710 * 1/4 110 -2 711 * 1/2 111 -1 712 * 713 * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul) 714 * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8 715 * => VLMAX = vlen >> (1 + 3 - (-3)) 716 * = 256 >> 7 717 * = 2 718 */ 719 static inline uint32_t vext_get_vlmax(uint32_t vlenb, uint32_t vsew, 720 int8_t lmul) 721 { 722 uint32_t vlen = vlenb << 3; 723 724 /* 725 * We need to use 'vlen' instead of 'vlenb' to 726 * preserve the '+ 3' in the formula. Otherwise 727 * we risk a negative shift if vsew < lmul. 728 */ 729 return vlen >> (vsew + 3 - lmul); 730 } 731 732 void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, 733 uint64_t *cs_base, uint32_t *pflags); 734 735 void riscv_cpu_update_mask(CPURISCVState *env); 736 bool riscv_cpu_is_32bit(RISCVCPU *cpu); 737 738 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, 739 target_ulong *ret_value, 740 target_ulong new_value, target_ulong write_mask); 741 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, 742 target_ulong *ret_value, 743 target_ulong new_value, 744 target_ulong write_mask); 745 746 static inline void riscv_csr_write(CPURISCVState *env, int csrno, 747 target_ulong val) 748 { 749 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); 750 } 751 752 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) 753 { 754 target_ulong val = 0; 755 riscv_csrrw(env, csrno, &val, 0, 0); 756 return val; 757 } 758 759 typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, 760 int csrno); 761 typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, 762 target_ulong *ret_value); 763 typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, 764 target_ulong new_value); 765 typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, 766 target_ulong *ret_value, 767 target_ulong new_value, 768 target_ulong write_mask); 769 770 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, 771 Int128 *ret_value, 772 Int128 new_value, Int128 write_mask); 773 774 typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno, 775 Int128 *ret_value); 776 typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int csrno, 777 Int128 new_value); 778 779 typedef struct { 780 const char *name; 781 riscv_csr_predicate_fn predicate; 782 riscv_csr_read_fn read; 783 riscv_csr_write_fn write; 784 riscv_csr_op_fn op; 785 riscv_csr_read128_fn read128; 786 riscv_csr_write128_fn write128; 787 /* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0) */ 788 uint32_t min_priv_ver; 789 } riscv_csr_operations; 790 791 /* CSR function table constants */ 792 enum { 793 CSR_TABLE_SIZE = 0x1000 794 }; 795 796 /* 797 * The event id are encoded based on the encoding specified in the 798 * SBI specification v0.3 799 */ 800 801 enum riscv_pmu_event_idx { 802 RISCV_PMU_EVENT_HW_CPU_CYCLES = 0x01, 803 RISCV_PMU_EVENT_HW_INSTRUCTIONS = 0x02, 804 RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS = 0x10019, 805 RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS = 0x1001B, 806 RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS = 0x10021, 807 }; 808 809 /* used by tcg/tcg-cpu.c*/ 810 void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en); 811 bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset); 812 void riscv_cpu_set_misa_ext(CPURISCVState *env, uint32_t ext); 813 bool riscv_cpu_is_vendor(Object *cpu_obj); 814 815 typedef struct RISCVCPUMultiExtConfig { 816 const char *name; 817 uint32_t offset; 818 bool enabled; 819 } RISCVCPUMultiExtConfig; 820 821 extern const RISCVCPUMultiExtConfig riscv_cpu_extensions[]; 822 extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[]; 823 extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[]; 824 extern const RISCVCPUMultiExtConfig riscv_cpu_named_features[]; 825 extern const RISCVCPUMultiExtConfig riscv_cpu_deprecated_exts[]; 826 827 typedef struct isa_ext_data { 828 const char *name; 829 int min_version; 830 int ext_enable_offset; 831 } RISCVIsaExtData; 832 extern const RISCVIsaExtData isa_edata_arr[]; 833 char *riscv_cpu_get_name(RISCVCPU *cpu); 834 835 void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp); 836 void riscv_add_satp_mode_properties(Object *obj); 837 bool riscv_cpu_accelerator_compatible(RISCVCPU *cpu); 838 839 /* CSR function table */ 840 extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; 841 842 extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[]; 843 844 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); 845 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); 846 847 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); 848 849 target_ulong riscv_new_csr_seed(target_ulong new_value, 850 target_ulong write_mask); 851 852 uint8_t satp_mode_max_from_map(uint32_t map); 853 const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); 854 855 /* Implemented in th_csr.c */ 856 void th_register_custom_csrs(RISCVCPU *cpu); 857 858 const char *priv_spec_to_str(int priv_version); 859 #endif /* RISCV_CPU_H */ 860