1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef RISCV_CPU_H 21 #define RISCV_CPU_H 22 23 #include "hw/core/cpu.h" 24 #include "hw/registerfields.h" 25 #include "exec/cpu-defs.h" 26 #include "qemu/cpu-float.h" 27 #include "qom/object.h" 28 #include "qemu/int128.h" 29 #include "cpu_bits.h" 30 31 #define TCG_GUEST_DEFAULT_MO 0 32 33 /* 34 * RISC-V-specific extra insn start words: 35 * 1: Original instruction opcode 36 */ 37 #define TARGET_INSN_START_EXTRA_WORDS 1 38 39 #define TYPE_RISCV_CPU "riscv-cpu" 40 41 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU 42 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) 43 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU 44 45 #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") 46 #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") 47 #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") 48 #define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128") 49 #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") 50 #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") 51 #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") 52 #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") 53 #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") 54 #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") 55 #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") 56 #define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906") 57 #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") 58 59 #if defined(TARGET_RISCV32) 60 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 61 #elif defined(TARGET_RISCV64) 62 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 63 #endif 64 65 #define RV(x) ((target_ulong)1 << (x - 'A')) 66 67 /* 68 * Consider updating register_cpu_props() when adding 69 * new MISA bits here. 70 */ 71 #define RVI RV('I') 72 #define RVE RV('E') /* E and I are mutually exclusive */ 73 #define RVM RV('M') 74 #define RVA RV('A') 75 #define RVF RV('F') 76 #define RVD RV('D') 77 #define RVV RV('V') 78 #define RVC RV('C') 79 #define RVS RV('S') 80 #define RVU RV('U') 81 #define RVH RV('H') 82 #define RVJ RV('J') 83 84 /* S extension denotes that Supervisor mode exists, however it is possible 85 to have a core that support S mode but does not have an MMU and there 86 is currently no bit in misa to indicate whether an MMU exists or not 87 so a cpu features bitfield is required, likewise for optional PMP support */ 88 enum { 89 RISCV_FEATURE_MMU, 90 RISCV_FEATURE_PMP, 91 RISCV_FEATURE_EPMP, 92 }; 93 94 /* Privileged specification version */ 95 enum { 96 PRIV_VERSION_1_10_0 = 0, 97 PRIV_VERSION_1_11_0, 98 PRIV_VERSION_1_12_0, 99 }; 100 101 #define VEXT_VERSION_1_00_0 0x00010000 102 103 enum { 104 TRANSLATE_SUCCESS, 105 TRANSLATE_FAIL, 106 TRANSLATE_PMP_FAIL, 107 TRANSLATE_G_STAGE_FAIL 108 }; 109 110 #define MMU_USER_IDX 3 111 112 #define MAX_RISCV_PMPS (16) 113 114 typedef struct CPUArchState CPURISCVState; 115 116 #if !defined(CONFIG_USER_ONLY) 117 #include "pmp.h" 118 #include "debug.h" 119 #endif 120 121 #define RV_VLEN_MAX 1024 122 #define RV_MAX_MHPMEVENTS 32 123 #define RV_MAX_MHPMCOUNTERS 32 124 125 FIELD(VTYPE, VLMUL, 0, 3) 126 FIELD(VTYPE, VSEW, 3, 3) 127 FIELD(VTYPE, VTA, 6, 1) 128 FIELD(VTYPE, VMA, 7, 1) 129 FIELD(VTYPE, VEDIV, 8, 2) 130 FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) 131 132 typedef struct PMUCTRState { 133 /* Current value of a counter */ 134 target_ulong mhpmcounter_val; 135 /* Current value of a counter in RV32*/ 136 target_ulong mhpmcounterh_val; 137 /* Snapshot values of counter */ 138 target_ulong mhpmcounter_prev; 139 /* Snapshort value of a counter in RV32 */ 140 target_ulong mhpmcounterh_prev; 141 bool started; 142 /* Value beyond UINT32_MAX/UINT64_MAX before overflow interrupt trigger */ 143 target_ulong irq_overflow_left; 144 } PMUCTRState; 145 146 struct CPUArchState { 147 target_ulong gpr[32]; 148 target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ 149 150 /* vector coprocessor state. */ 151 uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); 152 target_ulong vxrm; 153 target_ulong vxsat; 154 target_ulong vl; 155 target_ulong vstart; 156 target_ulong vtype; 157 bool vill; 158 159 target_ulong pc; 160 target_ulong load_res; 161 target_ulong load_val; 162 163 /* Floating-Point state */ 164 uint64_t fpr[32]; /* assume both F and D extensions */ 165 target_ulong frm; 166 float_status fp_status; 167 168 target_ulong badaddr; 169 target_ulong bins; 170 171 target_ulong guest_phys_fault_addr; 172 173 target_ulong priv_ver; 174 target_ulong bext_ver; 175 target_ulong vext_ver; 176 177 /* RISCVMXL, but uint32_t for vmstate migration */ 178 uint32_t misa_mxl; /* current mxl */ 179 uint32_t misa_mxl_max; /* max mxl for this cpu */ 180 uint32_t misa_ext; /* current extensions */ 181 uint32_t misa_ext_mask; /* max ext for this cpu */ 182 uint32_t xl; /* current xlen */ 183 184 /* 128-bit helpers upper part return value */ 185 target_ulong retxh; 186 187 uint32_t features; 188 189 #ifdef CONFIG_USER_ONLY 190 uint32_t elf_flags; 191 #endif 192 193 #ifndef CONFIG_USER_ONLY 194 target_ulong priv; 195 /* This contains QEMU specific information about the virt state. */ 196 target_ulong virt; 197 target_ulong geilen; 198 uint64_t resetvec; 199 200 target_ulong mhartid; 201 /* 202 * For RV32 this is 32-bit mstatus and 32-bit mstatush. 203 * For RV64 this is a 64-bit mstatus. 204 */ 205 uint64_t mstatus; 206 207 uint64_t mip; 208 /* 209 * MIP contains the software writable version of SEIP ORed with the 210 * external interrupt value. The MIP register is always up-to-date. 211 * To keep track of the current source, we also save booleans of the values 212 * here. 213 */ 214 bool external_seip; 215 bool software_seip; 216 217 uint64_t miclaim; 218 219 uint64_t mie; 220 uint64_t mideleg; 221 222 target_ulong satp; /* since: priv-1.10.0 */ 223 target_ulong stval; 224 target_ulong medeleg; 225 226 target_ulong stvec; 227 target_ulong sepc; 228 target_ulong scause; 229 230 target_ulong mtvec; 231 target_ulong mepc; 232 target_ulong mcause; 233 target_ulong mtval; /* since: priv-1.10.0 */ 234 235 /* Machine and Supervisor interrupt priorities */ 236 uint8_t miprio[64]; 237 uint8_t siprio[64]; 238 239 /* AIA CSRs */ 240 target_ulong miselect; 241 target_ulong siselect; 242 243 /* Hypervisor CSRs */ 244 target_ulong hstatus; 245 target_ulong hedeleg; 246 uint64_t hideleg; 247 target_ulong hcounteren; 248 target_ulong htval; 249 target_ulong htinst; 250 target_ulong hgatp; 251 target_ulong hgeie; 252 target_ulong hgeip; 253 uint64_t htimedelta; 254 255 /* Hypervisor controlled virtual interrupt priorities */ 256 target_ulong hvictl; 257 uint8_t hviprio[64]; 258 259 /* Upper 64-bits of 128-bit CSRs */ 260 uint64_t mscratchh; 261 uint64_t sscratchh; 262 263 /* Virtual CSRs */ 264 /* 265 * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. 266 * For RV64 this is a 64-bit vsstatus. 267 */ 268 uint64_t vsstatus; 269 target_ulong vstvec; 270 target_ulong vsscratch; 271 target_ulong vsepc; 272 target_ulong vscause; 273 target_ulong vstval; 274 target_ulong vsatp; 275 276 /* AIA VS-mode CSRs */ 277 target_ulong vsiselect; 278 279 target_ulong mtval2; 280 target_ulong mtinst; 281 282 /* HS Backup CSRs */ 283 target_ulong stvec_hs; 284 target_ulong sscratch_hs; 285 target_ulong sepc_hs; 286 target_ulong scause_hs; 287 target_ulong stval_hs; 288 target_ulong satp_hs; 289 uint64_t mstatus_hs; 290 291 /* Signals whether the current exception occurred with two-stage address 292 translation active. */ 293 bool two_stage_lookup; 294 /* 295 * Signals whether the current exception occurred while doing two-stage 296 * address translation for the VS-stage page table walk. 297 */ 298 bool two_stage_indirect_lookup; 299 300 target_ulong scounteren; 301 target_ulong mcounteren; 302 303 target_ulong mcountinhibit; 304 305 /* PMU counter state */ 306 PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS]; 307 308 /* PMU event selector configured values. First three are unused*/ 309 target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS]; 310 311 /* PMU event selector configured values for RV32*/ 312 target_ulong mhpmeventh_val[RV_MAX_MHPMEVENTS]; 313 314 target_ulong sscratch; 315 target_ulong mscratch; 316 317 /* Sstc CSRs */ 318 uint64_t stimecmp; 319 320 uint64_t vstimecmp; 321 322 /* physical memory protection */ 323 pmp_table_t pmp_state; 324 target_ulong mseccfg; 325 326 /* trigger module */ 327 target_ulong trigger_cur; 328 target_ulong tdata1[RV_MAX_TRIGGERS]; 329 target_ulong tdata2[RV_MAX_TRIGGERS]; 330 target_ulong tdata3[RV_MAX_TRIGGERS]; 331 struct CPUBreakpoint *cpu_breakpoint[RV_MAX_TRIGGERS]; 332 struct CPUWatchpoint *cpu_watchpoint[RV_MAX_TRIGGERS]; 333 QEMUTimer *itrigger_timer[RV_MAX_TRIGGERS]; 334 int64_t last_icount; 335 bool itrigger_enabled; 336 337 /* machine specific rdtime callback */ 338 uint64_t (*rdtime_fn)(void *); 339 void *rdtime_fn_arg; 340 341 /* machine specific AIA ireg read-modify-write callback */ 342 #define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \ 343 ((((__xlen) & 0xff) << 24) | \ 344 (((__vgein) & 0x3f) << 20) | \ 345 (((__virt) & 0x1) << 18) | \ 346 (((__priv) & 0x3) << 16) | \ 347 (__isel & 0xffff)) 348 #define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff) 349 #define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3) 350 #define AIA_IREG_VIRT(__ireg) (((__ireg) >> 18) & 0x1) 351 #define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 20) & 0x3f) 352 #define AIA_IREG_XLEN(__ireg) (((__ireg) >> 24) & 0xff) 353 int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg, 354 target_ulong *val, target_ulong new_val, target_ulong write_mask); 355 void *aia_ireg_rmw_fn_arg[4]; 356 357 /* True if in debugger mode. */ 358 bool debugger; 359 360 /* 361 * CSRs for PointerMasking extension 362 */ 363 target_ulong mmte; 364 target_ulong mpmmask; 365 target_ulong mpmbase; 366 target_ulong spmmask; 367 target_ulong spmbase; 368 target_ulong upmmask; 369 target_ulong upmbase; 370 371 /* CSRs for execution enviornment configuration */ 372 uint64_t menvcfg; 373 uint64_t mstateen[SMSTATEEN_MAX_COUNT]; 374 uint64_t hstateen[SMSTATEEN_MAX_COUNT]; 375 uint64_t sstateen[SMSTATEEN_MAX_COUNT]; 376 target_ulong senvcfg; 377 uint64_t henvcfg; 378 #endif 379 target_ulong cur_pmmask; 380 target_ulong cur_pmbase; 381 382 /* Fields from here on are preserved across CPU reset. */ 383 QEMUTimer *stimer; /* Internal timer for S-mode interrupt */ 384 QEMUTimer *vstimer; /* Internal timer for VS-mode interrupt */ 385 bool vstime_irq; 386 387 hwaddr kernel_addr; 388 hwaddr fdt_addr; 389 390 /* kvm timer */ 391 bool kvm_timer_dirty; 392 uint64_t kvm_timer_time; 393 uint64_t kvm_timer_compare; 394 uint64_t kvm_timer_state; 395 uint64_t kvm_timer_frequency; 396 }; 397 398 OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) 399 400 /** 401 * RISCVCPUClass: 402 * @parent_realize: The parent class' realize handler. 403 * @parent_phases: The parent class' reset phase handlers. 404 * 405 * A RISCV CPU model. 406 */ 407 struct RISCVCPUClass { 408 /*< private >*/ 409 CPUClass parent_class; 410 /*< public >*/ 411 DeviceRealize parent_realize; 412 ResettablePhases parent_phases; 413 }; 414 415 struct RISCVCPUConfig { 416 bool ext_i; 417 bool ext_e; 418 bool ext_g; 419 bool ext_m; 420 bool ext_a; 421 bool ext_f; 422 bool ext_d; 423 bool ext_c; 424 bool ext_s; 425 bool ext_u; 426 bool ext_h; 427 bool ext_j; 428 bool ext_v; 429 bool ext_zba; 430 bool ext_zbb; 431 bool ext_zbc; 432 bool ext_zbkb; 433 bool ext_zbkc; 434 bool ext_zbkx; 435 bool ext_zbs; 436 bool ext_zk; 437 bool ext_zkn; 438 bool ext_zknd; 439 bool ext_zkne; 440 bool ext_zknh; 441 bool ext_zkr; 442 bool ext_zks; 443 bool ext_zksed; 444 bool ext_zksh; 445 bool ext_zkt; 446 bool ext_ifencei; 447 bool ext_icsr; 448 bool ext_zihintpause; 449 bool ext_smstateen; 450 bool ext_sstc; 451 bool ext_svinval; 452 bool ext_svnapot; 453 bool ext_svpbmt; 454 bool ext_zdinx; 455 bool ext_zawrs; 456 bool ext_zfh; 457 bool ext_zfhmin; 458 bool ext_zfinx; 459 bool ext_zhinx; 460 bool ext_zhinxmin; 461 bool ext_zve32f; 462 bool ext_zve64f; 463 bool ext_zmmul; 464 bool ext_smaia; 465 bool ext_ssaia; 466 bool ext_sscofpmf; 467 bool rvv_ta_all_1s; 468 bool rvv_ma_all_1s; 469 470 uint32_t mvendorid; 471 uint64_t marchid; 472 uint64_t mimpid; 473 474 /* Vendor-specific custom extensions */ 475 bool ext_xtheadba; 476 bool ext_xtheadbb; 477 bool ext_xtheadbs; 478 bool ext_xtheadcmo; 479 bool ext_xtheadcondmov; 480 bool ext_xtheadfmemidx; 481 bool ext_xtheadfmv; 482 bool ext_xtheadmac; 483 bool ext_xtheadmemidx; 484 bool ext_xtheadmempair; 485 bool ext_xtheadsync; 486 bool ext_XVentanaCondOps; 487 488 uint8_t pmu_num; 489 char *priv_spec; 490 char *user_spec; 491 char *bext_spec; 492 char *vext_spec; 493 uint16_t vlen; 494 uint16_t elen; 495 bool mmu; 496 bool pmp; 497 bool epmp; 498 bool debug; 499 bool misa_w; 500 501 bool short_isa_string; 502 }; 503 504 typedef struct RISCVCPUConfig RISCVCPUConfig; 505 506 /** 507 * RISCVCPU: 508 * @env: #CPURISCVState 509 * 510 * A RISCV CPU. 511 */ 512 struct ArchCPU { 513 /*< private >*/ 514 CPUState parent_obj; 515 /*< public >*/ 516 CPUNegativeOffsetState neg; 517 CPURISCVState env; 518 519 char *dyn_csr_xml; 520 char *dyn_vreg_xml; 521 522 /* Configuration Settings */ 523 RISCVCPUConfig cfg; 524 525 QEMUTimer *pmu_timer; 526 /* A bitmask of Available programmable counters */ 527 uint32_t pmu_avail_ctrs; 528 /* Mapping of events to counters */ 529 GHashTable *pmu_event_ctr_map; 530 }; 531 532 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) 533 { 534 return (env->misa_ext & ext) != 0; 535 } 536 537 static inline bool riscv_feature(CPURISCVState *env, int feature) 538 { 539 return env->features & (1ULL << feature); 540 } 541 542 static inline void riscv_set_feature(CPURISCVState *env, int feature) 543 { 544 env->features |= (1ULL << feature); 545 } 546 547 #include "cpu_user.h" 548 549 extern const char * const riscv_int_regnames[]; 550 extern const char * const riscv_int_regnamesh[]; 551 extern const char * const riscv_fpr_regnames[]; 552 553 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); 554 void riscv_cpu_do_interrupt(CPUState *cpu); 555 int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 556 int cpuid, DumpState *s); 557 int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 558 int cpuid, DumpState *s); 559 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 560 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 561 int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero); 562 uint8_t riscv_cpu_default_priority(int irq); 563 uint64_t riscv_cpu_all_pending(CPURISCVState *env); 564 int riscv_cpu_mirq_pending(CPURISCVState *env); 565 int riscv_cpu_sirq_pending(CPURISCVState *env); 566 int riscv_cpu_vsirq_pending(CPURISCVState *env); 567 bool riscv_cpu_fp_enabled(CPURISCVState *env); 568 target_ulong riscv_cpu_get_geilen(CPURISCVState *env); 569 void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); 570 bool riscv_cpu_vector_enabled(CPURISCVState *env); 571 bool riscv_cpu_virt_enabled(CPURISCVState *env); 572 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); 573 bool riscv_cpu_two_stage_lookup(int mmu_idx); 574 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); 575 G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 576 MMUAccessType access_type, int mmu_idx, 577 uintptr_t retaddr); 578 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 579 MMUAccessType access_type, int mmu_idx, 580 bool probe, uintptr_t retaddr); 581 char *riscv_isa_string(RISCVCPU *cpu); 582 void riscv_cpu_list(void); 583 584 #define cpu_list riscv_cpu_list 585 #define cpu_mmu_index riscv_cpu_mmu_index 586 587 #ifndef CONFIG_USER_ONLY 588 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 589 vaddr addr, unsigned size, 590 MMUAccessType access_type, 591 int mmu_idx, MemTxAttrs attrs, 592 MemTxResult response, uintptr_t retaddr); 593 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 594 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); 595 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); 596 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); 597 uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value); 598 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ 599 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), 600 void *arg); 601 void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, 602 int (*rmw_fn)(void *arg, 603 target_ulong reg, 604 target_ulong *val, 605 target_ulong new_val, 606 target_ulong write_mask), 607 void *rmw_fn_arg); 608 #endif 609 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); 610 611 void riscv_translate_init(void); 612 G_NORETURN void riscv_raise_exception(CPURISCVState *env, 613 uint32_t exception, uintptr_t pc); 614 615 target_ulong riscv_cpu_get_fflags(CPURISCVState *env); 616 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); 617 618 #define TB_FLAGS_PRIV_MMU_MASK 3 619 #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2) 620 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS 621 #define TB_FLAGS_MSTATUS_VS MSTATUS_VS 622 623 #include "exec/cpu-all.h" 624 625 FIELD(TB_FLAGS, MEM_IDX, 0, 3) 626 FIELD(TB_FLAGS, LMUL, 3, 3) 627 FIELD(TB_FLAGS, SEW, 6, 3) 628 /* Skip MSTATUS_VS (0x600) bits */ 629 FIELD(TB_FLAGS, VL_EQ_VLMAX, 11, 1) 630 FIELD(TB_FLAGS, VILL, 12, 1) 631 /* Skip MSTATUS_FS (0x6000) bits */ 632 /* Is a Hypervisor instruction load/store allowed? */ 633 FIELD(TB_FLAGS, HLSX, 15, 1) 634 FIELD(TB_FLAGS, MSTATUS_HS_FS, 16, 2) 635 FIELD(TB_FLAGS, MSTATUS_HS_VS, 18, 2) 636 /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ 637 FIELD(TB_FLAGS, XL, 20, 2) 638 /* If PointerMasking should be applied */ 639 FIELD(TB_FLAGS, PM_MASK_ENABLED, 22, 1) 640 FIELD(TB_FLAGS, PM_BASE_ENABLED, 23, 1) 641 FIELD(TB_FLAGS, VTA, 24, 1) 642 FIELD(TB_FLAGS, VMA, 25, 1) 643 /* Native debug itrigger */ 644 FIELD(TB_FLAGS, ITRIGGER, 26, 1) 645 646 #ifdef TARGET_RISCV32 647 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) 648 #else 649 static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) 650 { 651 return env->misa_mxl; 652 } 653 #endif 654 #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env))) 655 656 static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURISCVState *env) 657 { 658 return &env_archcpu(env)->cfg; 659 } 660 661 #if defined(TARGET_RISCV32) 662 #define cpu_recompute_xl(env) ((void)(env), MXL_RV32) 663 #else 664 static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) 665 { 666 RISCVMXL xl = env->misa_mxl; 667 #if !defined(CONFIG_USER_ONLY) 668 /* 669 * When emulating a 32-bit-only cpu, use RV32. 670 * When emulating a 64-bit cpu, and MXL has been reduced to RV32, 671 * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened 672 * back to RV64 for lower privs. 673 */ 674 if (xl != MXL_RV32) { 675 switch (env->priv) { 676 case PRV_M: 677 break; 678 case PRV_U: 679 xl = get_field(env->mstatus, MSTATUS64_UXL); 680 break; 681 default: /* PRV_S | PRV_H */ 682 xl = get_field(env->mstatus, MSTATUS64_SXL); 683 break; 684 } 685 } 686 #endif 687 return xl; 688 } 689 #endif 690 691 static inline int riscv_cpu_xlen(CPURISCVState *env) 692 { 693 return 16 << env->xl; 694 } 695 696 #ifdef TARGET_RISCV32 697 #define riscv_cpu_sxl(env) ((void)(env), MXL_RV32) 698 #else 699 static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env) 700 { 701 #ifdef CONFIG_USER_ONLY 702 return env->misa_mxl; 703 #else 704 return get_field(env->mstatus, MSTATUS64_SXL); 705 #endif 706 } 707 #endif 708 709 /* 710 * Encode LMUL to lmul as follows: 711 * LMUL vlmul lmul 712 * 1 000 0 713 * 2 001 1 714 * 4 010 2 715 * 8 011 3 716 * - 100 - 717 * 1/8 101 -3 718 * 1/4 110 -2 719 * 1/2 111 -1 720 * 721 * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul) 722 * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8 723 * => VLMAX = vlen >> (1 + 3 - (-3)) 724 * = 256 >> 7 725 * = 2 726 */ 727 static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) 728 { 729 uint8_t sew = FIELD_EX64(vtype, VTYPE, VSEW); 730 int8_t lmul = sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3); 731 return cpu->cfg.vlen >> (sew + 3 - lmul); 732 } 733 734 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 735 target_ulong *cs_base, uint32_t *pflags); 736 737 void riscv_cpu_update_mask(CPURISCVState *env); 738 739 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, 740 target_ulong *ret_value, 741 target_ulong new_value, target_ulong write_mask); 742 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, 743 target_ulong *ret_value, 744 target_ulong new_value, 745 target_ulong write_mask); 746 747 static inline void riscv_csr_write(CPURISCVState *env, int csrno, 748 target_ulong val) 749 { 750 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); 751 } 752 753 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) 754 { 755 target_ulong val = 0; 756 riscv_csrrw(env, csrno, &val, 0, 0); 757 return val; 758 } 759 760 typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, 761 int csrno); 762 typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, 763 target_ulong *ret_value); 764 typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, 765 target_ulong new_value); 766 typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, 767 target_ulong *ret_value, 768 target_ulong new_value, 769 target_ulong write_mask); 770 771 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, 772 Int128 *ret_value, 773 Int128 new_value, Int128 write_mask); 774 775 typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno, 776 Int128 *ret_value); 777 typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int csrno, 778 Int128 new_value); 779 780 typedef struct { 781 const char *name; 782 riscv_csr_predicate_fn predicate; 783 riscv_csr_read_fn read; 784 riscv_csr_write_fn write; 785 riscv_csr_op_fn op; 786 riscv_csr_read128_fn read128; 787 riscv_csr_write128_fn write128; 788 /* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0) */ 789 uint32_t min_priv_ver; 790 } riscv_csr_operations; 791 792 /* CSR function table constants */ 793 enum { 794 CSR_TABLE_SIZE = 0x1000 795 }; 796 797 /** 798 * The event id are encoded based on the encoding specified in the 799 * SBI specification v0.3 800 */ 801 802 enum riscv_pmu_event_idx { 803 RISCV_PMU_EVENT_HW_CPU_CYCLES = 0x01, 804 RISCV_PMU_EVENT_HW_INSTRUCTIONS = 0x02, 805 RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS = 0x10019, 806 RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS = 0x1001B, 807 RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS = 0x10021, 808 }; 809 810 /* CSR function table */ 811 extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; 812 813 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); 814 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); 815 816 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); 817 818 #endif /* RISCV_CPU_H */ 819