1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef RISCV_CPU_H 21 #define RISCV_CPU_H 22 23 /* QEMU addressing/paging config */ 24 #define TARGET_PAGE_BITS 12 /* 4 KiB Pages */ 25 #if defined(TARGET_RISCV64) 26 #define TARGET_LONG_BITS 64 27 #define TARGET_PHYS_ADDR_SPACE_BITS 56 /* 44-bit PPN */ 28 #define TARGET_VIRT_ADDR_SPACE_BITS 48 /* sv48 */ 29 #elif defined(TARGET_RISCV32) 30 #define TARGET_LONG_BITS 32 31 #define TARGET_PHYS_ADDR_SPACE_BITS 34 /* 22-bit PPN */ 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */ 33 #endif 34 35 #define TCG_GUEST_DEFAULT_MO 0 36 37 #define CPUArchState struct CPURISCVState 38 39 #include "qemu-common.h" 40 #include "qom/cpu.h" 41 #include "exec/cpu-defs.h" 42 #include "fpu/softfloat.h" 43 44 #define TYPE_RISCV_CPU "riscv-cpu" 45 46 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU 47 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) 48 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU 49 50 #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") 51 #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") 52 #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") 53 #define TYPE_RISCV_CPU_RV32GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9.1") 54 #define TYPE_RISCV_CPU_RV32GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.10.0") 55 #define TYPE_RISCV_CPU_RV32IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv32imacu-nommu") 56 #define TYPE_RISCV_CPU_RV64GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.9.1") 57 #define TYPE_RISCV_CPU_RV64GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.10.0") 58 #define TYPE_RISCV_CPU_RV64IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv64imacu-nommu") 59 #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") 60 #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") 61 #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") 62 #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") 63 64 #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2)) 65 #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2)) 66 67 #if defined(TARGET_RISCV32) 68 #define RVXLEN RV32 69 #elif defined(TARGET_RISCV64) 70 #define RVXLEN RV64 71 #endif 72 73 #define RV(x) ((target_ulong)1 << (x - 'A')) 74 75 #define RVI RV('I') 76 #define RVE RV('E') /* E and I are mutually exclusive */ 77 #define RVM RV('M') 78 #define RVA RV('A') 79 #define RVF RV('F') 80 #define RVD RV('D') 81 #define RVC RV('C') 82 #define RVS RV('S') 83 #define RVU RV('U') 84 85 /* S extension denotes that Supervisor mode exists, however it is possible 86 to have a core that support S mode but does not have an MMU and there 87 is currently no bit in misa to indicate whether an MMU exists or not 88 so a cpu features bitfield is required, likewise for optional PMP support */ 89 enum { 90 RISCV_FEATURE_MMU, 91 RISCV_FEATURE_PMP, 92 RISCV_FEATURE_MISA 93 }; 94 95 #define USER_VERSION_2_02_0 0x00020200 96 #define PRIV_VERSION_1_09_1 0x00010901 97 #define PRIV_VERSION_1_10_0 0x00011000 98 99 #define TRANSLATE_FAIL 1 100 #define TRANSLATE_SUCCESS 0 101 #define NB_MMU_MODES 4 102 #define MMU_USER_IDX 3 103 104 #define MAX_RISCV_PMPS (16) 105 106 typedef struct CPURISCVState CPURISCVState; 107 108 #include "pmp.h" 109 110 struct CPURISCVState { 111 target_ulong gpr[32]; 112 uint64_t fpr[32]; /* assume both F and D extensions */ 113 target_ulong pc; 114 target_ulong load_res; 115 target_ulong load_val; 116 117 target_ulong frm; 118 119 target_ulong badaddr; 120 121 target_ulong user_ver; 122 target_ulong priv_ver; 123 target_ulong misa; 124 target_ulong misa_mask; 125 126 uint32_t features; 127 128 #ifdef CONFIG_USER_ONLY 129 uint32_t elf_flags; 130 #endif 131 132 #ifndef CONFIG_USER_ONLY 133 target_ulong priv; 134 target_ulong resetvec; 135 136 target_ulong mhartid; 137 target_ulong mstatus; 138 139 /* 140 * CAUTION! Unlike the rest of this struct, mip is accessed asynchonously 141 * by I/O threads. It should be read with atomic_read. It should be updated 142 * using riscv_cpu_update_mip with the iothread mutex held. The iothread 143 * mutex must be held because mip must be consistent with the CPU inturrept 144 * state. riscv_cpu_update_mip calls cpu_interrupt or cpu_reset_interrupt 145 * wuth the invariant that CPU_INTERRUPT_HARD is set iff mip is non-zero. 146 * mip is 32-bits to allow atomic_read on 32-bit hosts. 147 */ 148 uint32_t mip; 149 uint32_t miclaim; 150 151 target_ulong mie; 152 target_ulong mideleg; 153 154 target_ulong sptbr; /* until: priv-1.9.1 */ 155 target_ulong satp; /* since: priv-1.10.0 */ 156 target_ulong sbadaddr; 157 target_ulong mbadaddr; 158 target_ulong medeleg; 159 160 target_ulong stvec; 161 target_ulong sepc; 162 target_ulong scause; 163 164 target_ulong mtvec; 165 target_ulong mepc; 166 target_ulong mcause; 167 target_ulong mtval; /* since: priv-1.10.0 */ 168 169 target_ulong scounteren; 170 target_ulong mcounteren; 171 172 target_ulong sscratch; 173 target_ulong mscratch; 174 175 /* temporary htif regs */ 176 uint64_t mfromhost; 177 uint64_t mtohost; 178 uint64_t timecmp; 179 180 /* physical memory protection */ 181 pmp_table_t pmp_state; 182 183 /* True if in debugger mode. */ 184 bool debugger; 185 #endif 186 187 float_status fp_status; 188 189 /* QEMU */ 190 CPU_COMMON 191 192 /* Fields from here on are preserved across CPU reset. */ 193 QEMUTimer *timer; /* Internal timer */ 194 }; 195 196 #define RISCV_CPU_CLASS(klass) \ 197 OBJECT_CLASS_CHECK(RISCVCPUClass, (klass), TYPE_RISCV_CPU) 198 #define RISCV_CPU(obj) \ 199 OBJECT_CHECK(RISCVCPU, (obj), TYPE_RISCV_CPU) 200 #define RISCV_CPU_GET_CLASS(obj) \ 201 OBJECT_GET_CLASS(RISCVCPUClass, (obj), TYPE_RISCV_CPU) 202 203 /** 204 * RISCVCPUClass: 205 * @parent_realize: The parent class' realize handler. 206 * @parent_reset: The parent class' reset handler. 207 * 208 * A RISCV CPU model. 209 */ 210 typedef struct RISCVCPUClass { 211 /*< private >*/ 212 CPUClass parent_class; 213 /*< public >*/ 214 DeviceRealize parent_realize; 215 void (*parent_reset)(CPUState *cpu); 216 } RISCVCPUClass; 217 218 /** 219 * RISCVCPU: 220 * @env: #CPURISCVState 221 * 222 * A RISCV CPU. 223 */ 224 typedef struct RISCVCPU { 225 /*< private >*/ 226 CPUState parent_obj; 227 /*< public >*/ 228 CPURISCVState env; 229 230 /* Configuration Settings */ 231 struct { 232 char *priv_spec; 233 char *user_spec; 234 bool mmu; 235 bool pmp; 236 } cfg; 237 } RISCVCPU; 238 239 static inline RISCVCPU *riscv_env_get_cpu(CPURISCVState *env) 240 { 241 return container_of(env, RISCVCPU, env); 242 } 243 244 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) 245 { 246 return (env->misa & ext) != 0; 247 } 248 249 static inline bool riscv_feature(CPURISCVState *env, int feature) 250 { 251 return env->features & (1ULL << feature); 252 } 253 254 #include "cpu_user.h" 255 #include "cpu_bits.h" 256 257 extern const char * const riscv_int_regnames[]; 258 extern const char * const riscv_fpr_regnames[]; 259 extern const char * const riscv_excp_names[]; 260 extern const char * const riscv_intr_names[]; 261 262 #define ENV_GET_CPU(e) CPU(riscv_env_get_cpu(e)) 263 #define ENV_OFFSET offsetof(RISCVCPU, env) 264 265 void riscv_cpu_do_interrupt(CPUState *cpu); 266 int riscv_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 267 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 268 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); 269 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); 270 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 271 void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 272 MMUAccessType access_type, int mmu_idx, 273 uintptr_t retaddr); 274 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 275 MMUAccessType access_type, int mmu_idx, 276 bool probe, uintptr_t retaddr); 277 char *riscv_isa_string(RISCVCPU *cpu); 278 void riscv_cpu_list(void); 279 280 #define cpu_signal_handler riscv_cpu_signal_handler 281 #define cpu_list riscv_cpu_list 282 #define cpu_mmu_index riscv_cpu_mmu_index 283 284 #ifndef CONFIG_USER_ONLY 285 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts); 286 uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value); 287 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ 288 #endif 289 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); 290 291 void riscv_translate_init(void); 292 int riscv_cpu_signal_handler(int host_signum, void *pinfo, void *puc); 293 void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env, 294 uint32_t exception, uintptr_t pc); 295 296 target_ulong riscv_cpu_get_fflags(CPURISCVState *env); 297 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); 298 299 #define TB_FLAGS_MMU_MASK 3 300 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS 301 302 static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 303 target_ulong *cs_base, uint32_t *flags) 304 { 305 *pc = env->pc; 306 *cs_base = 0; 307 #ifdef CONFIG_USER_ONLY 308 *flags = TB_FLAGS_MSTATUS_FS; 309 #else 310 *flags = cpu_mmu_index(env, 0) | (env->mstatus & MSTATUS_FS); 311 #endif 312 } 313 314 int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, 315 target_ulong new_value, target_ulong write_mask); 316 int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value, 317 target_ulong new_value, target_ulong write_mask); 318 319 static inline void riscv_csr_write(CPURISCVState *env, int csrno, 320 target_ulong val) 321 { 322 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); 323 } 324 325 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) 326 { 327 target_ulong val = 0; 328 riscv_csrrw(env, csrno, &val, 0, 0); 329 return val; 330 } 331 332 typedef int (*riscv_csr_predicate_fn)(CPURISCVState *env, int csrno); 333 typedef int (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, 334 target_ulong *ret_value); 335 typedef int (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, 336 target_ulong new_value); 337 typedef int (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, 338 target_ulong *ret_value, target_ulong new_value, target_ulong write_mask); 339 340 typedef struct { 341 riscv_csr_predicate_fn predicate; 342 riscv_csr_read_fn read; 343 riscv_csr_write_fn write; 344 riscv_csr_op_fn op; 345 } riscv_csr_operations; 346 347 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); 348 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); 349 350 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); 351 352 #include "exec/cpu-all.h" 353 354 #endif /* RISCV_CPU_H */ 355