1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef RISCV_CPU_H 21 #define RISCV_CPU_H 22 23 #include "hw/core/cpu.h" 24 #include "hw/registerfields.h" 25 #include "hw/qdev-properties.h" 26 #include "exec/cpu-defs.h" 27 #include "exec/gdbstub.h" 28 #include "qemu/cpu-float.h" 29 #include "qom/object.h" 30 #include "qemu/int128.h" 31 #include "cpu_bits.h" 32 #include "cpu_cfg.h" 33 #include "qapi/qapi-types-common.h" 34 #include "cpu-qom.h" 35 36 typedef struct CPUArchState CPURISCVState; 37 38 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU 39 40 #if defined(TARGET_RISCV32) 41 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 42 #elif defined(TARGET_RISCV64) 43 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 44 #endif 45 46 /* 47 * RISC-V-specific extra insn start words: 48 * 1: Original instruction opcode 49 * 2: more information about instruction 50 */ 51 #define TARGET_INSN_START_EXTRA_WORDS 2 52 /* 53 * b0: Whether a instruction always raise a store AMO or not. 54 */ 55 #define RISCV_UW2_ALWAYS_STORE_AMO 1 56 57 #define RV(x) ((target_ulong)1 << (x - 'A')) 58 59 /* 60 * Update misa_bits[], misa_ext_info_arr[] and misa_ext_cfgs[] 61 * when adding new MISA bits here. 62 */ 63 #define RVI RV('I') 64 #define RVE RV('E') /* E and I are mutually exclusive */ 65 #define RVM RV('M') 66 #define RVA RV('A') 67 #define RVF RV('F') 68 #define RVD RV('D') 69 #define RVV RV('V') 70 #define RVC RV('C') 71 #define RVS RV('S') 72 #define RVU RV('U') 73 #define RVH RV('H') 74 #define RVG RV('G') 75 #define RVB RV('B') 76 77 extern const uint32_t misa_bits[]; 78 const char *riscv_get_misa_ext_name(uint32_t bit); 79 const char *riscv_get_misa_ext_description(uint32_t bit); 80 81 #define CPU_CFG_OFFSET(_prop) offsetof(struct RISCVCPUConfig, _prop) 82 83 typedef struct riscv_cpu_profile { 84 struct riscv_cpu_profile *parent; 85 const char *name; 86 uint32_t misa_ext; 87 bool enabled; 88 bool user_set; 89 int priv_spec; 90 int satp_mode; 91 const int32_t ext_offsets[]; 92 } RISCVCPUProfile; 93 94 #define RISCV_PROFILE_EXT_LIST_END -1 95 #define RISCV_PROFILE_ATTR_UNUSED -1 96 97 extern RISCVCPUProfile *riscv_profiles[]; 98 99 /* Privileged specification version */ 100 #define PRIV_VER_1_10_0_STR "v1.10.0" 101 #define PRIV_VER_1_11_0_STR "v1.11.0" 102 #define PRIV_VER_1_12_0_STR "v1.12.0" 103 #define PRIV_VER_1_13_0_STR "v1.13.0" 104 enum { 105 PRIV_VERSION_1_10_0 = 0, 106 PRIV_VERSION_1_11_0, 107 PRIV_VERSION_1_12_0, 108 PRIV_VERSION_1_13_0, 109 110 PRIV_VERSION_LATEST = PRIV_VERSION_1_13_0, 111 }; 112 113 #define VEXT_VERSION_1_00_0 0x00010000 114 #define VEXT_VER_1_00_0_STR "v1.0" 115 116 enum { 117 TRANSLATE_SUCCESS, 118 TRANSLATE_FAIL, 119 TRANSLATE_PMP_FAIL, 120 TRANSLATE_G_STAGE_FAIL 121 }; 122 123 /* Extension context status */ 124 typedef enum { 125 EXT_STATUS_DISABLED = 0, 126 EXT_STATUS_INITIAL, 127 EXT_STATUS_CLEAN, 128 EXT_STATUS_DIRTY, 129 } RISCVExtStatus; 130 131 /* Enum holds PMM field values for Zjpm v1.0 extension */ 132 typedef enum { 133 PMM_FIELD_DISABLED = 0, 134 PMM_FIELD_RESERVED = 1, 135 PMM_FIELD_PMLEN7 = 2, 136 PMM_FIELD_PMLEN16 = 3, 137 } RISCVPmPmm; 138 139 typedef struct riscv_cpu_implied_exts_rule { 140 #ifndef CONFIG_USER_ONLY 141 /* 142 * Bitmask indicates the rule enabled status for the harts. 143 * This enhancement is only available in system-mode QEMU, 144 * as we don't have a good way (e.g. mhartid) to distinguish 145 * the SMP cores in user-mode QEMU. 146 */ 147 unsigned long *enabled; 148 #endif 149 /* True if this is a MISA implied rule. */ 150 bool is_misa; 151 /* ext is MISA bit if is_misa flag is true, else multi extension offset. */ 152 const uint32_t ext; 153 const uint32_t implied_misa_exts; 154 const uint32_t implied_multi_exts[]; 155 } RISCVCPUImpliedExtsRule; 156 157 extern RISCVCPUImpliedExtsRule *riscv_misa_ext_implied_rules[]; 158 extern RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[]; 159 160 #define RISCV_IMPLIED_EXTS_RULE_END -1 161 162 #define MMU_USER_IDX 3 163 164 #define MAX_RISCV_PMPS (16) 165 166 #if !defined(CONFIG_USER_ONLY) 167 #include "pmp.h" 168 #include "debug.h" 169 #endif 170 171 #define RV_VLEN_MAX 1024 172 #define RV_MAX_MHPMEVENTS 32 173 #define RV_MAX_MHPMCOUNTERS 32 174 175 FIELD(VTYPE, VLMUL, 0, 3) 176 FIELD(VTYPE, VSEW, 3, 3) 177 FIELD(VTYPE, VTA, 6, 1) 178 FIELD(VTYPE, VMA, 7, 1) 179 FIELD(VTYPE, VEDIV, 8, 2) 180 FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) 181 182 typedef struct PMUCTRState { 183 /* Current value of a counter */ 184 target_ulong mhpmcounter_val; 185 /* Current value of a counter in RV32 */ 186 target_ulong mhpmcounterh_val; 187 /* Snapshot values of counter */ 188 target_ulong mhpmcounter_prev; 189 /* Snapshort value of a counter in RV32 */ 190 target_ulong mhpmcounterh_prev; 191 /* Value beyond UINT32_MAX/UINT64_MAX before overflow interrupt trigger */ 192 target_ulong irq_overflow_left; 193 } PMUCTRState; 194 195 typedef struct PMUFixedCtrState { 196 /* Track cycle and icount for each privilege mode */ 197 uint64_t counter[4]; 198 uint64_t counter_prev[4]; 199 /* Track cycle and icount for each privilege mode when V = 1*/ 200 uint64_t counter_virt[2]; 201 uint64_t counter_virt_prev[2]; 202 } PMUFixedCtrState; 203 204 struct CPUArchState { 205 target_ulong gpr[32]; 206 target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ 207 208 /* vector coprocessor state. */ 209 uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); 210 target_ulong vxrm; 211 target_ulong vxsat; 212 target_ulong vl; 213 target_ulong vstart; 214 target_ulong vtype; 215 bool vill; 216 217 target_ulong pc; 218 target_ulong load_res; 219 target_ulong load_val; 220 221 /* Floating-Point state */ 222 uint64_t fpr[32]; /* assume both F and D extensions */ 223 target_ulong frm; 224 float_status fp_status; 225 226 target_ulong badaddr; 227 target_ulong bins; 228 229 target_ulong guest_phys_fault_addr; 230 231 target_ulong priv_ver; 232 target_ulong vext_ver; 233 234 /* RISCVMXL, but uint32_t for vmstate migration */ 235 uint32_t misa_mxl; /* current mxl */ 236 uint32_t misa_ext; /* current extensions */ 237 uint32_t misa_ext_mask; /* max ext for this cpu */ 238 uint32_t xl; /* current xlen */ 239 240 /* 128-bit helpers upper part return value */ 241 target_ulong retxh; 242 243 target_ulong jvt; 244 245 /* elp state for zicfilp extension */ 246 bool elp; 247 /* shadow stack register for zicfiss extension */ 248 target_ulong ssp; 249 /* env place holder for extra word 2 during unwind */ 250 target_ulong excp_uw2; 251 /* sw check code for sw check exception */ 252 target_ulong sw_check_code; 253 #ifdef CONFIG_USER_ONLY 254 uint32_t elf_flags; 255 #endif 256 257 target_ulong priv; 258 /* CSRs for execution environment configuration */ 259 uint64_t menvcfg; 260 target_ulong senvcfg; 261 262 #ifndef CONFIG_USER_ONLY 263 /* This contains QEMU specific information about the virt state. */ 264 bool virt_enabled; 265 target_ulong geilen; 266 uint64_t resetvec; 267 268 target_ulong mhartid; 269 /* 270 * For RV32 this is 32-bit mstatus and 32-bit mstatush. 271 * For RV64 this is a 64-bit mstatus. 272 */ 273 uint64_t mstatus; 274 275 uint64_t mip; 276 /* 277 * MIP contains the software writable version of SEIP ORed with the 278 * external interrupt value. The MIP register is always up-to-date. 279 * To keep track of the current source, we also save booleans of the values 280 * here. 281 */ 282 bool external_seip; 283 bool software_seip; 284 285 uint64_t miclaim; 286 287 uint64_t mie; 288 uint64_t mideleg; 289 290 /* 291 * When mideleg[i]=0 and mvien[i]=1, sie[i] is no more 292 * alias of mie[i] and needs to be maintained separately. 293 */ 294 uint64_t sie; 295 296 /* 297 * When hideleg[i]=0 and hvien[i]=1, vsie[i] is no more 298 * alias of sie[i] (mie[i]) and needs to be maintained separately. 299 */ 300 uint64_t vsie; 301 302 target_ulong satp; /* since: priv-1.10.0 */ 303 target_ulong stval; 304 target_ulong medeleg; 305 306 target_ulong stvec; 307 target_ulong sepc; 308 target_ulong scause; 309 310 target_ulong mtvec; 311 target_ulong mepc; 312 target_ulong mcause; 313 target_ulong mtval; /* since: priv-1.10.0 */ 314 315 /* Machine and Supervisor interrupt priorities */ 316 uint8_t miprio[64]; 317 uint8_t siprio[64]; 318 319 /* AIA CSRs */ 320 target_ulong miselect; 321 target_ulong siselect; 322 uint64_t mvien; 323 uint64_t mvip; 324 325 /* Hypervisor CSRs */ 326 target_ulong hstatus; 327 target_ulong hedeleg; 328 uint64_t hideleg; 329 uint32_t hcounteren; 330 target_ulong htval; 331 target_ulong htinst; 332 target_ulong hgatp; 333 target_ulong hgeie; 334 target_ulong hgeip; 335 uint64_t htimedelta; 336 uint64_t hvien; 337 338 /* 339 * Bits VSSIP, VSTIP and VSEIP in hvip are maintained in mip. Other bits 340 * from 0:12 are reserved. Bits 13:63 are not aliased and must be separately 341 * maintain in hvip. 342 */ 343 uint64_t hvip; 344 345 /* Hypervisor controlled virtual interrupt priorities */ 346 target_ulong hvictl; 347 uint8_t hviprio[64]; 348 349 /* Upper 64-bits of 128-bit CSRs */ 350 uint64_t mscratchh; 351 uint64_t sscratchh; 352 353 /* Virtual CSRs */ 354 /* 355 * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. 356 * For RV64 this is a 64-bit vsstatus. 357 */ 358 uint64_t vsstatus; 359 target_ulong vstvec; 360 target_ulong vsscratch; 361 target_ulong vsepc; 362 target_ulong vscause; 363 target_ulong vstval; 364 target_ulong vsatp; 365 366 /* AIA VS-mode CSRs */ 367 target_ulong vsiselect; 368 369 target_ulong mtval2; 370 target_ulong mtinst; 371 372 /* HS Backup CSRs */ 373 target_ulong stvec_hs; 374 target_ulong sscratch_hs; 375 target_ulong sepc_hs; 376 target_ulong scause_hs; 377 target_ulong stval_hs; 378 target_ulong satp_hs; 379 uint64_t mstatus_hs; 380 381 /* 382 * Signals whether the current exception occurred with two-stage address 383 * translation active. 384 */ 385 bool two_stage_lookup; 386 /* 387 * Signals whether the current exception occurred while doing two-stage 388 * address translation for the VS-stage page table walk. 389 */ 390 bool two_stage_indirect_lookup; 391 392 uint32_t scounteren; 393 uint32_t mcounteren; 394 395 uint32_t mcountinhibit; 396 397 /* PMU cycle & instret privilege mode filtering */ 398 target_ulong mcyclecfg; 399 target_ulong mcyclecfgh; 400 target_ulong minstretcfg; 401 target_ulong minstretcfgh; 402 403 /* PMU counter state */ 404 PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS]; 405 406 /* PMU event selector configured values. First three are unused */ 407 target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS]; 408 409 /* PMU event selector configured values for RV32 */ 410 target_ulong mhpmeventh_val[RV_MAX_MHPMEVENTS]; 411 412 PMUFixedCtrState pmu_fixed_ctrs[2]; 413 414 target_ulong sscratch; 415 target_ulong mscratch; 416 417 /* Sstc CSRs */ 418 uint64_t stimecmp; 419 420 uint64_t vstimecmp; 421 422 /* physical memory protection */ 423 pmp_table_t pmp_state; 424 target_ulong mseccfg; 425 426 /* trigger module */ 427 target_ulong trigger_cur; 428 target_ulong tdata1[RV_MAX_TRIGGERS]; 429 target_ulong tdata2[RV_MAX_TRIGGERS]; 430 target_ulong tdata3[RV_MAX_TRIGGERS]; 431 target_ulong mcontext; 432 struct CPUBreakpoint *cpu_breakpoint[RV_MAX_TRIGGERS]; 433 struct CPUWatchpoint *cpu_watchpoint[RV_MAX_TRIGGERS]; 434 QEMUTimer *itrigger_timer[RV_MAX_TRIGGERS]; 435 int64_t last_icount; 436 bool itrigger_enabled; 437 438 /* machine specific rdtime callback */ 439 uint64_t (*rdtime_fn)(void *); 440 void *rdtime_fn_arg; 441 442 /* machine specific AIA ireg read-modify-write callback */ 443 #define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \ 444 ((((__xlen) & 0xff) << 24) | \ 445 (((__vgein) & 0x3f) << 20) | \ 446 (((__virt) & 0x1) << 18) | \ 447 (((__priv) & 0x3) << 16) | \ 448 (__isel & 0xffff)) 449 #define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff) 450 #define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3) 451 #define AIA_IREG_VIRT(__ireg) (((__ireg) >> 18) & 0x1) 452 #define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 20) & 0x3f) 453 #define AIA_IREG_XLEN(__ireg) (((__ireg) >> 24) & 0xff) 454 int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg, 455 target_ulong *val, target_ulong new_val, target_ulong write_mask); 456 void *aia_ireg_rmw_fn_arg[4]; 457 458 /* True if in debugger mode. */ 459 bool debugger; 460 461 uint64_t mstateen[SMSTATEEN_MAX_COUNT]; 462 uint64_t hstateen[SMSTATEEN_MAX_COUNT]; 463 uint64_t sstateen[SMSTATEEN_MAX_COUNT]; 464 uint64_t henvcfg; 465 #endif 466 467 /* Fields from here on are preserved across CPU reset. */ 468 QEMUTimer *stimer; /* Internal timer for S-mode interrupt */ 469 QEMUTimer *vstimer; /* Internal timer for VS-mode interrupt */ 470 bool vstime_irq; 471 472 hwaddr kernel_addr; 473 hwaddr fdt_addr; 474 475 #ifdef CONFIG_KVM 476 /* kvm timer */ 477 bool kvm_timer_dirty; 478 uint64_t kvm_timer_time; 479 uint64_t kvm_timer_compare; 480 uint64_t kvm_timer_state; 481 uint64_t kvm_timer_frequency; 482 #endif /* CONFIG_KVM */ 483 484 /* RNMI */ 485 target_ulong mnscratch; 486 target_ulong mnepc; 487 target_ulong mncause; /* mncause without bit XLEN-1 set to 1 */ 488 target_ulong mnstatus; 489 target_ulong rnmip; 490 uint64_t rnmi_irqvec; 491 uint64_t rnmi_excpvec; 492 }; 493 494 /* 495 * RISCVCPU: 496 * @env: #CPURISCVState 497 * 498 * A RISCV CPU. 499 */ 500 struct ArchCPU { 501 CPUState parent_obj; 502 503 CPURISCVState env; 504 505 GDBFeature dyn_csr_feature; 506 GDBFeature dyn_vreg_feature; 507 508 /* Configuration Settings */ 509 RISCVCPUConfig cfg; 510 511 QEMUTimer *pmu_timer; 512 /* A bitmask of Available programmable counters */ 513 uint32_t pmu_avail_ctrs; 514 /* Mapping of events to counters */ 515 GHashTable *pmu_event_ctr_map; 516 const GPtrArray *decoders; 517 }; 518 519 /** 520 * RISCVCPUClass: 521 * @parent_realize: The parent class' realize handler. 522 * @parent_phases: The parent class' reset phase handlers. 523 * 524 * A RISCV CPU model. 525 */ 526 struct RISCVCPUClass { 527 CPUClass parent_class; 528 529 DeviceRealize parent_realize; 530 ResettablePhases parent_phases; 531 uint32_t misa_mxl_max; /* max mxl for this cpu */ 532 }; 533 534 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) 535 { 536 return (env->misa_ext & ext) != 0; 537 } 538 539 #include "cpu_user.h" 540 541 extern const char * const riscv_int_regnames[]; 542 extern const char * const riscv_int_regnamesh[]; 543 extern const char * const riscv_fpr_regnames[]; 544 545 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); 546 int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 547 int cpuid, DumpState *s); 548 int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 549 int cpuid, DumpState *s); 550 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 551 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 552 int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero); 553 uint8_t riscv_cpu_default_priority(int irq); 554 uint64_t riscv_cpu_all_pending(CPURISCVState *env); 555 int riscv_cpu_mirq_pending(CPURISCVState *env); 556 int riscv_cpu_sirq_pending(CPURISCVState *env); 557 int riscv_cpu_vsirq_pending(CPURISCVState *env); 558 bool riscv_cpu_fp_enabled(CPURISCVState *env); 559 target_ulong riscv_cpu_get_geilen(CPURISCVState *env); 560 void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); 561 bool riscv_cpu_vector_enabled(CPURISCVState *env); 562 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); 563 int riscv_env_mmu_index(CPURISCVState *env, bool ifetch); 564 bool cpu_get_fcfien(CPURISCVState *env); 565 bool cpu_get_bcfien(CPURISCVState *env); 566 G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 567 MMUAccessType access_type, 568 int mmu_idx, uintptr_t retaddr); 569 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 570 MMUAccessType access_type, int mmu_idx, 571 bool probe, uintptr_t retaddr); 572 char *riscv_isa_string(RISCVCPU *cpu); 573 int riscv_cpu_max_xlen(RISCVCPUClass *mcc); 574 bool riscv_cpu_option_set(const char *optname); 575 576 #ifndef CONFIG_USER_ONLY 577 void riscv_cpu_do_interrupt(CPUState *cpu); 578 void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename); 579 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 580 vaddr addr, unsigned size, 581 MMUAccessType access_type, 582 int mmu_idx, MemTxAttrs attrs, 583 MemTxResult response, uintptr_t retaddr); 584 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 585 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); 586 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); 587 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); 588 uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask, 589 uint64_t value); 590 void riscv_cpu_set_rnmi(RISCVCPU *cpu, uint32_t irq, bool level); 591 void riscv_cpu_interrupt(CPURISCVState *env); 592 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ 593 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), 594 void *arg); 595 void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, 596 int (*rmw_fn)(void *arg, 597 target_ulong reg, 598 target_ulong *val, 599 target_ulong new_val, 600 target_ulong write_mask), 601 void *rmw_fn_arg); 602 603 RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit); 604 #endif /* !CONFIG_USER_ONLY */ 605 606 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv, bool virt_en); 607 608 void riscv_translate_init(void); 609 void riscv_translate_code(CPUState *cs, TranslationBlock *tb, 610 int *max_insns, vaddr pc, void *host_pc); 611 612 G_NORETURN void riscv_raise_exception(CPURISCVState *env, 613 RISCVException exception, 614 uintptr_t pc); 615 616 target_ulong riscv_cpu_get_fflags(CPURISCVState *env); 617 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); 618 619 #include "exec/cpu-all.h" 620 621 FIELD(TB_FLAGS, MEM_IDX, 0, 3) 622 FIELD(TB_FLAGS, FS, 3, 2) 623 /* Vector flags */ 624 FIELD(TB_FLAGS, VS, 5, 2) 625 FIELD(TB_FLAGS, LMUL, 7, 3) 626 FIELD(TB_FLAGS, SEW, 10, 3) 627 FIELD(TB_FLAGS, VL_EQ_VLMAX, 13, 1) 628 FIELD(TB_FLAGS, VILL, 14, 1) 629 FIELD(TB_FLAGS, VSTART_EQ_ZERO, 15, 1) 630 /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ 631 FIELD(TB_FLAGS, XL, 16, 2) 632 /* If PointerMasking should be applied */ 633 FIELD(TB_FLAGS, PM_MASK_ENABLED, 18, 1) 634 FIELD(TB_FLAGS, PM_BASE_ENABLED, 19, 1) 635 FIELD(TB_FLAGS, VTA, 18, 1) 636 FIELD(TB_FLAGS, VMA, 19, 1) 637 /* Native debug itrigger */ 638 FIELD(TB_FLAGS, ITRIGGER, 20, 1) 639 /* Virtual mode enabled */ 640 FIELD(TB_FLAGS, VIRT_ENABLED, 21, 1) 641 FIELD(TB_FLAGS, PRIV, 22, 2) 642 FIELD(TB_FLAGS, AXL, 24, 2) 643 /* zicfilp needs a TB flag to track indirect branches */ 644 FIELD(TB_FLAGS, FCFI_ENABLED, 26, 1) 645 FIELD(TB_FLAGS, FCFI_LP_EXPECTED, 27, 1) 646 /* zicfiss needs a TB flag so that correct TB is located based on tb flags */ 647 FIELD(TB_FLAGS, BCFI_ENABLED, 28, 1) 648 /* If pointer masking should be applied and address sign extended */ 649 FIELD(TB_FLAGS, PM_PMM, 29, 2) 650 FIELD(TB_FLAGS, PM_SIGNEXTEND, 31, 1) 651 652 #ifdef TARGET_RISCV32 653 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) 654 #else 655 static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) 656 { 657 return env->misa_mxl; 658 } 659 #endif 660 #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env))) 661 662 static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURISCVState *env) 663 { 664 return &env_archcpu(env)->cfg; 665 } 666 667 #if !defined(CONFIG_USER_ONLY) 668 static inline int cpu_address_mode(CPURISCVState *env) 669 { 670 int mode = env->priv; 671 672 if (mode == PRV_M && get_field(env->mstatus, MSTATUS_MPRV)) { 673 mode = get_field(env->mstatus, MSTATUS_MPP); 674 } 675 return mode; 676 } 677 678 static inline RISCVMXL cpu_get_xl(CPURISCVState *env, target_ulong mode) 679 { 680 RISCVMXL xl = env->misa_mxl; 681 /* 682 * When emulating a 32-bit-only cpu, use RV32. 683 * When emulating a 64-bit cpu, and MXL has been reduced to RV32, 684 * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened 685 * back to RV64 for lower privs. 686 */ 687 if (xl != MXL_RV32) { 688 switch (mode) { 689 case PRV_M: 690 break; 691 case PRV_U: 692 xl = get_field(env->mstatus, MSTATUS64_UXL); 693 break; 694 default: /* PRV_S */ 695 xl = get_field(env->mstatus, MSTATUS64_SXL); 696 break; 697 } 698 } 699 return xl; 700 } 701 #endif 702 703 #if defined(TARGET_RISCV32) 704 #define cpu_recompute_xl(env) ((void)(env), MXL_RV32) 705 #else 706 static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) 707 { 708 #if !defined(CONFIG_USER_ONLY) 709 return cpu_get_xl(env, env->priv); 710 #else 711 return env->misa_mxl; 712 #endif 713 } 714 #endif 715 716 #if defined(TARGET_RISCV32) 717 #define cpu_address_xl(env) ((void)(env), MXL_RV32) 718 #else 719 static inline RISCVMXL cpu_address_xl(CPURISCVState *env) 720 { 721 #ifdef CONFIG_USER_ONLY 722 return env->xl; 723 #else 724 int mode = cpu_address_mode(env); 725 726 return cpu_get_xl(env, mode); 727 #endif 728 } 729 #endif 730 731 static inline int riscv_cpu_xlen(CPURISCVState *env) 732 { 733 return 16 << env->xl; 734 } 735 736 #ifdef TARGET_RISCV32 737 #define riscv_cpu_sxl(env) ((void)(env), MXL_RV32) 738 #else 739 static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env) 740 { 741 #ifdef CONFIG_USER_ONLY 742 return env->misa_mxl; 743 #else 744 if (env->misa_mxl != MXL_RV32) { 745 return get_field(env->mstatus, MSTATUS64_SXL); 746 } 747 #endif 748 return MXL_RV32; 749 } 750 #endif 751 752 /* 753 * Encode LMUL to lmul as follows: 754 * LMUL vlmul lmul 755 * 1 000 0 756 * 2 001 1 757 * 4 010 2 758 * 8 011 3 759 * - 100 - 760 * 1/8 101 -3 761 * 1/4 110 -2 762 * 1/2 111 -1 763 * 764 * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul) 765 * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8 766 * => VLMAX = vlen >> (1 + 3 - (-3)) 767 * = 256 >> 7 768 * = 2 769 */ 770 static inline uint32_t vext_get_vlmax(uint32_t vlenb, uint32_t vsew, 771 int8_t lmul) 772 { 773 uint32_t vlen = vlenb << 3; 774 775 /* 776 * We need to use 'vlen' instead of 'vlenb' to 777 * preserve the '+ 3' in the formula. Otherwise 778 * we risk a negative shift if vsew < lmul. 779 */ 780 return vlen >> (vsew + 3 - lmul); 781 } 782 783 void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, 784 uint64_t *cs_base, uint32_t *pflags); 785 786 bool riscv_cpu_is_32bit(RISCVCPU *cpu); 787 788 bool riscv_cpu_virt_mem_enabled(CPURISCVState *env); 789 RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env); 790 RISCVPmPmm riscv_pm_get_virt_pmm(CPURISCVState *env); 791 uint32_t riscv_pm_get_pmlen(RISCVPmPmm pmm); 792 793 RISCVException riscv_csrr(CPURISCVState *env, int csrno, 794 target_ulong *ret_value); 795 796 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, 797 target_ulong *ret_value, 798 target_ulong new_value, target_ulong write_mask); 799 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, 800 target_ulong *ret_value, 801 target_ulong new_value, 802 target_ulong write_mask); 803 804 static inline void riscv_csr_write(CPURISCVState *env, int csrno, 805 target_ulong val) 806 { 807 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); 808 } 809 810 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) 811 { 812 target_ulong val = 0; 813 riscv_csrrw(env, csrno, &val, 0, 0); 814 return val; 815 } 816 817 typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, 818 int csrno); 819 typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, 820 target_ulong *ret_value); 821 typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, 822 target_ulong new_value); 823 typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, 824 target_ulong *ret_value, 825 target_ulong new_value, 826 target_ulong write_mask); 827 828 RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno, 829 Int128 *ret_value); 830 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, 831 Int128 *ret_value, 832 Int128 new_value, Int128 write_mask); 833 834 typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno, 835 Int128 *ret_value); 836 typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int csrno, 837 Int128 new_value); 838 839 typedef struct { 840 const char *name; 841 riscv_csr_predicate_fn predicate; 842 riscv_csr_read_fn read; 843 riscv_csr_write_fn write; 844 riscv_csr_op_fn op; 845 riscv_csr_read128_fn read128; 846 riscv_csr_write128_fn write128; 847 /* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0) */ 848 uint32_t min_priv_ver; 849 } riscv_csr_operations; 850 851 /* CSR function table constants */ 852 enum { 853 CSR_TABLE_SIZE = 0x1000 854 }; 855 856 /* 857 * The event id are encoded based on the encoding specified in the 858 * SBI specification v0.3 859 */ 860 861 enum riscv_pmu_event_idx { 862 RISCV_PMU_EVENT_HW_CPU_CYCLES = 0x01, 863 RISCV_PMU_EVENT_HW_INSTRUCTIONS = 0x02, 864 RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS = 0x10019, 865 RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS = 0x1001B, 866 RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS = 0x10021, 867 }; 868 869 /* used by tcg/tcg-cpu.c*/ 870 void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en); 871 bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset); 872 void riscv_cpu_set_misa_ext(CPURISCVState *env, uint32_t ext); 873 bool riscv_cpu_is_vendor(Object *cpu_obj); 874 875 typedef struct RISCVCPUMultiExtConfig { 876 const char *name; 877 uint32_t offset; 878 bool enabled; 879 } RISCVCPUMultiExtConfig; 880 881 extern const RISCVCPUMultiExtConfig riscv_cpu_extensions[]; 882 extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[]; 883 extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[]; 884 extern const RISCVCPUMultiExtConfig riscv_cpu_named_features[]; 885 extern const RISCVCPUMultiExtConfig riscv_cpu_deprecated_exts[]; 886 887 typedef struct isa_ext_data { 888 const char *name; 889 int min_version; 890 int ext_enable_offset; 891 } RISCVIsaExtData; 892 extern const RISCVIsaExtData isa_edata_arr[]; 893 char *riscv_cpu_get_name(RISCVCPU *cpu); 894 895 void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp); 896 void riscv_add_satp_mode_properties(Object *obj); 897 bool riscv_cpu_accelerator_compatible(RISCVCPU *cpu); 898 899 /* CSR function table */ 900 extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; 901 902 extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[]; 903 904 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); 905 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); 906 907 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); 908 909 target_ulong riscv_new_csr_seed(target_ulong new_value, 910 target_ulong write_mask); 911 912 uint8_t satp_mode_max_from_map(uint32_t map); 913 const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); 914 915 /* Implemented in th_csr.c */ 916 void th_register_custom_csrs(RISCVCPU *cpu); 917 918 const char *priv_spec_to_str(int priv_version); 919 #endif /* RISCV_CPU_H */ 920