1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef RISCV_CPU_H 21 #define RISCV_CPU_H 22 23 #include "hw/core/cpu.h" 24 #include "hw/registerfields.h" 25 #include "hw/qdev-properties.h" 26 #include "exec/cpu-defs.h" 27 #include "qemu/cpu-float.h" 28 #include "qom/object.h" 29 #include "qemu/int128.h" 30 #include "cpu_bits.h" 31 #include "cpu_cfg.h" 32 #include "qapi/qapi-types-common.h" 33 #include "cpu-qom.h" 34 35 typedef struct CPUArchState CPURISCVState; 36 37 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU 38 39 #if defined(TARGET_RISCV32) 40 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 41 #elif defined(TARGET_RISCV64) 42 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 43 #endif 44 45 #define TCG_GUEST_DEFAULT_MO 0 46 47 /* 48 * RISC-V-specific extra insn start words: 49 * 1: Original instruction opcode 50 */ 51 #define TARGET_INSN_START_EXTRA_WORDS 1 52 53 #define RV(x) ((target_ulong)1 << (x - 'A')) 54 55 /* 56 * Update misa_bits[], misa_ext_info_arr[] and misa_ext_cfgs[] 57 * when adding new MISA bits here. 58 */ 59 #define RVI RV('I') 60 #define RVE RV('E') /* E and I are mutually exclusive */ 61 #define RVM RV('M') 62 #define RVA RV('A') 63 #define RVF RV('F') 64 #define RVD RV('D') 65 #define RVV RV('V') 66 #define RVC RV('C') 67 #define RVS RV('S') 68 #define RVU RV('U') 69 #define RVH RV('H') 70 #define RVJ RV('J') 71 #define RVG RV('G') 72 #define RVB RV('B') 73 74 extern const uint32_t misa_bits[]; 75 const char *riscv_get_misa_ext_name(uint32_t bit); 76 const char *riscv_get_misa_ext_description(uint32_t bit); 77 78 #define CPU_CFG_OFFSET(_prop) offsetof(struct RISCVCPUConfig, _prop) 79 80 typedef struct riscv_cpu_profile { 81 struct riscv_cpu_profile *parent; 82 const char *name; 83 uint32_t misa_ext; 84 bool enabled; 85 bool user_set; 86 int priv_spec; 87 int satp_mode; 88 const int32_t ext_offsets[]; 89 } RISCVCPUProfile; 90 91 #define RISCV_PROFILE_EXT_LIST_END -1 92 #define RISCV_PROFILE_ATTR_UNUSED -1 93 94 extern RISCVCPUProfile *riscv_profiles[]; 95 96 /* Privileged specification version */ 97 #define PRIV_VER_1_10_0_STR "v1.10.0" 98 #define PRIV_VER_1_11_0_STR "v1.11.0" 99 #define PRIV_VER_1_12_0_STR "v1.12.0" 100 enum { 101 PRIV_VERSION_1_10_0 = 0, 102 PRIV_VERSION_1_11_0, 103 PRIV_VERSION_1_12_0, 104 105 PRIV_VERSION_LATEST = PRIV_VERSION_1_12_0, 106 }; 107 108 #define VEXT_VERSION_1_00_0 0x00010000 109 #define VEXT_VER_1_00_0_STR "v1.0" 110 111 enum { 112 TRANSLATE_SUCCESS, 113 TRANSLATE_FAIL, 114 TRANSLATE_PMP_FAIL, 115 TRANSLATE_G_STAGE_FAIL 116 }; 117 118 /* Extension context status */ 119 typedef enum { 120 EXT_STATUS_DISABLED = 0, 121 EXT_STATUS_INITIAL, 122 EXT_STATUS_CLEAN, 123 EXT_STATUS_DIRTY, 124 } RISCVExtStatus; 125 126 #define MMU_USER_IDX 3 127 128 #define MAX_RISCV_PMPS (16) 129 130 #if !defined(CONFIG_USER_ONLY) 131 #include "pmp.h" 132 #include "debug.h" 133 #endif 134 135 #define RV_VLEN_MAX 1024 136 #define RV_MAX_MHPMEVENTS 32 137 #define RV_MAX_MHPMCOUNTERS 32 138 139 FIELD(VTYPE, VLMUL, 0, 3) 140 FIELD(VTYPE, VSEW, 3, 3) 141 FIELD(VTYPE, VTA, 6, 1) 142 FIELD(VTYPE, VMA, 7, 1) 143 FIELD(VTYPE, VEDIV, 8, 2) 144 FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) 145 146 typedef struct PMUCTRState { 147 /* Current value of a counter */ 148 target_ulong mhpmcounter_val; 149 /* Current value of a counter in RV32 */ 150 target_ulong mhpmcounterh_val; 151 /* Snapshot values of counter */ 152 target_ulong mhpmcounter_prev; 153 /* Snapshort value of a counter in RV32 */ 154 target_ulong mhpmcounterh_prev; 155 bool started; 156 /* Value beyond UINT32_MAX/UINT64_MAX before overflow interrupt trigger */ 157 target_ulong irq_overflow_left; 158 } PMUCTRState; 159 160 struct CPUArchState { 161 target_ulong gpr[32]; 162 target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ 163 164 /* vector coprocessor state. */ 165 uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); 166 target_ulong vxrm; 167 target_ulong vxsat; 168 target_ulong vl; 169 target_ulong vstart; 170 target_ulong vtype; 171 bool vill; 172 173 target_ulong pc; 174 target_ulong load_res; 175 target_ulong load_val; 176 177 /* Floating-Point state */ 178 uint64_t fpr[32]; /* assume both F and D extensions */ 179 target_ulong frm; 180 float_status fp_status; 181 182 target_ulong badaddr; 183 target_ulong bins; 184 185 target_ulong guest_phys_fault_addr; 186 187 target_ulong priv_ver; 188 target_ulong vext_ver; 189 190 /* RISCVMXL, but uint32_t for vmstate migration */ 191 uint32_t misa_mxl; /* current mxl */ 192 uint32_t misa_mxl_max; /* max mxl for this cpu */ 193 uint32_t misa_ext; /* current extensions */ 194 uint32_t misa_ext_mask; /* max ext for this cpu */ 195 uint32_t xl; /* current xlen */ 196 197 /* 128-bit helpers upper part return value */ 198 target_ulong retxh; 199 200 target_ulong jvt; 201 202 #ifdef CONFIG_USER_ONLY 203 uint32_t elf_flags; 204 #endif 205 206 #ifndef CONFIG_USER_ONLY 207 target_ulong priv; 208 /* This contains QEMU specific information about the virt state. */ 209 bool virt_enabled; 210 target_ulong geilen; 211 uint64_t resetvec; 212 213 target_ulong mhartid; 214 /* 215 * For RV32 this is 32-bit mstatus and 32-bit mstatush. 216 * For RV64 this is a 64-bit mstatus. 217 */ 218 uint64_t mstatus; 219 220 uint64_t mip; 221 /* 222 * MIP contains the software writable version of SEIP ORed with the 223 * external interrupt value. The MIP register is always up-to-date. 224 * To keep track of the current source, we also save booleans of the values 225 * here. 226 */ 227 bool external_seip; 228 bool software_seip; 229 230 uint64_t miclaim; 231 232 uint64_t mie; 233 uint64_t mideleg; 234 235 /* 236 * When mideleg[i]=0 and mvien[i]=1, sie[i] is no more 237 * alias of mie[i] and needs to be maintained separately. 238 */ 239 uint64_t sie; 240 241 /* 242 * When hideleg[i]=0 and hvien[i]=1, vsie[i] is no more 243 * alias of sie[i] (mie[i]) and needs to be maintained separately. 244 */ 245 uint64_t vsie; 246 247 target_ulong satp; /* since: priv-1.10.0 */ 248 target_ulong stval; 249 target_ulong medeleg; 250 251 target_ulong stvec; 252 target_ulong sepc; 253 target_ulong scause; 254 255 target_ulong mtvec; 256 target_ulong mepc; 257 target_ulong mcause; 258 target_ulong mtval; /* since: priv-1.10.0 */ 259 260 /* Machine and Supervisor interrupt priorities */ 261 uint8_t miprio[64]; 262 uint8_t siprio[64]; 263 264 /* AIA CSRs */ 265 target_ulong miselect; 266 target_ulong siselect; 267 uint64_t mvien; 268 uint64_t mvip; 269 270 /* Hypervisor CSRs */ 271 target_ulong hstatus; 272 target_ulong hedeleg; 273 uint64_t hideleg; 274 target_ulong hcounteren; 275 target_ulong htval; 276 target_ulong htinst; 277 target_ulong hgatp; 278 target_ulong hgeie; 279 target_ulong hgeip; 280 uint64_t htimedelta; 281 uint64_t hvien; 282 283 /* 284 * Bits VSSIP, VSTIP and VSEIP in hvip are maintained in mip. Other bits 285 * from 0:12 are reserved. Bits 13:63 are not aliased and must be separately 286 * maintain in hvip. 287 */ 288 uint64_t hvip; 289 290 /* Hypervisor controlled virtual interrupt priorities */ 291 target_ulong hvictl; 292 uint8_t hviprio[64]; 293 294 /* Upper 64-bits of 128-bit CSRs */ 295 uint64_t mscratchh; 296 uint64_t sscratchh; 297 298 /* Virtual CSRs */ 299 /* 300 * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. 301 * For RV64 this is a 64-bit vsstatus. 302 */ 303 uint64_t vsstatus; 304 target_ulong vstvec; 305 target_ulong vsscratch; 306 target_ulong vsepc; 307 target_ulong vscause; 308 target_ulong vstval; 309 target_ulong vsatp; 310 311 /* AIA VS-mode CSRs */ 312 target_ulong vsiselect; 313 314 target_ulong mtval2; 315 target_ulong mtinst; 316 317 /* HS Backup CSRs */ 318 target_ulong stvec_hs; 319 target_ulong sscratch_hs; 320 target_ulong sepc_hs; 321 target_ulong scause_hs; 322 target_ulong stval_hs; 323 target_ulong satp_hs; 324 uint64_t mstatus_hs; 325 326 /* 327 * Signals whether the current exception occurred with two-stage address 328 * translation active. 329 */ 330 bool two_stage_lookup; 331 /* 332 * Signals whether the current exception occurred while doing two-stage 333 * address translation for the VS-stage page table walk. 334 */ 335 bool two_stage_indirect_lookup; 336 337 target_ulong scounteren; 338 target_ulong mcounteren; 339 340 target_ulong mcountinhibit; 341 342 /* PMU counter state */ 343 PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS]; 344 345 /* PMU event selector configured values. First three are unused */ 346 target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS]; 347 348 /* PMU event selector configured values for RV32 */ 349 target_ulong mhpmeventh_val[RV_MAX_MHPMEVENTS]; 350 351 target_ulong sscratch; 352 target_ulong mscratch; 353 354 /* Sstc CSRs */ 355 uint64_t stimecmp; 356 357 uint64_t vstimecmp; 358 359 /* physical memory protection */ 360 pmp_table_t pmp_state; 361 target_ulong mseccfg; 362 363 /* trigger module */ 364 target_ulong trigger_cur; 365 target_ulong tdata1[RV_MAX_TRIGGERS]; 366 target_ulong tdata2[RV_MAX_TRIGGERS]; 367 target_ulong tdata3[RV_MAX_TRIGGERS]; 368 struct CPUBreakpoint *cpu_breakpoint[RV_MAX_TRIGGERS]; 369 struct CPUWatchpoint *cpu_watchpoint[RV_MAX_TRIGGERS]; 370 QEMUTimer *itrigger_timer[RV_MAX_TRIGGERS]; 371 int64_t last_icount; 372 bool itrigger_enabled; 373 374 /* machine specific rdtime callback */ 375 uint64_t (*rdtime_fn)(void *); 376 void *rdtime_fn_arg; 377 378 /* machine specific AIA ireg read-modify-write callback */ 379 #define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \ 380 ((((__xlen) & 0xff) << 24) | \ 381 (((__vgein) & 0x3f) << 20) | \ 382 (((__virt) & 0x1) << 18) | \ 383 (((__priv) & 0x3) << 16) | \ 384 (__isel & 0xffff)) 385 #define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff) 386 #define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3) 387 #define AIA_IREG_VIRT(__ireg) (((__ireg) >> 18) & 0x1) 388 #define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 20) & 0x3f) 389 #define AIA_IREG_XLEN(__ireg) (((__ireg) >> 24) & 0xff) 390 int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg, 391 target_ulong *val, target_ulong new_val, target_ulong write_mask); 392 void *aia_ireg_rmw_fn_arg[4]; 393 394 /* True if in debugger mode. */ 395 bool debugger; 396 397 /* 398 * CSRs for PointerMasking extension 399 */ 400 target_ulong mmte; 401 target_ulong mpmmask; 402 target_ulong mpmbase; 403 target_ulong spmmask; 404 target_ulong spmbase; 405 target_ulong upmmask; 406 target_ulong upmbase; 407 408 /* CSRs for execution environment configuration */ 409 uint64_t menvcfg; 410 uint64_t mstateen[SMSTATEEN_MAX_COUNT]; 411 uint64_t hstateen[SMSTATEEN_MAX_COUNT]; 412 uint64_t sstateen[SMSTATEEN_MAX_COUNT]; 413 target_ulong senvcfg; 414 uint64_t henvcfg; 415 #endif 416 target_ulong cur_pmmask; 417 target_ulong cur_pmbase; 418 419 /* Fields from here on are preserved across CPU reset. */ 420 QEMUTimer *stimer; /* Internal timer for S-mode interrupt */ 421 QEMUTimer *vstimer; /* Internal timer for VS-mode interrupt */ 422 bool vstime_irq; 423 424 hwaddr kernel_addr; 425 hwaddr fdt_addr; 426 427 #ifdef CONFIG_KVM 428 /* kvm timer */ 429 bool kvm_timer_dirty; 430 uint64_t kvm_timer_time; 431 uint64_t kvm_timer_compare; 432 uint64_t kvm_timer_state; 433 uint64_t kvm_timer_frequency; 434 #endif /* CONFIG_KVM */ 435 }; 436 437 /* 438 * RISCVCPU: 439 * @env: #CPURISCVState 440 * 441 * A RISCV CPU. 442 */ 443 struct ArchCPU { 444 CPUState parent_obj; 445 446 CPURISCVState env; 447 448 char *dyn_csr_xml; 449 char *dyn_vreg_xml; 450 451 /* Configuration Settings */ 452 RISCVCPUConfig cfg; 453 454 QEMUTimer *pmu_timer; 455 /* A bitmask of Available programmable counters */ 456 uint32_t pmu_avail_ctrs; 457 /* Mapping of events to counters */ 458 GHashTable *pmu_event_ctr_map; 459 }; 460 461 /** 462 * RISCVCPUClass: 463 * @parent_realize: The parent class' realize handler. 464 * @parent_phases: The parent class' reset phase handlers. 465 * 466 * A RISCV CPU model. 467 */ 468 struct RISCVCPUClass { 469 CPUClass parent_class; 470 471 DeviceRealize parent_realize; 472 ResettablePhases parent_phases; 473 }; 474 475 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) 476 { 477 return (env->misa_ext & ext) != 0; 478 } 479 480 #include "cpu_user.h" 481 482 extern const char * const riscv_int_regnames[]; 483 extern const char * const riscv_int_regnamesh[]; 484 extern const char * const riscv_fpr_regnames[]; 485 486 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); 487 void riscv_cpu_do_interrupt(CPUState *cpu); 488 int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 489 int cpuid, DumpState *s); 490 int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 491 int cpuid, DumpState *s); 492 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 493 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 494 int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero); 495 uint8_t riscv_cpu_default_priority(int irq); 496 uint64_t riscv_cpu_all_pending(CPURISCVState *env); 497 int riscv_cpu_mirq_pending(CPURISCVState *env); 498 int riscv_cpu_sirq_pending(CPURISCVState *env); 499 int riscv_cpu_vsirq_pending(CPURISCVState *env); 500 bool riscv_cpu_fp_enabled(CPURISCVState *env); 501 target_ulong riscv_cpu_get_geilen(CPURISCVState *env); 502 void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); 503 bool riscv_cpu_vector_enabled(CPURISCVState *env); 504 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); 505 int riscv_env_mmu_index(CPURISCVState *env, bool ifetch); 506 G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 507 MMUAccessType access_type, 508 int mmu_idx, uintptr_t retaddr); 509 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 510 MMUAccessType access_type, int mmu_idx, 511 bool probe, uintptr_t retaddr); 512 char *riscv_isa_string(RISCVCPU *cpu); 513 bool riscv_cpu_option_set(const char *optname); 514 515 #ifndef CONFIG_USER_ONLY 516 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 517 vaddr addr, unsigned size, 518 MMUAccessType access_type, 519 int mmu_idx, MemTxAttrs attrs, 520 MemTxResult response, uintptr_t retaddr); 521 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 522 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); 523 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); 524 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); 525 uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask, 526 uint64_t value); 527 void riscv_cpu_interrupt(CPURISCVState *env); 528 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ 529 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), 530 void *arg); 531 void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, 532 int (*rmw_fn)(void *arg, 533 target_ulong reg, 534 target_ulong *val, 535 target_ulong new_val, 536 target_ulong write_mask), 537 void *rmw_fn_arg); 538 539 RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit); 540 #endif 541 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); 542 543 void riscv_translate_init(void); 544 G_NORETURN void riscv_raise_exception(CPURISCVState *env, 545 uint32_t exception, uintptr_t pc); 546 547 target_ulong riscv_cpu_get_fflags(CPURISCVState *env); 548 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); 549 550 #include "exec/cpu-all.h" 551 552 FIELD(TB_FLAGS, MEM_IDX, 0, 3) 553 FIELD(TB_FLAGS, FS, 3, 2) 554 /* Vector flags */ 555 FIELD(TB_FLAGS, VS, 5, 2) 556 FIELD(TB_FLAGS, LMUL, 7, 3) 557 FIELD(TB_FLAGS, SEW, 10, 3) 558 FIELD(TB_FLAGS, VL_EQ_VLMAX, 13, 1) 559 FIELD(TB_FLAGS, VILL, 14, 1) 560 FIELD(TB_FLAGS, VSTART_EQ_ZERO, 15, 1) 561 /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ 562 FIELD(TB_FLAGS, XL, 16, 2) 563 /* If PointerMasking should be applied */ 564 FIELD(TB_FLAGS, PM_MASK_ENABLED, 18, 1) 565 FIELD(TB_FLAGS, PM_BASE_ENABLED, 19, 1) 566 FIELD(TB_FLAGS, VTA, 20, 1) 567 FIELD(TB_FLAGS, VMA, 21, 1) 568 /* Native debug itrigger */ 569 FIELD(TB_FLAGS, ITRIGGER, 22, 1) 570 /* Virtual mode enabled */ 571 FIELD(TB_FLAGS, VIRT_ENABLED, 23, 1) 572 FIELD(TB_FLAGS, PRIV, 24, 2) 573 FIELD(TB_FLAGS, AXL, 26, 2) 574 575 #ifdef TARGET_RISCV32 576 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) 577 #else 578 static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) 579 { 580 return env->misa_mxl; 581 } 582 #endif 583 #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env))) 584 585 static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURISCVState *env) 586 { 587 return &env_archcpu(env)->cfg; 588 } 589 590 #if !defined(CONFIG_USER_ONLY) 591 static inline int cpu_address_mode(CPURISCVState *env) 592 { 593 int mode = env->priv; 594 595 if (mode == PRV_M && get_field(env->mstatus, MSTATUS_MPRV)) { 596 mode = get_field(env->mstatus, MSTATUS_MPP); 597 } 598 return mode; 599 } 600 601 static inline RISCVMXL cpu_get_xl(CPURISCVState *env, target_ulong mode) 602 { 603 RISCVMXL xl = env->misa_mxl; 604 /* 605 * When emulating a 32-bit-only cpu, use RV32. 606 * When emulating a 64-bit cpu, and MXL has been reduced to RV32, 607 * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened 608 * back to RV64 for lower privs. 609 */ 610 if (xl != MXL_RV32) { 611 switch (mode) { 612 case PRV_M: 613 break; 614 case PRV_U: 615 xl = get_field(env->mstatus, MSTATUS64_UXL); 616 break; 617 default: /* PRV_S */ 618 xl = get_field(env->mstatus, MSTATUS64_SXL); 619 break; 620 } 621 } 622 return xl; 623 } 624 #endif 625 626 #if defined(TARGET_RISCV32) 627 #define cpu_recompute_xl(env) ((void)(env), MXL_RV32) 628 #else 629 static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) 630 { 631 #if !defined(CONFIG_USER_ONLY) 632 return cpu_get_xl(env, env->priv); 633 #else 634 return env->misa_mxl; 635 #endif 636 } 637 #endif 638 639 #if defined(TARGET_RISCV32) 640 #define cpu_address_xl(env) ((void)(env), MXL_RV32) 641 #else 642 static inline RISCVMXL cpu_address_xl(CPURISCVState *env) 643 { 644 #ifdef CONFIG_USER_ONLY 645 return env->xl; 646 #else 647 int mode = cpu_address_mode(env); 648 649 return cpu_get_xl(env, mode); 650 #endif 651 } 652 #endif 653 654 static inline int riscv_cpu_xlen(CPURISCVState *env) 655 { 656 return 16 << env->xl; 657 } 658 659 #ifdef TARGET_RISCV32 660 #define riscv_cpu_sxl(env) ((void)(env), MXL_RV32) 661 #else 662 static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env) 663 { 664 #ifdef CONFIG_USER_ONLY 665 return env->misa_mxl; 666 #else 667 return get_field(env->mstatus, MSTATUS64_SXL); 668 #endif 669 } 670 #endif 671 672 /* 673 * Encode LMUL to lmul as follows: 674 * LMUL vlmul lmul 675 * 1 000 0 676 * 2 001 1 677 * 4 010 2 678 * 8 011 3 679 * - 100 - 680 * 1/8 101 -3 681 * 1/4 110 -2 682 * 1/2 111 -1 683 * 684 * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul) 685 * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8 686 * => VLMAX = vlen >> (1 + 3 - (-3)) 687 * = 256 >> 7 688 * = 2 689 */ 690 static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) 691 { 692 uint8_t sew = FIELD_EX64(vtype, VTYPE, VSEW); 693 int8_t lmul = sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3); 694 return cpu->cfg.vlen >> (sew + 3 - lmul); 695 } 696 697 void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, 698 uint64_t *cs_base, uint32_t *pflags); 699 700 void riscv_cpu_update_mask(CPURISCVState *env); 701 bool riscv_cpu_is_32bit(RISCVCPU *cpu); 702 703 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, 704 target_ulong *ret_value, 705 target_ulong new_value, target_ulong write_mask); 706 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, 707 target_ulong *ret_value, 708 target_ulong new_value, 709 target_ulong write_mask); 710 711 static inline void riscv_csr_write(CPURISCVState *env, int csrno, 712 target_ulong val) 713 { 714 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); 715 } 716 717 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) 718 { 719 target_ulong val = 0; 720 riscv_csrrw(env, csrno, &val, 0, 0); 721 return val; 722 } 723 724 typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, 725 int csrno); 726 typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, 727 target_ulong *ret_value); 728 typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, 729 target_ulong new_value); 730 typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, 731 target_ulong *ret_value, 732 target_ulong new_value, 733 target_ulong write_mask); 734 735 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, 736 Int128 *ret_value, 737 Int128 new_value, Int128 write_mask); 738 739 typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno, 740 Int128 *ret_value); 741 typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int csrno, 742 Int128 new_value); 743 744 typedef struct { 745 const char *name; 746 riscv_csr_predicate_fn predicate; 747 riscv_csr_read_fn read; 748 riscv_csr_write_fn write; 749 riscv_csr_op_fn op; 750 riscv_csr_read128_fn read128; 751 riscv_csr_write128_fn write128; 752 /* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0) */ 753 uint32_t min_priv_ver; 754 } riscv_csr_operations; 755 756 /* CSR function table constants */ 757 enum { 758 CSR_TABLE_SIZE = 0x1000 759 }; 760 761 /* 762 * The event id are encoded based on the encoding specified in the 763 * SBI specification v0.3 764 */ 765 766 enum riscv_pmu_event_idx { 767 RISCV_PMU_EVENT_HW_CPU_CYCLES = 0x01, 768 RISCV_PMU_EVENT_HW_INSTRUCTIONS = 0x02, 769 RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS = 0x10019, 770 RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS = 0x1001B, 771 RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS = 0x10021, 772 }; 773 774 /* used by tcg/tcg-cpu.c*/ 775 void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en); 776 bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset); 777 void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext); 778 bool riscv_cpu_is_vendor(Object *cpu_obj); 779 780 typedef struct RISCVCPUMultiExtConfig { 781 const char *name; 782 uint32_t offset; 783 bool enabled; 784 } RISCVCPUMultiExtConfig; 785 786 extern const RISCVCPUMultiExtConfig riscv_cpu_extensions[]; 787 extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[]; 788 extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[]; 789 extern const RISCVCPUMultiExtConfig riscv_cpu_named_features[]; 790 extern const RISCVCPUMultiExtConfig riscv_cpu_deprecated_exts[]; 791 extern Property riscv_cpu_options[]; 792 793 typedef struct isa_ext_data { 794 const char *name; 795 int min_version; 796 int ext_enable_offset; 797 } RISCVIsaExtData; 798 extern const RISCVIsaExtData isa_edata_arr[]; 799 char *riscv_cpu_get_name(RISCVCPU *cpu); 800 801 void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp); 802 void riscv_add_satp_mode_properties(Object *obj); 803 bool riscv_cpu_accelerator_compatible(RISCVCPU *cpu); 804 805 /* CSR function table */ 806 extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; 807 808 extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[]; 809 810 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); 811 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); 812 813 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); 814 815 uint8_t satp_mode_max_from_map(uint32_t map); 816 const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); 817 818 #endif /* RISCV_CPU_H */ 819