1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef RISCV_CPU_H 21 #define RISCV_CPU_H 22 23 #include "hw/core/cpu.h" 24 #include "hw/registerfields.h" 25 #include "exec/cpu-defs.h" 26 #include "qemu/cpu-float.h" 27 #include "qom/object.h" 28 #include "qemu/int128.h" 29 #include "cpu_bits.h" 30 31 #define TCG_GUEST_DEFAULT_MO 0 32 33 /* 34 * RISC-V-specific extra insn start words: 35 * 1: Original instruction opcode 36 */ 37 #define TARGET_INSN_START_EXTRA_WORDS 1 38 39 #define TYPE_RISCV_CPU "riscv-cpu" 40 41 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU 42 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) 43 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU 44 45 #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") 46 #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") 47 #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") 48 #define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128") 49 #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") 50 #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") 51 #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") 52 #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") 53 #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") 54 #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") 55 #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") 56 #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") 57 58 #if defined(TARGET_RISCV32) 59 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 60 #elif defined(TARGET_RISCV64) 61 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 62 #endif 63 64 #define RV(x) ((target_ulong)1 << (x - 'A')) 65 66 #define RVI RV('I') 67 #define RVE RV('E') /* E and I are mutually exclusive */ 68 #define RVM RV('M') 69 #define RVA RV('A') 70 #define RVF RV('F') 71 #define RVD RV('D') 72 #define RVV RV('V') 73 #define RVC RV('C') 74 #define RVS RV('S') 75 #define RVU RV('U') 76 #define RVH RV('H') 77 #define RVJ RV('J') 78 79 /* S extension denotes that Supervisor mode exists, however it is possible 80 to have a core that support S mode but does not have an MMU and there 81 is currently no bit in misa to indicate whether an MMU exists or not 82 so a cpu features bitfield is required, likewise for optional PMP support */ 83 enum { 84 RISCV_FEATURE_MMU, 85 RISCV_FEATURE_PMP, 86 RISCV_FEATURE_EPMP, 87 RISCV_FEATURE_MISA, 88 RISCV_FEATURE_AIA, 89 RISCV_FEATURE_DEBUG 90 }; 91 92 /* Privileged specification version */ 93 enum { 94 PRIV_VERSION_1_10_0 = 0, 95 PRIV_VERSION_1_11_0, 96 PRIV_VERSION_1_12_0, 97 }; 98 99 #define VEXT_VERSION_1_00_0 0x00010000 100 101 enum { 102 TRANSLATE_SUCCESS, 103 TRANSLATE_FAIL, 104 TRANSLATE_PMP_FAIL, 105 TRANSLATE_G_STAGE_FAIL 106 }; 107 108 #define MMU_USER_IDX 3 109 110 #define MAX_RISCV_PMPS (16) 111 112 typedef struct CPUArchState CPURISCVState; 113 114 #if !defined(CONFIG_USER_ONLY) 115 #include "pmp.h" 116 #include "debug.h" 117 #endif 118 119 #define RV_VLEN_MAX 1024 120 #define RV_MAX_MHPMEVENTS 32 121 #define RV_MAX_MHPMCOUNTERS 32 122 123 FIELD(VTYPE, VLMUL, 0, 3) 124 FIELD(VTYPE, VSEW, 3, 3) 125 FIELD(VTYPE, VTA, 6, 1) 126 FIELD(VTYPE, VMA, 7, 1) 127 FIELD(VTYPE, VEDIV, 8, 2) 128 FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) 129 130 typedef struct PMUCTRState { 131 /* Current value of a counter */ 132 target_ulong mhpmcounter_val; 133 /* Current value of a counter in RV32*/ 134 target_ulong mhpmcounterh_val; 135 /* Snapshot values of counter */ 136 target_ulong mhpmcounter_prev; 137 /* Snapshort value of a counter in RV32 */ 138 target_ulong mhpmcounterh_prev; 139 bool started; 140 } PMUCTRState; 141 142 struct CPUArchState { 143 target_ulong gpr[32]; 144 target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ 145 uint64_t fpr[32]; /* assume both F and D extensions */ 146 147 /* vector coprocessor state. */ 148 uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); 149 target_ulong vxrm; 150 target_ulong vxsat; 151 target_ulong vl; 152 target_ulong vstart; 153 target_ulong vtype; 154 bool vill; 155 156 target_ulong pc; 157 target_ulong load_res; 158 target_ulong load_val; 159 160 target_ulong frm; 161 162 target_ulong badaddr; 163 target_ulong bins; 164 165 target_ulong guest_phys_fault_addr; 166 167 target_ulong priv_ver; 168 target_ulong bext_ver; 169 target_ulong vext_ver; 170 171 /* RISCVMXL, but uint32_t for vmstate migration */ 172 uint32_t misa_mxl; /* current mxl */ 173 uint32_t misa_mxl_max; /* max mxl for this cpu */ 174 uint32_t misa_ext; /* current extensions */ 175 uint32_t misa_ext_mask; /* max ext for this cpu */ 176 uint32_t xl; /* current xlen */ 177 178 /* 128-bit helpers upper part return value */ 179 target_ulong retxh; 180 181 uint32_t features; 182 183 #ifdef CONFIG_USER_ONLY 184 uint32_t elf_flags; 185 #endif 186 187 #ifndef CONFIG_USER_ONLY 188 target_ulong priv; 189 /* This contains QEMU specific information about the virt state. */ 190 target_ulong virt; 191 target_ulong geilen; 192 target_ulong resetvec; 193 194 target_ulong mhartid; 195 /* 196 * For RV32 this is 32-bit mstatus and 32-bit mstatush. 197 * For RV64 this is a 64-bit mstatus. 198 */ 199 uint64_t mstatus; 200 201 uint64_t mip; 202 /* 203 * MIP contains the software writable version of SEIP ORed with the 204 * external interrupt value. The MIP register is always up-to-date. 205 * To keep track of the current source, we also save booleans of the values 206 * here. 207 */ 208 bool external_seip; 209 bool software_seip; 210 211 uint64_t miclaim; 212 213 uint64_t mie; 214 uint64_t mideleg; 215 216 target_ulong satp; /* since: priv-1.10.0 */ 217 target_ulong stval; 218 target_ulong medeleg; 219 220 target_ulong stvec; 221 target_ulong sepc; 222 target_ulong scause; 223 224 target_ulong mtvec; 225 target_ulong mepc; 226 target_ulong mcause; 227 target_ulong mtval; /* since: priv-1.10.0 */ 228 229 /* Machine and Supervisor interrupt priorities */ 230 uint8_t miprio[64]; 231 uint8_t siprio[64]; 232 233 /* AIA CSRs */ 234 target_ulong miselect; 235 target_ulong siselect; 236 237 /* Hypervisor CSRs */ 238 target_ulong hstatus; 239 target_ulong hedeleg; 240 uint64_t hideleg; 241 target_ulong hcounteren; 242 target_ulong htval; 243 target_ulong htinst; 244 target_ulong hgatp; 245 target_ulong hgeie; 246 target_ulong hgeip; 247 uint64_t htimedelta; 248 249 /* Hypervisor controlled virtual interrupt priorities */ 250 target_ulong hvictl; 251 uint8_t hviprio[64]; 252 253 /* Upper 64-bits of 128-bit CSRs */ 254 uint64_t mscratchh; 255 uint64_t sscratchh; 256 257 /* Virtual CSRs */ 258 /* 259 * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. 260 * For RV64 this is a 64-bit vsstatus. 261 */ 262 uint64_t vsstatus; 263 target_ulong vstvec; 264 target_ulong vsscratch; 265 target_ulong vsepc; 266 target_ulong vscause; 267 target_ulong vstval; 268 target_ulong vsatp; 269 270 /* AIA VS-mode CSRs */ 271 target_ulong vsiselect; 272 273 target_ulong mtval2; 274 target_ulong mtinst; 275 276 /* HS Backup CSRs */ 277 target_ulong stvec_hs; 278 target_ulong sscratch_hs; 279 target_ulong sepc_hs; 280 target_ulong scause_hs; 281 target_ulong stval_hs; 282 target_ulong satp_hs; 283 uint64_t mstatus_hs; 284 285 /* Signals whether the current exception occurred with two-stage address 286 translation active. */ 287 bool two_stage_lookup; 288 289 target_ulong scounteren; 290 target_ulong mcounteren; 291 292 target_ulong mcountinhibit; 293 294 /* PMU counter state */ 295 PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS]; 296 297 /* PMU event selector configured values. First three are unused*/ 298 target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS]; 299 300 target_ulong sscratch; 301 target_ulong mscratch; 302 303 /* temporary htif regs */ 304 uint64_t mfromhost; 305 uint64_t mtohost; 306 uint64_t timecmp; 307 308 /* physical memory protection */ 309 pmp_table_t pmp_state; 310 target_ulong mseccfg; 311 312 /* trigger module */ 313 target_ulong trigger_cur; 314 type2_trigger_t type2_trig[TRIGGER_TYPE2_NUM]; 315 316 /* machine specific rdtime callback */ 317 uint64_t (*rdtime_fn)(void *); 318 void *rdtime_fn_arg; 319 320 /* machine specific AIA ireg read-modify-write callback */ 321 #define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \ 322 ((((__xlen) & 0xff) << 24) | \ 323 (((__vgein) & 0x3f) << 20) | \ 324 (((__virt) & 0x1) << 18) | \ 325 (((__priv) & 0x3) << 16) | \ 326 (__isel & 0xffff)) 327 #define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff) 328 #define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3) 329 #define AIA_IREG_VIRT(__ireg) (((__ireg) >> 18) & 0x1) 330 #define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 20) & 0x3f) 331 #define AIA_IREG_XLEN(__ireg) (((__ireg) >> 24) & 0xff) 332 int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg, 333 target_ulong *val, target_ulong new_val, target_ulong write_mask); 334 void *aia_ireg_rmw_fn_arg[4]; 335 336 /* True if in debugger mode. */ 337 bool debugger; 338 339 /* 340 * CSRs for PointerMasking extension 341 */ 342 target_ulong mmte; 343 target_ulong mpmmask; 344 target_ulong mpmbase; 345 target_ulong spmmask; 346 target_ulong spmbase; 347 target_ulong upmmask; 348 target_ulong upmbase; 349 350 /* CSRs for execution enviornment configuration */ 351 uint64_t menvcfg; 352 target_ulong senvcfg; 353 uint64_t henvcfg; 354 #endif 355 target_ulong cur_pmmask; 356 target_ulong cur_pmbase; 357 358 float_status fp_status; 359 360 /* Fields from here on are preserved across CPU reset. */ 361 QEMUTimer *timer; /* Internal timer */ 362 363 hwaddr kernel_addr; 364 hwaddr fdt_addr; 365 366 /* kvm timer */ 367 bool kvm_timer_dirty; 368 uint64_t kvm_timer_time; 369 uint64_t kvm_timer_compare; 370 uint64_t kvm_timer_state; 371 uint64_t kvm_timer_frequency; 372 }; 373 374 OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) 375 376 /** 377 * RISCVCPUClass: 378 * @parent_realize: The parent class' realize handler. 379 * @parent_reset: The parent class' reset handler. 380 * 381 * A RISCV CPU model. 382 */ 383 struct RISCVCPUClass { 384 /*< private >*/ 385 CPUClass parent_class; 386 /*< public >*/ 387 DeviceRealize parent_realize; 388 DeviceReset parent_reset; 389 }; 390 391 struct RISCVCPUConfig { 392 bool ext_i; 393 bool ext_e; 394 bool ext_g; 395 bool ext_m; 396 bool ext_a; 397 bool ext_f; 398 bool ext_d; 399 bool ext_c; 400 bool ext_s; 401 bool ext_u; 402 bool ext_h; 403 bool ext_j; 404 bool ext_v; 405 bool ext_zba; 406 bool ext_zbb; 407 bool ext_zbc; 408 bool ext_zbkb; 409 bool ext_zbkc; 410 bool ext_zbkx; 411 bool ext_zbs; 412 bool ext_zk; 413 bool ext_zkn; 414 bool ext_zknd; 415 bool ext_zkne; 416 bool ext_zknh; 417 bool ext_zkr; 418 bool ext_zks; 419 bool ext_zksed; 420 bool ext_zksh; 421 bool ext_zkt; 422 bool ext_ifencei; 423 bool ext_icsr; 424 bool ext_svinval; 425 bool ext_svnapot; 426 bool ext_svpbmt; 427 bool ext_zdinx; 428 bool ext_zfh; 429 bool ext_zfhmin; 430 bool ext_zfinx; 431 bool ext_zhinx; 432 bool ext_zhinxmin; 433 bool ext_zve32f; 434 bool ext_zve64f; 435 bool ext_zmmul; 436 bool rvv_ta_all_1s; 437 438 uint32_t mvendorid; 439 uint64_t marchid; 440 uint64_t mimpid; 441 442 /* Vendor-specific custom extensions */ 443 bool ext_XVentanaCondOps; 444 445 uint8_t pmu_num; 446 char *priv_spec; 447 char *user_spec; 448 char *bext_spec; 449 char *vext_spec; 450 uint16_t vlen; 451 uint16_t elen; 452 bool mmu; 453 bool pmp; 454 bool epmp; 455 bool aia; 456 bool debug; 457 uint64_t resetvec; 458 459 bool short_isa_string; 460 }; 461 462 typedef struct RISCVCPUConfig RISCVCPUConfig; 463 464 /** 465 * RISCVCPU: 466 * @env: #CPURISCVState 467 * 468 * A RISCV CPU. 469 */ 470 struct ArchCPU { 471 /*< private >*/ 472 CPUState parent_obj; 473 /*< public >*/ 474 CPUNegativeOffsetState neg; 475 CPURISCVState env; 476 477 char *dyn_csr_xml; 478 char *dyn_vreg_xml; 479 480 /* Configuration Settings */ 481 RISCVCPUConfig cfg; 482 }; 483 484 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) 485 { 486 return (env->misa_ext & ext) != 0; 487 } 488 489 static inline bool riscv_feature(CPURISCVState *env, int feature) 490 { 491 return env->features & (1ULL << feature); 492 } 493 494 static inline void riscv_set_feature(CPURISCVState *env, int feature) 495 { 496 env->features |= (1ULL << feature); 497 } 498 499 #include "cpu_user.h" 500 501 extern const char * const riscv_int_regnames[]; 502 extern const char * const riscv_int_regnamesh[]; 503 extern const char * const riscv_fpr_regnames[]; 504 505 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); 506 void riscv_cpu_do_interrupt(CPUState *cpu); 507 int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 508 int cpuid, void *opaque); 509 int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 510 int cpuid, void *opaque); 511 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 512 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 513 int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero); 514 uint8_t riscv_cpu_default_priority(int irq); 515 uint64_t riscv_cpu_all_pending(CPURISCVState *env); 516 int riscv_cpu_mirq_pending(CPURISCVState *env); 517 int riscv_cpu_sirq_pending(CPURISCVState *env); 518 int riscv_cpu_vsirq_pending(CPURISCVState *env); 519 bool riscv_cpu_fp_enabled(CPURISCVState *env); 520 target_ulong riscv_cpu_get_geilen(CPURISCVState *env); 521 void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); 522 bool riscv_cpu_vector_enabled(CPURISCVState *env); 523 bool riscv_cpu_virt_enabled(CPURISCVState *env); 524 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); 525 bool riscv_cpu_two_stage_lookup(int mmu_idx); 526 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); 527 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 528 G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 529 MMUAccessType access_type, int mmu_idx, 530 uintptr_t retaddr); 531 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 532 MMUAccessType access_type, int mmu_idx, 533 bool probe, uintptr_t retaddr); 534 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 535 vaddr addr, unsigned size, 536 MMUAccessType access_type, 537 int mmu_idx, MemTxAttrs attrs, 538 MemTxResult response, uintptr_t retaddr); 539 char *riscv_isa_string(RISCVCPU *cpu); 540 void riscv_cpu_list(void); 541 542 #define cpu_list riscv_cpu_list 543 #define cpu_mmu_index riscv_cpu_mmu_index 544 545 #ifndef CONFIG_USER_ONLY 546 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); 547 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); 548 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); 549 uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value); 550 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ 551 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), 552 void *arg); 553 void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, 554 int (*rmw_fn)(void *arg, 555 target_ulong reg, 556 target_ulong *val, 557 target_ulong new_val, 558 target_ulong write_mask), 559 void *rmw_fn_arg); 560 #endif 561 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); 562 563 void riscv_translate_init(void); 564 G_NORETURN void riscv_raise_exception(CPURISCVState *env, 565 uint32_t exception, uintptr_t pc); 566 567 target_ulong riscv_cpu_get_fflags(CPURISCVState *env); 568 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); 569 570 #define TB_FLAGS_PRIV_MMU_MASK 3 571 #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2) 572 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS 573 #define TB_FLAGS_MSTATUS_VS MSTATUS_VS 574 575 #include "exec/cpu-all.h" 576 577 FIELD(TB_FLAGS, MEM_IDX, 0, 3) 578 FIELD(TB_FLAGS, LMUL, 3, 3) 579 FIELD(TB_FLAGS, SEW, 6, 3) 580 /* Skip MSTATUS_VS (0x600) bits */ 581 FIELD(TB_FLAGS, VL_EQ_VLMAX, 11, 1) 582 FIELD(TB_FLAGS, VILL, 12, 1) 583 /* Skip MSTATUS_FS (0x6000) bits */ 584 /* Is a Hypervisor instruction load/store allowed? */ 585 FIELD(TB_FLAGS, HLSX, 15, 1) 586 FIELD(TB_FLAGS, MSTATUS_HS_FS, 16, 2) 587 FIELD(TB_FLAGS, MSTATUS_HS_VS, 18, 2) 588 /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ 589 FIELD(TB_FLAGS, XL, 20, 2) 590 /* If PointerMasking should be applied */ 591 FIELD(TB_FLAGS, PM_MASK_ENABLED, 22, 1) 592 FIELD(TB_FLAGS, PM_BASE_ENABLED, 23, 1) 593 FIELD(TB_FLAGS, VTA, 24, 1) 594 595 #ifdef TARGET_RISCV32 596 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) 597 #else 598 static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) 599 { 600 return env->misa_mxl; 601 } 602 #endif 603 #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env))) 604 605 #if defined(TARGET_RISCV32) 606 #define cpu_recompute_xl(env) ((void)(env), MXL_RV32) 607 #else 608 static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) 609 { 610 RISCVMXL xl = env->misa_mxl; 611 #if !defined(CONFIG_USER_ONLY) 612 /* 613 * When emulating a 32-bit-only cpu, use RV32. 614 * When emulating a 64-bit cpu, and MXL has been reduced to RV32, 615 * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened 616 * back to RV64 for lower privs. 617 */ 618 if (xl != MXL_RV32) { 619 switch (env->priv) { 620 case PRV_M: 621 break; 622 case PRV_U: 623 xl = get_field(env->mstatus, MSTATUS64_UXL); 624 break; 625 default: /* PRV_S | PRV_H */ 626 xl = get_field(env->mstatus, MSTATUS64_SXL); 627 break; 628 } 629 } 630 #endif 631 return xl; 632 } 633 #endif 634 635 static inline int riscv_cpu_xlen(CPURISCVState *env) 636 { 637 return 16 << env->xl; 638 } 639 640 #ifdef TARGET_RISCV32 641 #define riscv_cpu_sxl(env) ((void)(env), MXL_RV32) 642 #else 643 static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env) 644 { 645 #ifdef CONFIG_USER_ONLY 646 return env->misa_mxl; 647 #else 648 return get_field(env->mstatus, MSTATUS64_SXL); 649 #endif 650 } 651 #endif 652 653 /* 654 * Encode LMUL to lmul as follows: 655 * LMUL vlmul lmul 656 * 1 000 0 657 * 2 001 1 658 * 4 010 2 659 * 8 011 3 660 * - 100 - 661 * 1/8 101 -3 662 * 1/4 110 -2 663 * 1/2 111 -1 664 * 665 * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul) 666 * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8 667 * => VLMAX = vlen >> (1 + 3 - (-3)) 668 * = 256 >> 7 669 * = 2 670 */ 671 static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) 672 { 673 uint8_t sew = FIELD_EX64(vtype, VTYPE, VSEW); 674 int8_t lmul = sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3); 675 return cpu->cfg.vlen >> (sew + 3 - lmul); 676 } 677 678 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 679 target_ulong *cs_base, uint32_t *pflags); 680 681 void riscv_cpu_update_mask(CPURISCVState *env); 682 683 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, 684 target_ulong *ret_value, 685 target_ulong new_value, target_ulong write_mask); 686 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, 687 target_ulong *ret_value, 688 target_ulong new_value, 689 target_ulong write_mask); 690 691 static inline void riscv_csr_write(CPURISCVState *env, int csrno, 692 target_ulong val) 693 { 694 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); 695 } 696 697 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) 698 { 699 target_ulong val = 0; 700 riscv_csrrw(env, csrno, &val, 0, 0); 701 return val; 702 } 703 704 typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, 705 int csrno); 706 typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, 707 target_ulong *ret_value); 708 typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, 709 target_ulong new_value); 710 typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, 711 target_ulong *ret_value, 712 target_ulong new_value, 713 target_ulong write_mask); 714 715 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, 716 Int128 *ret_value, 717 Int128 new_value, Int128 write_mask); 718 719 typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno, 720 Int128 *ret_value); 721 typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int csrno, 722 Int128 new_value); 723 724 typedef struct { 725 const char *name; 726 riscv_csr_predicate_fn predicate; 727 riscv_csr_read_fn read; 728 riscv_csr_write_fn write; 729 riscv_csr_op_fn op; 730 riscv_csr_read128_fn read128; 731 riscv_csr_write128_fn write128; 732 /* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0) */ 733 uint32_t min_priv_ver; 734 } riscv_csr_operations; 735 736 /* CSR function table constants */ 737 enum { 738 CSR_TABLE_SIZE = 0x1000 739 }; 740 741 /* CSR function table */ 742 extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; 743 744 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); 745 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); 746 747 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); 748 749 #endif /* RISCV_CPU_H */ 750