1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef RISCV_CPU_H 21 #define RISCV_CPU_H 22 23 #include "hw/core/cpu.h" 24 #include "hw/registerfields.h" 25 #include "exec/cpu-defs.h" 26 #include "qemu/cpu-float.h" 27 #include "qom/object.h" 28 #include "qemu/int128.h" 29 #include "cpu_bits.h" 30 #include "qapi/qapi-types-common.h" 31 32 #define TCG_GUEST_DEFAULT_MO 0 33 34 /* 35 * RISC-V-specific extra insn start words: 36 * 1: Original instruction opcode 37 */ 38 #define TARGET_INSN_START_EXTRA_WORDS 1 39 40 #define TYPE_RISCV_CPU "riscv-cpu" 41 42 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU 43 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) 44 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU 45 46 #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") 47 #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") 48 #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") 49 #define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128") 50 #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") 51 #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") 52 #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") 53 #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") 54 #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") 55 #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") 56 #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") 57 #define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906") 58 #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") 59 60 #if defined(TARGET_RISCV32) 61 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 62 #elif defined(TARGET_RISCV64) 63 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 64 #endif 65 66 #define RV(x) ((target_ulong)1 << (x - 'A')) 67 68 /* 69 * Consider updating register_cpu_props() when adding 70 * new MISA bits here. 71 */ 72 #define RVI RV('I') 73 #define RVE RV('E') /* E and I are mutually exclusive */ 74 #define RVM RV('M') 75 #define RVA RV('A') 76 #define RVF RV('F') 77 #define RVD RV('D') 78 #define RVV RV('V') 79 #define RVC RV('C') 80 #define RVS RV('S') 81 #define RVU RV('U') 82 #define RVH RV('H') 83 #define RVJ RV('J') 84 85 86 /* Privileged specification version */ 87 enum { 88 PRIV_VERSION_1_10_0 = 0, 89 PRIV_VERSION_1_11_0, 90 PRIV_VERSION_1_12_0, 91 }; 92 93 #define VEXT_VERSION_1_00_0 0x00010000 94 95 enum { 96 TRANSLATE_SUCCESS, 97 TRANSLATE_FAIL, 98 TRANSLATE_PMP_FAIL, 99 TRANSLATE_G_STAGE_FAIL 100 }; 101 102 #define MMU_USER_IDX 3 103 104 #define MAX_RISCV_PMPS (16) 105 106 typedef struct CPUArchState CPURISCVState; 107 108 #if !defined(CONFIG_USER_ONLY) 109 #include "pmp.h" 110 #include "debug.h" 111 #endif 112 113 #define RV_VLEN_MAX 1024 114 #define RV_MAX_MHPMEVENTS 32 115 #define RV_MAX_MHPMCOUNTERS 32 116 117 FIELD(VTYPE, VLMUL, 0, 3) 118 FIELD(VTYPE, VSEW, 3, 3) 119 FIELD(VTYPE, VTA, 6, 1) 120 FIELD(VTYPE, VMA, 7, 1) 121 FIELD(VTYPE, VEDIV, 8, 2) 122 FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) 123 124 typedef struct PMUCTRState { 125 /* Current value of a counter */ 126 target_ulong mhpmcounter_val; 127 /* Current value of a counter in RV32 */ 128 target_ulong mhpmcounterh_val; 129 /* Snapshot values of counter */ 130 target_ulong mhpmcounter_prev; 131 /* Snapshort value of a counter in RV32 */ 132 target_ulong mhpmcounterh_prev; 133 bool started; 134 /* Value beyond UINT32_MAX/UINT64_MAX before overflow interrupt trigger */ 135 target_ulong irq_overflow_left; 136 } PMUCTRState; 137 138 struct CPUArchState { 139 target_ulong gpr[32]; 140 target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ 141 142 /* vector coprocessor state. */ 143 uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); 144 target_ulong vxrm; 145 target_ulong vxsat; 146 target_ulong vl; 147 target_ulong vstart; 148 target_ulong vtype; 149 bool vill; 150 151 target_ulong pc; 152 target_ulong load_res; 153 target_ulong load_val; 154 155 /* Floating-Point state */ 156 uint64_t fpr[32]; /* assume both F and D extensions */ 157 target_ulong frm; 158 float_status fp_status; 159 160 target_ulong badaddr; 161 target_ulong bins; 162 163 target_ulong guest_phys_fault_addr; 164 165 target_ulong priv_ver; 166 target_ulong bext_ver; 167 target_ulong vext_ver; 168 169 /* RISCVMXL, but uint32_t for vmstate migration */ 170 uint32_t misa_mxl; /* current mxl */ 171 uint32_t misa_mxl_max; /* max mxl for this cpu */ 172 uint32_t misa_ext; /* current extensions */ 173 uint32_t misa_ext_mask; /* max ext for this cpu */ 174 uint32_t xl; /* current xlen */ 175 176 /* 128-bit helpers upper part return value */ 177 target_ulong retxh; 178 179 target_ulong jvt; 180 181 #ifdef CONFIG_USER_ONLY 182 uint32_t elf_flags; 183 #endif 184 185 #ifndef CONFIG_USER_ONLY 186 target_ulong priv; 187 /* This contains QEMU specific information about the virt state. */ 188 bool virt_enabled; 189 target_ulong geilen; 190 uint64_t resetvec; 191 192 target_ulong mhartid; 193 /* 194 * For RV32 this is 32-bit mstatus and 32-bit mstatush. 195 * For RV64 this is a 64-bit mstatus. 196 */ 197 uint64_t mstatus; 198 199 uint64_t mip; 200 /* 201 * MIP contains the software writable version of SEIP ORed with the 202 * external interrupt value. The MIP register is always up-to-date. 203 * To keep track of the current source, we also save booleans of the values 204 * here. 205 */ 206 bool external_seip; 207 bool software_seip; 208 209 uint64_t miclaim; 210 211 uint64_t mie; 212 uint64_t mideleg; 213 214 target_ulong satp; /* since: priv-1.10.0 */ 215 target_ulong stval; 216 target_ulong medeleg; 217 218 target_ulong stvec; 219 target_ulong sepc; 220 target_ulong scause; 221 222 target_ulong mtvec; 223 target_ulong mepc; 224 target_ulong mcause; 225 target_ulong mtval; /* since: priv-1.10.0 */ 226 227 /* Machine and Supervisor interrupt priorities */ 228 uint8_t miprio[64]; 229 uint8_t siprio[64]; 230 231 /* AIA CSRs */ 232 target_ulong miselect; 233 target_ulong siselect; 234 235 /* Hypervisor CSRs */ 236 target_ulong hstatus; 237 target_ulong hedeleg; 238 uint64_t hideleg; 239 target_ulong hcounteren; 240 target_ulong htval; 241 target_ulong htinst; 242 target_ulong hgatp; 243 target_ulong hgeie; 244 target_ulong hgeip; 245 uint64_t htimedelta; 246 247 /* Hypervisor controlled virtual interrupt priorities */ 248 target_ulong hvictl; 249 uint8_t hviprio[64]; 250 251 /* Upper 64-bits of 128-bit CSRs */ 252 uint64_t mscratchh; 253 uint64_t sscratchh; 254 255 /* Virtual CSRs */ 256 /* 257 * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. 258 * For RV64 this is a 64-bit vsstatus. 259 */ 260 uint64_t vsstatus; 261 target_ulong vstvec; 262 target_ulong vsscratch; 263 target_ulong vsepc; 264 target_ulong vscause; 265 target_ulong vstval; 266 target_ulong vsatp; 267 268 /* AIA VS-mode CSRs */ 269 target_ulong vsiselect; 270 271 target_ulong mtval2; 272 target_ulong mtinst; 273 274 /* HS Backup CSRs */ 275 target_ulong stvec_hs; 276 target_ulong sscratch_hs; 277 target_ulong sepc_hs; 278 target_ulong scause_hs; 279 target_ulong stval_hs; 280 target_ulong satp_hs; 281 uint64_t mstatus_hs; 282 283 /* 284 * Signals whether the current exception occurred with two-stage address 285 * translation active. 286 */ 287 bool two_stage_lookup; 288 /* 289 * Signals whether the current exception occurred while doing two-stage 290 * address translation for the VS-stage page table walk. 291 */ 292 bool two_stage_indirect_lookup; 293 294 target_ulong scounteren; 295 target_ulong mcounteren; 296 297 target_ulong mcountinhibit; 298 299 /* PMU counter state */ 300 PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS]; 301 302 /* PMU event selector configured values. First three are unused */ 303 target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS]; 304 305 /* PMU event selector configured values for RV32 */ 306 target_ulong mhpmeventh_val[RV_MAX_MHPMEVENTS]; 307 308 target_ulong sscratch; 309 target_ulong mscratch; 310 311 /* Sstc CSRs */ 312 uint64_t stimecmp; 313 314 uint64_t vstimecmp; 315 316 /* physical memory protection */ 317 pmp_table_t pmp_state; 318 target_ulong mseccfg; 319 320 /* trigger module */ 321 target_ulong trigger_cur; 322 target_ulong tdata1[RV_MAX_TRIGGERS]; 323 target_ulong tdata2[RV_MAX_TRIGGERS]; 324 target_ulong tdata3[RV_MAX_TRIGGERS]; 325 struct CPUBreakpoint *cpu_breakpoint[RV_MAX_TRIGGERS]; 326 struct CPUWatchpoint *cpu_watchpoint[RV_MAX_TRIGGERS]; 327 QEMUTimer *itrigger_timer[RV_MAX_TRIGGERS]; 328 int64_t last_icount; 329 bool itrigger_enabled; 330 331 /* machine specific rdtime callback */ 332 uint64_t (*rdtime_fn)(void *); 333 void *rdtime_fn_arg; 334 335 /* machine specific AIA ireg read-modify-write callback */ 336 #define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \ 337 ((((__xlen) & 0xff) << 24) | \ 338 (((__vgein) & 0x3f) << 20) | \ 339 (((__virt) & 0x1) << 18) | \ 340 (((__priv) & 0x3) << 16) | \ 341 (__isel & 0xffff)) 342 #define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff) 343 #define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3) 344 #define AIA_IREG_VIRT(__ireg) (((__ireg) >> 18) & 0x1) 345 #define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 20) & 0x3f) 346 #define AIA_IREG_XLEN(__ireg) (((__ireg) >> 24) & 0xff) 347 int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg, 348 target_ulong *val, target_ulong new_val, target_ulong write_mask); 349 void *aia_ireg_rmw_fn_arg[4]; 350 351 /* True if in debugger mode. */ 352 bool debugger; 353 354 /* 355 * CSRs for PointerMasking extension 356 */ 357 target_ulong mmte; 358 target_ulong mpmmask; 359 target_ulong mpmbase; 360 target_ulong spmmask; 361 target_ulong spmbase; 362 target_ulong upmmask; 363 target_ulong upmbase; 364 365 /* CSRs for execution enviornment configuration */ 366 uint64_t menvcfg; 367 uint64_t mstateen[SMSTATEEN_MAX_COUNT]; 368 uint64_t hstateen[SMSTATEEN_MAX_COUNT]; 369 uint64_t sstateen[SMSTATEEN_MAX_COUNT]; 370 target_ulong senvcfg; 371 uint64_t henvcfg; 372 #endif 373 target_ulong cur_pmmask; 374 target_ulong cur_pmbase; 375 376 /* Fields from here on are preserved across CPU reset. */ 377 QEMUTimer *stimer; /* Internal timer for S-mode interrupt */ 378 QEMUTimer *vstimer; /* Internal timer for VS-mode interrupt */ 379 bool vstime_irq; 380 381 hwaddr kernel_addr; 382 hwaddr fdt_addr; 383 384 /* kvm timer */ 385 bool kvm_timer_dirty; 386 uint64_t kvm_timer_time; 387 uint64_t kvm_timer_compare; 388 uint64_t kvm_timer_state; 389 uint64_t kvm_timer_frequency; 390 }; 391 392 OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) 393 394 /* 395 * RISCVCPUClass: 396 * @parent_realize: The parent class' realize handler. 397 * @parent_phases: The parent class' reset phase handlers. 398 * 399 * A RISCV CPU model. 400 */ 401 struct RISCVCPUClass { 402 /* < private > */ 403 CPUClass parent_class; 404 /* < public > */ 405 DeviceRealize parent_realize; 406 ResettablePhases parent_phases; 407 }; 408 409 /* 410 * map is a 16-bit bitmap: the most significant set bit in map is the maximum 411 * satp mode that is supported. It may be chosen by the user and must respect 412 * what qemu implements (valid_1_10_32/64) and what the hw is capable of 413 * (supported bitmap below). 414 * 415 * init is a 16-bit bitmap used to make sure the user selected a correct 416 * configuration as per the specification. 417 * 418 * supported is a 16-bit bitmap used to reflect the hw capabilities. 419 */ 420 typedef struct { 421 uint16_t map, init, supported; 422 } RISCVSATPMap; 423 424 struct RISCVCPUConfig { 425 bool ext_g; 426 bool ext_j; 427 bool ext_v; 428 bool ext_zba; 429 bool ext_zbb; 430 bool ext_zbc; 431 bool ext_zbkb; 432 bool ext_zbkc; 433 bool ext_zbkx; 434 bool ext_zbs; 435 bool ext_zca; 436 bool ext_zcb; 437 bool ext_zcd; 438 bool ext_zce; 439 bool ext_zcf; 440 bool ext_zcmp; 441 bool ext_zcmt; 442 bool ext_zk; 443 bool ext_zkn; 444 bool ext_zknd; 445 bool ext_zkne; 446 bool ext_zknh; 447 bool ext_zkr; 448 bool ext_zks; 449 bool ext_zksed; 450 bool ext_zksh; 451 bool ext_zkt; 452 bool ext_ifencei; 453 bool ext_icsr; 454 bool ext_icbom; 455 bool ext_icboz; 456 bool ext_zicond; 457 bool ext_zihintpause; 458 bool ext_smstateen; 459 bool ext_sstc; 460 bool ext_svadu; 461 bool ext_svinval; 462 bool ext_svnapot; 463 bool ext_svpbmt; 464 bool ext_zdinx; 465 bool ext_zawrs; 466 bool ext_zfh; 467 bool ext_zfhmin; 468 bool ext_zfinx; 469 bool ext_zhinx; 470 bool ext_zhinxmin; 471 bool ext_zve32f; 472 bool ext_zve64f; 473 bool ext_zve64d; 474 bool ext_zmmul; 475 bool ext_zvfh; 476 bool ext_zvfhmin; 477 bool ext_smaia; 478 bool ext_ssaia; 479 bool ext_sscofpmf; 480 bool rvv_ta_all_1s; 481 bool rvv_ma_all_1s; 482 483 uint32_t mvendorid; 484 uint64_t marchid; 485 uint64_t mimpid; 486 487 /* Vendor-specific custom extensions */ 488 bool ext_xtheadba; 489 bool ext_xtheadbb; 490 bool ext_xtheadbs; 491 bool ext_xtheadcmo; 492 bool ext_xtheadcondmov; 493 bool ext_xtheadfmemidx; 494 bool ext_xtheadfmv; 495 bool ext_xtheadmac; 496 bool ext_xtheadmemidx; 497 bool ext_xtheadmempair; 498 bool ext_xtheadsync; 499 bool ext_XVentanaCondOps; 500 501 uint8_t pmu_num; 502 char *priv_spec; 503 char *user_spec; 504 char *bext_spec; 505 char *vext_spec; 506 uint16_t vlen; 507 uint16_t elen; 508 uint16_t cbom_blocksize; 509 uint16_t cboz_blocksize; 510 bool mmu; 511 bool pmp; 512 bool epmp; 513 bool debug; 514 bool misa_w; 515 516 bool short_isa_string; 517 518 #ifndef CONFIG_USER_ONLY 519 RISCVSATPMap satp_mode; 520 #endif 521 }; 522 523 typedef struct RISCVCPUConfig RISCVCPUConfig; 524 525 /* 526 * RISCVCPU: 527 * @env: #CPURISCVState 528 * 529 * A RISCV CPU. 530 */ 531 struct ArchCPU { 532 /* < private > */ 533 CPUState parent_obj; 534 /* < public > */ 535 CPUNegativeOffsetState neg; 536 CPURISCVState env; 537 538 char *dyn_csr_xml; 539 char *dyn_vreg_xml; 540 541 /* Configuration Settings */ 542 RISCVCPUConfig cfg; 543 544 QEMUTimer *pmu_timer; 545 /* A bitmask of Available programmable counters */ 546 uint32_t pmu_avail_ctrs; 547 /* Mapping of events to counters */ 548 GHashTable *pmu_event_ctr_map; 549 }; 550 551 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) 552 { 553 return (env->misa_ext & ext) != 0; 554 } 555 556 #include "cpu_user.h" 557 558 extern const char * const riscv_int_regnames[]; 559 extern const char * const riscv_int_regnamesh[]; 560 extern const char * const riscv_fpr_regnames[]; 561 562 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); 563 void riscv_cpu_do_interrupt(CPUState *cpu); 564 int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 565 int cpuid, DumpState *s); 566 int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 567 int cpuid, DumpState *s); 568 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 569 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 570 int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero); 571 uint8_t riscv_cpu_default_priority(int irq); 572 uint64_t riscv_cpu_all_pending(CPURISCVState *env); 573 int riscv_cpu_mirq_pending(CPURISCVState *env); 574 int riscv_cpu_sirq_pending(CPURISCVState *env); 575 int riscv_cpu_vsirq_pending(CPURISCVState *env); 576 bool riscv_cpu_fp_enabled(CPURISCVState *env); 577 target_ulong riscv_cpu_get_geilen(CPURISCVState *env); 578 void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); 579 bool riscv_cpu_vector_enabled(CPURISCVState *env); 580 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); 581 bool riscv_cpu_two_stage_lookup(int mmu_idx); 582 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); 583 G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 584 MMUAccessType access_type, 585 int mmu_idx, uintptr_t retaddr); 586 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 587 MMUAccessType access_type, int mmu_idx, 588 bool probe, uintptr_t retaddr); 589 char *riscv_isa_string(RISCVCPU *cpu); 590 void riscv_cpu_list(void); 591 592 #define cpu_list riscv_cpu_list 593 #define cpu_mmu_index riscv_cpu_mmu_index 594 595 #ifndef CONFIG_USER_ONLY 596 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 597 vaddr addr, unsigned size, 598 MMUAccessType access_type, 599 int mmu_idx, MemTxAttrs attrs, 600 MemTxResult response, uintptr_t retaddr); 601 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 602 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); 603 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); 604 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); 605 uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask, 606 uint64_t value); 607 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ 608 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), 609 void *arg); 610 void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, 611 int (*rmw_fn)(void *arg, 612 target_ulong reg, 613 target_ulong *val, 614 target_ulong new_val, 615 target_ulong write_mask), 616 void *rmw_fn_arg); 617 618 RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit); 619 #endif 620 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); 621 622 void riscv_translate_init(void); 623 G_NORETURN void riscv_raise_exception(CPURISCVState *env, 624 uint32_t exception, uintptr_t pc); 625 626 target_ulong riscv_cpu_get_fflags(CPURISCVState *env); 627 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); 628 629 #define TB_FLAGS_PRIV_MMU_MASK 3 630 #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2) 631 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS 632 #define TB_FLAGS_MSTATUS_VS MSTATUS_VS 633 634 #include "exec/cpu-all.h" 635 636 FIELD(TB_FLAGS, MEM_IDX, 0, 3) 637 FIELD(TB_FLAGS, LMUL, 3, 3) 638 FIELD(TB_FLAGS, SEW, 6, 3) 639 /* Skip MSTATUS_VS (0x600) bits */ 640 FIELD(TB_FLAGS, VL_EQ_VLMAX, 11, 1) 641 FIELD(TB_FLAGS, VILL, 12, 1) 642 /* Skip MSTATUS_FS (0x6000) bits */ 643 /* Is a Hypervisor instruction load/store allowed? */ 644 FIELD(TB_FLAGS, HLSX, 15, 1) 645 FIELD(TB_FLAGS, MSTATUS_HS_FS, 16, 2) 646 FIELD(TB_FLAGS, MSTATUS_HS_VS, 18, 2) 647 /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ 648 FIELD(TB_FLAGS, XL, 20, 2) 649 /* If PointerMasking should be applied */ 650 FIELD(TB_FLAGS, PM_MASK_ENABLED, 22, 1) 651 FIELD(TB_FLAGS, PM_BASE_ENABLED, 23, 1) 652 FIELD(TB_FLAGS, VTA, 24, 1) 653 FIELD(TB_FLAGS, VMA, 25, 1) 654 /* Native debug itrigger */ 655 FIELD(TB_FLAGS, ITRIGGER, 26, 1) 656 657 #ifdef TARGET_RISCV32 658 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) 659 #else 660 static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) 661 { 662 return env->misa_mxl; 663 } 664 #endif 665 #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env))) 666 667 static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURISCVState *env) 668 { 669 return &env_archcpu(env)->cfg; 670 } 671 672 #if defined(TARGET_RISCV32) 673 #define cpu_recompute_xl(env) ((void)(env), MXL_RV32) 674 #else 675 static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) 676 { 677 RISCVMXL xl = env->misa_mxl; 678 #if !defined(CONFIG_USER_ONLY) 679 /* 680 * When emulating a 32-bit-only cpu, use RV32. 681 * When emulating a 64-bit cpu, and MXL has been reduced to RV32, 682 * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened 683 * back to RV64 for lower privs. 684 */ 685 if (xl != MXL_RV32) { 686 switch (env->priv) { 687 case PRV_M: 688 break; 689 case PRV_U: 690 xl = get_field(env->mstatus, MSTATUS64_UXL); 691 break; 692 default: /* PRV_S | PRV_H */ 693 xl = get_field(env->mstatus, MSTATUS64_SXL); 694 break; 695 } 696 } 697 #endif 698 return xl; 699 } 700 #endif 701 702 static inline int riscv_cpu_xlen(CPURISCVState *env) 703 { 704 return 16 << env->xl; 705 } 706 707 #ifdef TARGET_RISCV32 708 #define riscv_cpu_sxl(env) ((void)(env), MXL_RV32) 709 #else 710 static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env) 711 { 712 #ifdef CONFIG_USER_ONLY 713 return env->misa_mxl; 714 #else 715 return get_field(env->mstatus, MSTATUS64_SXL); 716 #endif 717 } 718 #endif 719 720 /* 721 * Encode LMUL to lmul as follows: 722 * LMUL vlmul lmul 723 * 1 000 0 724 * 2 001 1 725 * 4 010 2 726 * 8 011 3 727 * - 100 - 728 * 1/8 101 -3 729 * 1/4 110 -2 730 * 1/2 111 -1 731 * 732 * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul) 733 * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8 734 * => VLMAX = vlen >> (1 + 3 - (-3)) 735 * = 256 >> 7 736 * = 2 737 */ 738 static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) 739 { 740 uint8_t sew = FIELD_EX64(vtype, VTYPE, VSEW); 741 int8_t lmul = sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3); 742 return cpu->cfg.vlen >> (sew + 3 - lmul); 743 } 744 745 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 746 target_ulong *cs_base, uint32_t *pflags); 747 748 void riscv_cpu_update_mask(CPURISCVState *env); 749 750 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, 751 target_ulong *ret_value, 752 target_ulong new_value, target_ulong write_mask); 753 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, 754 target_ulong *ret_value, 755 target_ulong new_value, 756 target_ulong write_mask); 757 758 static inline void riscv_csr_write(CPURISCVState *env, int csrno, 759 target_ulong val) 760 { 761 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); 762 } 763 764 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) 765 { 766 target_ulong val = 0; 767 riscv_csrrw(env, csrno, &val, 0, 0); 768 return val; 769 } 770 771 typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, 772 int csrno); 773 typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, 774 target_ulong *ret_value); 775 typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, 776 target_ulong new_value); 777 typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, 778 target_ulong *ret_value, 779 target_ulong new_value, 780 target_ulong write_mask); 781 782 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, 783 Int128 *ret_value, 784 Int128 new_value, Int128 write_mask); 785 786 typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno, 787 Int128 *ret_value); 788 typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int csrno, 789 Int128 new_value); 790 791 typedef struct { 792 const char *name; 793 riscv_csr_predicate_fn predicate; 794 riscv_csr_read_fn read; 795 riscv_csr_write_fn write; 796 riscv_csr_op_fn op; 797 riscv_csr_read128_fn read128; 798 riscv_csr_write128_fn write128; 799 /* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0) */ 800 uint32_t min_priv_ver; 801 } riscv_csr_operations; 802 803 /* CSR function table constants */ 804 enum { 805 CSR_TABLE_SIZE = 0x1000 806 }; 807 808 /* 809 * The event id are encoded based on the encoding specified in the 810 * SBI specification v0.3 811 */ 812 813 enum riscv_pmu_event_idx { 814 RISCV_PMU_EVENT_HW_CPU_CYCLES = 0x01, 815 RISCV_PMU_EVENT_HW_INSTRUCTIONS = 0x02, 816 RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS = 0x10019, 817 RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS = 0x1001B, 818 RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS = 0x10021, 819 }; 820 821 /* CSR function table */ 822 extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; 823 824 extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[]; 825 826 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); 827 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); 828 829 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); 830 831 uint8_t satp_mode_max_from_map(uint32_t map); 832 const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); 833 834 #endif /* RISCV_CPU_H */ 835