1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef RISCV_CPU_H 21 #define RISCV_CPU_H 22 23 #include "hw/core/cpu.h" 24 #include "hw/registerfields.h" 25 #include "exec/cpu-defs.h" 26 #include "qemu/cpu-float.h" 27 #include "qom/object.h" 28 #include "qemu/int128.h" 29 #include "cpu_bits.h" 30 31 #define TCG_GUEST_DEFAULT_MO 0 32 33 /* 34 * RISC-V-specific extra insn start words: 35 * 1: Original instruction opcode 36 */ 37 #define TARGET_INSN_START_EXTRA_WORDS 1 38 39 #define TYPE_RISCV_CPU "riscv-cpu" 40 41 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU 42 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) 43 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU 44 45 #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") 46 #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") 47 #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") 48 #define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128") 49 #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") 50 #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") 51 #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") 52 #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") 53 #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") 54 #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") 55 #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") 56 #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") 57 58 #if defined(TARGET_RISCV32) 59 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 60 #elif defined(TARGET_RISCV64) 61 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 62 #endif 63 64 #define RV(x) ((target_ulong)1 << (x - 'A')) 65 66 #define RVI RV('I') 67 #define RVE RV('E') /* E and I are mutually exclusive */ 68 #define RVM RV('M') 69 #define RVA RV('A') 70 #define RVF RV('F') 71 #define RVD RV('D') 72 #define RVV RV('V') 73 #define RVC RV('C') 74 #define RVS RV('S') 75 #define RVU RV('U') 76 #define RVH RV('H') 77 #define RVJ RV('J') 78 79 /* S extension denotes that Supervisor mode exists, however it is possible 80 to have a core that support S mode but does not have an MMU and there 81 is currently no bit in misa to indicate whether an MMU exists or not 82 so a cpu features bitfield is required, likewise for optional PMP support */ 83 enum { 84 RISCV_FEATURE_MMU, 85 RISCV_FEATURE_PMP, 86 RISCV_FEATURE_EPMP, 87 RISCV_FEATURE_MISA, 88 RISCV_FEATURE_AIA, 89 RISCV_FEATURE_DEBUG 90 }; 91 92 /* Privileged specification version */ 93 enum { 94 PRIV_VERSION_1_10_0 = 0, 95 PRIV_VERSION_1_11_0, 96 PRIV_VERSION_1_12_0, 97 }; 98 99 #define VEXT_VERSION_1_00_0 0x00010000 100 101 enum { 102 TRANSLATE_SUCCESS, 103 TRANSLATE_FAIL, 104 TRANSLATE_PMP_FAIL, 105 TRANSLATE_G_STAGE_FAIL 106 }; 107 108 #define MMU_USER_IDX 3 109 110 #define MAX_RISCV_PMPS (16) 111 112 typedef struct CPUArchState CPURISCVState; 113 114 #if !defined(CONFIG_USER_ONLY) 115 #include "pmp.h" 116 #include "debug.h" 117 #endif 118 119 #define RV_VLEN_MAX 1024 120 121 FIELD(VTYPE, VLMUL, 0, 3) 122 FIELD(VTYPE, VSEW, 3, 3) 123 FIELD(VTYPE, VTA, 6, 1) 124 FIELD(VTYPE, VMA, 7, 1) 125 FIELD(VTYPE, VEDIV, 8, 2) 126 FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) 127 128 struct CPUArchState { 129 target_ulong gpr[32]; 130 target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ 131 uint64_t fpr[32]; /* assume both F and D extensions */ 132 133 /* vector coprocessor state. */ 134 uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); 135 target_ulong vxrm; 136 target_ulong vxsat; 137 target_ulong vl; 138 target_ulong vstart; 139 target_ulong vtype; 140 bool vill; 141 142 target_ulong pc; 143 target_ulong load_res; 144 target_ulong load_val; 145 146 target_ulong frm; 147 148 target_ulong badaddr; 149 target_ulong bins; 150 151 target_ulong guest_phys_fault_addr; 152 153 target_ulong priv_ver; 154 target_ulong bext_ver; 155 target_ulong vext_ver; 156 157 /* RISCVMXL, but uint32_t for vmstate migration */ 158 uint32_t misa_mxl; /* current mxl */ 159 uint32_t misa_mxl_max; /* max mxl for this cpu */ 160 uint32_t misa_ext; /* current extensions */ 161 uint32_t misa_ext_mask; /* max ext for this cpu */ 162 uint32_t xl; /* current xlen */ 163 164 /* 128-bit helpers upper part return value */ 165 target_ulong retxh; 166 167 uint32_t features; 168 169 #ifdef CONFIG_USER_ONLY 170 uint32_t elf_flags; 171 #endif 172 173 #ifndef CONFIG_USER_ONLY 174 target_ulong priv; 175 /* This contains QEMU specific information about the virt state. */ 176 target_ulong virt; 177 target_ulong geilen; 178 target_ulong resetvec; 179 180 target_ulong mhartid; 181 /* 182 * For RV32 this is 32-bit mstatus and 32-bit mstatush. 183 * For RV64 this is a 64-bit mstatus. 184 */ 185 uint64_t mstatus; 186 187 uint64_t mip; 188 /* 189 * MIP contains the software writable version of SEIP ORed with the 190 * external interrupt value. The MIP register is always up-to-date. 191 * To keep track of the current source, we also save booleans of the values 192 * here. 193 */ 194 bool external_seip; 195 bool software_seip; 196 197 uint64_t miclaim; 198 199 uint64_t mie; 200 uint64_t mideleg; 201 202 target_ulong satp; /* since: priv-1.10.0 */ 203 target_ulong stval; 204 target_ulong medeleg; 205 206 target_ulong stvec; 207 target_ulong sepc; 208 target_ulong scause; 209 210 target_ulong mtvec; 211 target_ulong mepc; 212 target_ulong mcause; 213 target_ulong mtval; /* since: priv-1.10.0 */ 214 215 /* Machine and Supervisor interrupt priorities */ 216 uint8_t miprio[64]; 217 uint8_t siprio[64]; 218 219 /* AIA CSRs */ 220 target_ulong miselect; 221 target_ulong siselect; 222 223 /* Hypervisor CSRs */ 224 target_ulong hstatus; 225 target_ulong hedeleg; 226 uint64_t hideleg; 227 target_ulong hcounteren; 228 target_ulong htval; 229 target_ulong htinst; 230 target_ulong hgatp; 231 target_ulong hgeie; 232 target_ulong hgeip; 233 uint64_t htimedelta; 234 235 /* Hypervisor controlled virtual interrupt priorities */ 236 target_ulong hvictl; 237 uint8_t hviprio[64]; 238 239 /* Upper 64-bits of 128-bit CSRs */ 240 uint64_t mscratchh; 241 uint64_t sscratchh; 242 243 /* Virtual CSRs */ 244 /* 245 * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. 246 * For RV64 this is a 64-bit vsstatus. 247 */ 248 uint64_t vsstatus; 249 target_ulong vstvec; 250 target_ulong vsscratch; 251 target_ulong vsepc; 252 target_ulong vscause; 253 target_ulong vstval; 254 target_ulong vsatp; 255 256 /* AIA VS-mode CSRs */ 257 target_ulong vsiselect; 258 259 target_ulong mtval2; 260 target_ulong mtinst; 261 262 /* HS Backup CSRs */ 263 target_ulong stvec_hs; 264 target_ulong sscratch_hs; 265 target_ulong sepc_hs; 266 target_ulong scause_hs; 267 target_ulong stval_hs; 268 target_ulong satp_hs; 269 uint64_t mstatus_hs; 270 271 /* Signals whether the current exception occurred with two-stage address 272 translation active. */ 273 bool two_stage_lookup; 274 275 target_ulong scounteren; 276 target_ulong mcounteren; 277 278 target_ulong mcountinhibit; 279 280 target_ulong sscratch; 281 target_ulong mscratch; 282 283 /* temporary htif regs */ 284 uint64_t mfromhost; 285 uint64_t mtohost; 286 uint64_t timecmp; 287 288 /* physical memory protection */ 289 pmp_table_t pmp_state; 290 target_ulong mseccfg; 291 292 /* trigger module */ 293 target_ulong trigger_cur; 294 type2_trigger_t type2_trig[TRIGGER_TYPE2_NUM]; 295 296 /* machine specific rdtime callback */ 297 uint64_t (*rdtime_fn)(void *); 298 void *rdtime_fn_arg; 299 300 /* machine specific AIA ireg read-modify-write callback */ 301 #define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \ 302 ((((__xlen) & 0xff) << 24) | \ 303 (((__vgein) & 0x3f) << 20) | \ 304 (((__virt) & 0x1) << 18) | \ 305 (((__priv) & 0x3) << 16) | \ 306 (__isel & 0xffff)) 307 #define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff) 308 #define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3) 309 #define AIA_IREG_VIRT(__ireg) (((__ireg) >> 18) & 0x1) 310 #define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 20) & 0x3f) 311 #define AIA_IREG_XLEN(__ireg) (((__ireg) >> 24) & 0xff) 312 int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg, 313 target_ulong *val, target_ulong new_val, target_ulong write_mask); 314 void *aia_ireg_rmw_fn_arg[4]; 315 316 /* True if in debugger mode. */ 317 bool debugger; 318 319 /* 320 * CSRs for PointerMasking extension 321 */ 322 target_ulong mmte; 323 target_ulong mpmmask; 324 target_ulong mpmbase; 325 target_ulong spmmask; 326 target_ulong spmbase; 327 target_ulong upmmask; 328 target_ulong upmbase; 329 330 /* CSRs for execution enviornment configuration */ 331 uint64_t menvcfg; 332 target_ulong senvcfg; 333 uint64_t henvcfg; 334 #endif 335 target_ulong cur_pmmask; 336 target_ulong cur_pmbase; 337 338 float_status fp_status; 339 340 /* Fields from here on are preserved across CPU reset. */ 341 QEMUTimer *timer; /* Internal timer */ 342 343 hwaddr kernel_addr; 344 hwaddr fdt_addr; 345 346 /* kvm timer */ 347 bool kvm_timer_dirty; 348 uint64_t kvm_timer_time; 349 uint64_t kvm_timer_compare; 350 uint64_t kvm_timer_state; 351 uint64_t kvm_timer_frequency; 352 }; 353 354 OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) 355 356 /** 357 * RISCVCPUClass: 358 * @parent_realize: The parent class' realize handler. 359 * @parent_reset: The parent class' reset handler. 360 * 361 * A RISCV CPU model. 362 */ 363 struct RISCVCPUClass { 364 /*< private >*/ 365 CPUClass parent_class; 366 /*< public >*/ 367 DeviceRealize parent_realize; 368 DeviceReset parent_reset; 369 }; 370 371 struct RISCVCPUConfig { 372 bool ext_i; 373 bool ext_e; 374 bool ext_g; 375 bool ext_m; 376 bool ext_a; 377 bool ext_f; 378 bool ext_d; 379 bool ext_c; 380 bool ext_s; 381 bool ext_u; 382 bool ext_h; 383 bool ext_j; 384 bool ext_v; 385 bool ext_zba; 386 bool ext_zbb; 387 bool ext_zbc; 388 bool ext_zbkb; 389 bool ext_zbkc; 390 bool ext_zbkx; 391 bool ext_zbs; 392 bool ext_zk; 393 bool ext_zkn; 394 bool ext_zknd; 395 bool ext_zkne; 396 bool ext_zknh; 397 bool ext_zkr; 398 bool ext_zks; 399 bool ext_zksed; 400 bool ext_zksh; 401 bool ext_zkt; 402 bool ext_ifencei; 403 bool ext_icsr; 404 bool ext_svinval; 405 bool ext_svnapot; 406 bool ext_svpbmt; 407 bool ext_zdinx; 408 bool ext_zfh; 409 bool ext_zfhmin; 410 bool ext_zfinx; 411 bool ext_zhinx; 412 bool ext_zhinxmin; 413 bool ext_zve32f; 414 bool ext_zve64f; 415 bool ext_zmmul; 416 bool rvv_ta_all_1s; 417 418 uint32_t mvendorid; 419 uint64_t marchid; 420 uint64_t mimpid; 421 422 /* Vendor-specific custom extensions */ 423 bool ext_XVentanaCondOps; 424 425 uint8_t pmu_num; 426 char *priv_spec; 427 char *user_spec; 428 char *bext_spec; 429 char *vext_spec; 430 uint16_t vlen; 431 uint16_t elen; 432 bool mmu; 433 bool pmp; 434 bool epmp; 435 bool aia; 436 bool debug; 437 uint64_t resetvec; 438 439 bool short_isa_string; 440 }; 441 442 typedef struct RISCVCPUConfig RISCVCPUConfig; 443 444 /** 445 * RISCVCPU: 446 * @env: #CPURISCVState 447 * 448 * A RISCV CPU. 449 */ 450 struct ArchCPU { 451 /*< private >*/ 452 CPUState parent_obj; 453 /*< public >*/ 454 CPUNegativeOffsetState neg; 455 CPURISCVState env; 456 457 char *dyn_csr_xml; 458 char *dyn_vreg_xml; 459 460 /* Configuration Settings */ 461 RISCVCPUConfig cfg; 462 }; 463 464 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) 465 { 466 return (env->misa_ext & ext) != 0; 467 } 468 469 static inline bool riscv_feature(CPURISCVState *env, int feature) 470 { 471 return env->features & (1ULL << feature); 472 } 473 474 static inline void riscv_set_feature(CPURISCVState *env, int feature) 475 { 476 env->features |= (1ULL << feature); 477 } 478 479 #include "cpu_user.h" 480 481 extern const char * const riscv_int_regnames[]; 482 extern const char * const riscv_int_regnamesh[]; 483 extern const char * const riscv_fpr_regnames[]; 484 485 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); 486 void riscv_cpu_do_interrupt(CPUState *cpu); 487 int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 488 int cpuid, void *opaque); 489 int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 490 int cpuid, void *opaque); 491 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 492 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 493 int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero); 494 uint8_t riscv_cpu_default_priority(int irq); 495 uint64_t riscv_cpu_all_pending(CPURISCVState *env); 496 int riscv_cpu_mirq_pending(CPURISCVState *env); 497 int riscv_cpu_sirq_pending(CPURISCVState *env); 498 int riscv_cpu_vsirq_pending(CPURISCVState *env); 499 bool riscv_cpu_fp_enabled(CPURISCVState *env); 500 target_ulong riscv_cpu_get_geilen(CPURISCVState *env); 501 void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); 502 bool riscv_cpu_vector_enabled(CPURISCVState *env); 503 bool riscv_cpu_virt_enabled(CPURISCVState *env); 504 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); 505 bool riscv_cpu_two_stage_lookup(int mmu_idx); 506 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); 507 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 508 G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 509 MMUAccessType access_type, int mmu_idx, 510 uintptr_t retaddr); 511 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 512 MMUAccessType access_type, int mmu_idx, 513 bool probe, uintptr_t retaddr); 514 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 515 vaddr addr, unsigned size, 516 MMUAccessType access_type, 517 int mmu_idx, MemTxAttrs attrs, 518 MemTxResult response, uintptr_t retaddr); 519 char *riscv_isa_string(RISCVCPU *cpu); 520 void riscv_cpu_list(void); 521 522 #define cpu_list riscv_cpu_list 523 #define cpu_mmu_index riscv_cpu_mmu_index 524 525 #ifndef CONFIG_USER_ONLY 526 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); 527 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); 528 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); 529 uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value); 530 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ 531 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), 532 void *arg); 533 void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, 534 int (*rmw_fn)(void *arg, 535 target_ulong reg, 536 target_ulong *val, 537 target_ulong new_val, 538 target_ulong write_mask), 539 void *rmw_fn_arg); 540 #endif 541 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); 542 543 void riscv_translate_init(void); 544 G_NORETURN void riscv_raise_exception(CPURISCVState *env, 545 uint32_t exception, uintptr_t pc); 546 547 target_ulong riscv_cpu_get_fflags(CPURISCVState *env); 548 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); 549 550 #define TB_FLAGS_PRIV_MMU_MASK 3 551 #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2) 552 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS 553 #define TB_FLAGS_MSTATUS_VS MSTATUS_VS 554 555 #include "exec/cpu-all.h" 556 557 FIELD(TB_FLAGS, MEM_IDX, 0, 3) 558 FIELD(TB_FLAGS, LMUL, 3, 3) 559 FIELD(TB_FLAGS, SEW, 6, 3) 560 /* Skip MSTATUS_VS (0x600) bits */ 561 FIELD(TB_FLAGS, VL_EQ_VLMAX, 11, 1) 562 FIELD(TB_FLAGS, VILL, 12, 1) 563 /* Skip MSTATUS_FS (0x6000) bits */ 564 /* Is a Hypervisor instruction load/store allowed? */ 565 FIELD(TB_FLAGS, HLSX, 15, 1) 566 FIELD(TB_FLAGS, MSTATUS_HS_FS, 16, 2) 567 FIELD(TB_FLAGS, MSTATUS_HS_VS, 18, 2) 568 /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ 569 FIELD(TB_FLAGS, XL, 20, 2) 570 /* If PointerMasking should be applied */ 571 FIELD(TB_FLAGS, PM_MASK_ENABLED, 22, 1) 572 FIELD(TB_FLAGS, PM_BASE_ENABLED, 23, 1) 573 FIELD(TB_FLAGS, VTA, 24, 1) 574 575 #ifdef TARGET_RISCV32 576 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) 577 #else 578 static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) 579 { 580 return env->misa_mxl; 581 } 582 #endif 583 #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env))) 584 585 #if defined(TARGET_RISCV32) 586 #define cpu_recompute_xl(env) ((void)(env), MXL_RV32) 587 #else 588 static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) 589 { 590 RISCVMXL xl = env->misa_mxl; 591 #if !defined(CONFIG_USER_ONLY) 592 /* 593 * When emulating a 32-bit-only cpu, use RV32. 594 * When emulating a 64-bit cpu, and MXL has been reduced to RV32, 595 * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened 596 * back to RV64 for lower privs. 597 */ 598 if (xl != MXL_RV32) { 599 switch (env->priv) { 600 case PRV_M: 601 break; 602 case PRV_U: 603 xl = get_field(env->mstatus, MSTATUS64_UXL); 604 break; 605 default: /* PRV_S | PRV_H */ 606 xl = get_field(env->mstatus, MSTATUS64_SXL); 607 break; 608 } 609 } 610 #endif 611 return xl; 612 } 613 #endif 614 615 static inline int riscv_cpu_xlen(CPURISCVState *env) 616 { 617 return 16 << env->xl; 618 } 619 620 #ifdef TARGET_RISCV32 621 #define riscv_cpu_sxl(env) ((void)(env), MXL_RV32) 622 #else 623 static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env) 624 { 625 #ifdef CONFIG_USER_ONLY 626 return env->misa_mxl; 627 #else 628 return get_field(env->mstatus, MSTATUS64_SXL); 629 #endif 630 } 631 #endif 632 633 /* 634 * Encode LMUL to lmul as follows: 635 * LMUL vlmul lmul 636 * 1 000 0 637 * 2 001 1 638 * 4 010 2 639 * 8 011 3 640 * - 100 - 641 * 1/8 101 -3 642 * 1/4 110 -2 643 * 1/2 111 -1 644 * 645 * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul) 646 * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8 647 * => VLMAX = vlen >> (1 + 3 - (-3)) 648 * = 256 >> 7 649 * = 2 650 */ 651 static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) 652 { 653 uint8_t sew = FIELD_EX64(vtype, VTYPE, VSEW); 654 int8_t lmul = sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3); 655 return cpu->cfg.vlen >> (sew + 3 - lmul); 656 } 657 658 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 659 target_ulong *cs_base, uint32_t *pflags); 660 661 void riscv_cpu_update_mask(CPURISCVState *env); 662 663 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, 664 target_ulong *ret_value, 665 target_ulong new_value, target_ulong write_mask); 666 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, 667 target_ulong *ret_value, 668 target_ulong new_value, 669 target_ulong write_mask); 670 671 static inline void riscv_csr_write(CPURISCVState *env, int csrno, 672 target_ulong val) 673 { 674 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); 675 } 676 677 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) 678 { 679 target_ulong val = 0; 680 riscv_csrrw(env, csrno, &val, 0, 0); 681 return val; 682 } 683 684 typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, 685 int csrno); 686 typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, 687 target_ulong *ret_value); 688 typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, 689 target_ulong new_value); 690 typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, 691 target_ulong *ret_value, 692 target_ulong new_value, 693 target_ulong write_mask); 694 695 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, 696 Int128 *ret_value, 697 Int128 new_value, Int128 write_mask); 698 699 typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno, 700 Int128 *ret_value); 701 typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int csrno, 702 Int128 new_value); 703 704 typedef struct { 705 const char *name; 706 riscv_csr_predicate_fn predicate; 707 riscv_csr_read_fn read; 708 riscv_csr_write_fn write; 709 riscv_csr_op_fn op; 710 riscv_csr_read128_fn read128; 711 riscv_csr_write128_fn write128; 712 /* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0) */ 713 uint32_t min_priv_ver; 714 } riscv_csr_operations; 715 716 /* CSR function table constants */ 717 enum { 718 CSR_TABLE_SIZE = 0x1000 719 }; 720 721 /* CSR function table */ 722 extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; 723 724 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); 725 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); 726 727 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); 728 729 #endif /* RISCV_CPU_H */ 730