1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef RISCV_CPU_H 21 #define RISCV_CPU_H 22 23 #include "hw/core/cpu.h" 24 #include "exec/cpu-defs.h" 25 #include "fpu/softfloat-types.h" 26 27 #define TCG_GUEST_DEFAULT_MO 0 28 29 #define TYPE_RISCV_CPU "riscv-cpu" 30 31 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU 32 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) 33 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU 34 35 #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") 36 #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") 37 #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") 38 #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") 39 #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") 40 #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") 41 #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") 42 #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") 43 #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") 44 45 #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2)) 46 #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2)) 47 48 #if defined(TARGET_RISCV32) 49 #define RVXLEN RV32 50 #elif defined(TARGET_RISCV64) 51 #define RVXLEN RV64 52 #endif 53 54 #define RV(x) ((target_ulong)1 << (x - 'A')) 55 56 #define RVI RV('I') 57 #define RVE RV('E') /* E and I are mutually exclusive */ 58 #define RVM RV('M') 59 #define RVA RV('A') 60 #define RVF RV('F') 61 #define RVD RV('D') 62 #define RVV RV('V') 63 #define RVC RV('C') 64 #define RVS RV('S') 65 #define RVU RV('U') 66 #define RVH RV('H') 67 68 /* S extension denotes that Supervisor mode exists, however it is possible 69 to have a core that support S mode but does not have an MMU and there 70 is currently no bit in misa to indicate whether an MMU exists or not 71 so a cpu features bitfield is required, likewise for optional PMP support */ 72 enum { 73 RISCV_FEATURE_MMU, 74 RISCV_FEATURE_PMP, 75 RISCV_FEATURE_MISA 76 }; 77 78 #define PRIV_VERSION_1_10_0 0x00011000 79 #define PRIV_VERSION_1_11_0 0x00011100 80 81 #define TRANSLATE_PMP_FAIL 2 82 #define TRANSLATE_FAIL 1 83 #define TRANSLATE_SUCCESS 0 84 #define MMU_USER_IDX 3 85 86 #define MAX_RISCV_PMPS (16) 87 88 typedef struct CPURISCVState CPURISCVState; 89 90 #include "pmp.h" 91 92 #define RV_VLEN_MAX 512 93 94 struct CPURISCVState { 95 target_ulong gpr[32]; 96 uint64_t fpr[32]; /* assume both F and D extensions */ 97 98 /* vector coprocessor state. */ 99 uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); 100 target_ulong vxrm; 101 target_ulong vxsat; 102 target_ulong vl; 103 target_ulong vstart; 104 target_ulong vtype; 105 106 target_ulong pc; 107 target_ulong load_res; 108 target_ulong load_val; 109 110 target_ulong frm; 111 112 target_ulong badaddr; 113 target_ulong guest_phys_fault_addr; 114 115 target_ulong priv_ver; 116 target_ulong misa; 117 target_ulong misa_mask; 118 119 uint32_t features; 120 121 #ifdef CONFIG_USER_ONLY 122 uint32_t elf_flags; 123 #endif 124 125 #ifndef CONFIG_USER_ONLY 126 target_ulong priv; 127 /* This contains QEMU specific information about the virt state. */ 128 target_ulong virt; 129 target_ulong resetvec; 130 131 target_ulong mhartid; 132 target_ulong mstatus; 133 134 target_ulong mip; 135 136 #ifdef TARGET_RISCV32 137 target_ulong mstatush; 138 #endif 139 140 uint32_t miclaim; 141 142 target_ulong mie; 143 target_ulong mideleg; 144 145 target_ulong sptbr; /* until: priv-1.9.1 */ 146 target_ulong satp; /* since: priv-1.10.0 */ 147 target_ulong sbadaddr; 148 target_ulong mbadaddr; 149 target_ulong medeleg; 150 151 target_ulong stvec; 152 target_ulong sepc; 153 target_ulong scause; 154 155 target_ulong mtvec; 156 target_ulong mepc; 157 target_ulong mcause; 158 target_ulong mtval; /* since: priv-1.10.0 */ 159 160 /* Hypervisor CSRs */ 161 target_ulong hstatus; 162 target_ulong hedeleg; 163 target_ulong hideleg; 164 target_ulong hcounteren; 165 target_ulong htval; 166 target_ulong htinst; 167 target_ulong hgatp; 168 uint64_t htimedelta; 169 170 /* Virtual CSRs */ 171 target_ulong vsstatus; 172 target_ulong vstvec; 173 target_ulong vsscratch; 174 target_ulong vsepc; 175 target_ulong vscause; 176 target_ulong vstval; 177 target_ulong vsatp; 178 #ifdef TARGET_RISCV32 179 target_ulong vsstatush; 180 #endif 181 182 target_ulong mtval2; 183 target_ulong mtinst; 184 185 /* HS Backup CSRs */ 186 target_ulong stvec_hs; 187 target_ulong sscratch_hs; 188 target_ulong sepc_hs; 189 target_ulong scause_hs; 190 target_ulong stval_hs; 191 target_ulong satp_hs; 192 target_ulong mstatus_hs; 193 #ifdef TARGET_RISCV32 194 target_ulong mstatush_hs; 195 #endif 196 197 target_ulong scounteren; 198 target_ulong mcounteren; 199 200 target_ulong sscratch; 201 target_ulong mscratch; 202 203 /* temporary htif regs */ 204 uint64_t mfromhost; 205 uint64_t mtohost; 206 uint64_t timecmp; 207 208 /* physical memory protection */ 209 pmp_table_t pmp_state; 210 211 /* machine specific rdtime callback */ 212 uint64_t (*rdtime_fn)(void); 213 214 /* True if in debugger mode. */ 215 bool debugger; 216 #endif 217 218 float_status fp_status; 219 220 /* Fields from here on are preserved across CPU reset. */ 221 QEMUTimer *timer; /* Internal timer */ 222 }; 223 224 #define RISCV_CPU_CLASS(klass) \ 225 OBJECT_CLASS_CHECK(RISCVCPUClass, (klass), TYPE_RISCV_CPU) 226 #define RISCV_CPU(obj) \ 227 OBJECT_CHECK(RISCVCPU, (obj), TYPE_RISCV_CPU) 228 #define RISCV_CPU_GET_CLASS(obj) \ 229 OBJECT_GET_CLASS(RISCVCPUClass, (obj), TYPE_RISCV_CPU) 230 231 /** 232 * RISCVCPUClass: 233 * @parent_realize: The parent class' realize handler. 234 * @parent_reset: The parent class' reset handler. 235 * 236 * A RISCV CPU model. 237 */ 238 typedef struct RISCVCPUClass { 239 /*< private >*/ 240 CPUClass parent_class; 241 /*< public >*/ 242 DeviceRealize parent_realize; 243 DeviceReset parent_reset; 244 } RISCVCPUClass; 245 246 /** 247 * RISCVCPU: 248 * @env: #CPURISCVState 249 * 250 * A RISCV CPU. 251 */ 252 typedef struct RISCVCPU { 253 /*< private >*/ 254 CPUState parent_obj; 255 /*< public >*/ 256 CPUNegativeOffsetState neg; 257 CPURISCVState env; 258 259 /* Configuration Settings */ 260 struct { 261 bool ext_i; 262 bool ext_e; 263 bool ext_g; 264 bool ext_m; 265 bool ext_a; 266 bool ext_f; 267 bool ext_d; 268 bool ext_c; 269 bool ext_s; 270 bool ext_u; 271 bool ext_h; 272 bool ext_counters; 273 bool ext_ifencei; 274 bool ext_icsr; 275 276 char *priv_spec; 277 char *user_spec; 278 bool mmu; 279 bool pmp; 280 } cfg; 281 } RISCVCPU; 282 283 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) 284 { 285 return (env->misa & ext) != 0; 286 } 287 288 static inline bool riscv_feature(CPURISCVState *env, int feature) 289 { 290 return env->features & (1ULL << feature); 291 } 292 293 #include "cpu_user.h" 294 #include "cpu_bits.h" 295 296 extern const char * const riscv_int_regnames[]; 297 extern const char * const riscv_fpr_regnames[]; 298 extern const char * const riscv_excp_names[]; 299 extern const char * const riscv_intr_names[]; 300 301 void riscv_cpu_do_interrupt(CPUState *cpu); 302 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 303 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 304 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); 305 bool riscv_cpu_fp_enabled(CPURISCVState *env); 306 bool riscv_cpu_virt_enabled(CPURISCVState *env); 307 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); 308 bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env); 309 void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable); 310 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); 311 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 312 void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 313 MMUAccessType access_type, int mmu_idx, 314 uintptr_t retaddr); 315 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 316 MMUAccessType access_type, int mmu_idx, 317 bool probe, uintptr_t retaddr); 318 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 319 vaddr addr, unsigned size, 320 MMUAccessType access_type, 321 int mmu_idx, MemTxAttrs attrs, 322 MemTxResult response, uintptr_t retaddr); 323 char *riscv_isa_string(RISCVCPU *cpu); 324 void riscv_cpu_list(void); 325 326 #define cpu_signal_handler riscv_cpu_signal_handler 327 #define cpu_list riscv_cpu_list 328 #define cpu_mmu_index riscv_cpu_mmu_index 329 330 #ifndef CONFIG_USER_ONLY 331 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); 332 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts); 333 uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value); 334 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ 335 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void)); 336 #endif 337 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); 338 339 void riscv_translate_init(void); 340 int riscv_cpu_signal_handler(int host_signum, void *pinfo, void *puc); 341 void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env, 342 uint32_t exception, uintptr_t pc); 343 344 target_ulong riscv_cpu_get_fflags(CPURISCVState *env); 345 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); 346 347 #define TB_FLAGS_MMU_MASK 3 348 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS 349 350 static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 351 target_ulong *cs_base, uint32_t *flags) 352 { 353 *pc = env->pc; 354 *cs_base = 0; 355 #ifdef CONFIG_USER_ONLY 356 *flags = TB_FLAGS_MSTATUS_FS; 357 #else 358 *flags = cpu_mmu_index(env, 0); 359 if (riscv_cpu_fp_enabled(env)) { 360 *flags |= env->mstatus & MSTATUS_FS; 361 } 362 #endif 363 } 364 365 int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, 366 target_ulong new_value, target_ulong write_mask); 367 int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value, 368 target_ulong new_value, target_ulong write_mask); 369 370 static inline void riscv_csr_write(CPURISCVState *env, int csrno, 371 target_ulong val) 372 { 373 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); 374 } 375 376 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) 377 { 378 target_ulong val = 0; 379 riscv_csrrw(env, csrno, &val, 0, 0); 380 return val; 381 } 382 383 typedef int (*riscv_csr_predicate_fn)(CPURISCVState *env, int csrno); 384 typedef int (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, 385 target_ulong *ret_value); 386 typedef int (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, 387 target_ulong new_value); 388 typedef int (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, 389 target_ulong *ret_value, target_ulong new_value, target_ulong write_mask); 390 391 typedef struct { 392 riscv_csr_predicate_fn predicate; 393 riscv_csr_read_fn read; 394 riscv_csr_write_fn write; 395 riscv_csr_op_fn op; 396 } riscv_csr_operations; 397 398 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); 399 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); 400 401 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); 402 403 typedef CPURISCVState CPUArchState; 404 typedef RISCVCPU ArchCPU; 405 406 #include "exec/cpu-all.h" 407 408 #endif /* RISCV_CPU_H */ 409