1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef RISCV_CPU_H 21 #define RISCV_CPU_H 22 23 #include "hw/core/cpu.h" 24 #include "hw/registerfields.h" 25 #include "exec/cpu-defs.h" 26 #include "fpu/softfloat-types.h" 27 #include "qom/object.h" 28 #include "cpu_bits.h" 29 30 #define TCG_GUEST_DEFAULT_MO 0 31 32 #define TYPE_RISCV_CPU "riscv-cpu" 33 34 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU 35 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) 36 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU 37 38 #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") 39 #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") 40 #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") 41 #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") 42 #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") 43 #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") 44 #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") 45 #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") 46 #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") 47 #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") 48 49 #if defined(TARGET_RISCV32) 50 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 51 #elif defined(TARGET_RISCV64) 52 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 53 #endif 54 55 #define RV(x) ((target_ulong)1 << (x - 'A')) 56 57 #define RVI RV('I') 58 #define RVE RV('E') /* E and I are mutually exclusive */ 59 #define RVM RV('M') 60 #define RVA RV('A') 61 #define RVF RV('F') 62 #define RVD RV('D') 63 #define RVV RV('V') 64 #define RVC RV('C') 65 #define RVS RV('S') 66 #define RVU RV('U') 67 #define RVH RV('H') 68 #define RVJ RV('J') 69 70 /* S extension denotes that Supervisor mode exists, however it is possible 71 to have a core that support S mode but does not have an MMU and there 72 is currently no bit in misa to indicate whether an MMU exists or not 73 so a cpu features bitfield is required, likewise for optional PMP support */ 74 enum { 75 RISCV_FEATURE_MMU, 76 RISCV_FEATURE_PMP, 77 RISCV_FEATURE_EPMP, 78 RISCV_FEATURE_MISA 79 }; 80 81 #define PRIV_VERSION_1_10_0 0x00011000 82 #define PRIV_VERSION_1_11_0 0x00011100 83 84 #define VEXT_VERSION_1_00_0 0x00010000 85 86 enum { 87 TRANSLATE_SUCCESS, 88 TRANSLATE_FAIL, 89 TRANSLATE_PMP_FAIL, 90 TRANSLATE_G_STAGE_FAIL 91 }; 92 93 #define MMU_USER_IDX 3 94 95 #define MAX_RISCV_PMPS (16) 96 97 typedef struct CPURISCVState CPURISCVState; 98 99 #if !defined(CONFIG_USER_ONLY) 100 #include "pmp.h" 101 #endif 102 103 #define RV_VLEN_MAX 256 104 105 FIELD(VTYPE, VLMUL, 0, 2) 106 FIELD(VTYPE, VSEW, 2, 3) 107 FIELD(VTYPE, VEDIV, 5, 2) 108 FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 9) 109 FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1) 110 111 struct CPURISCVState { 112 target_ulong gpr[32]; 113 uint64_t fpr[32]; /* assume both F and D extensions */ 114 115 /* vector coprocessor state. */ 116 uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); 117 target_ulong vxrm; 118 target_ulong vxsat; 119 target_ulong vl; 120 target_ulong vstart; 121 target_ulong vtype; 122 123 target_ulong pc; 124 target_ulong load_res; 125 target_ulong load_val; 126 127 target_ulong frm; 128 129 target_ulong badaddr; 130 target_ulong guest_phys_fault_addr; 131 132 target_ulong priv_ver; 133 target_ulong bext_ver; 134 target_ulong vext_ver; 135 136 /* RISCVMXL, but uint32_t for vmstate migration */ 137 uint32_t misa_mxl; /* current mxl */ 138 uint32_t misa_mxl_max; /* max mxl for this cpu */ 139 uint32_t misa_ext; /* current extensions */ 140 uint32_t misa_ext_mask; /* max ext for this cpu */ 141 142 uint32_t features; 143 144 #ifdef CONFIG_USER_ONLY 145 uint32_t elf_flags; 146 #endif 147 148 #ifndef CONFIG_USER_ONLY 149 target_ulong priv; 150 /* This contains QEMU specific information about the virt state. */ 151 target_ulong virt; 152 target_ulong resetvec; 153 154 target_ulong mhartid; 155 /* 156 * For RV32 this is 32-bit mstatus and 32-bit mstatush. 157 * For RV64 this is a 64-bit mstatus. 158 */ 159 uint64_t mstatus; 160 161 target_ulong mip; 162 163 uint32_t miclaim; 164 165 target_ulong mie; 166 target_ulong mideleg; 167 168 target_ulong satp; /* since: priv-1.10.0 */ 169 target_ulong stval; 170 target_ulong medeleg; 171 172 target_ulong stvec; 173 target_ulong sepc; 174 target_ulong scause; 175 176 target_ulong mtvec; 177 target_ulong mepc; 178 target_ulong mcause; 179 target_ulong mtval; /* since: priv-1.10.0 */ 180 181 /* Hypervisor CSRs */ 182 target_ulong hstatus; 183 target_ulong hedeleg; 184 target_ulong hideleg; 185 target_ulong hcounteren; 186 target_ulong htval; 187 target_ulong htinst; 188 target_ulong hgatp; 189 uint64_t htimedelta; 190 191 /* Virtual CSRs */ 192 /* 193 * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. 194 * For RV64 this is a 64-bit vsstatus. 195 */ 196 uint64_t vsstatus; 197 target_ulong vstvec; 198 target_ulong vsscratch; 199 target_ulong vsepc; 200 target_ulong vscause; 201 target_ulong vstval; 202 target_ulong vsatp; 203 204 target_ulong mtval2; 205 target_ulong mtinst; 206 207 /* HS Backup CSRs */ 208 target_ulong stvec_hs; 209 target_ulong sscratch_hs; 210 target_ulong sepc_hs; 211 target_ulong scause_hs; 212 target_ulong stval_hs; 213 target_ulong satp_hs; 214 uint64_t mstatus_hs; 215 216 /* Signals whether the current exception occurred with two-stage address 217 translation active. */ 218 bool two_stage_lookup; 219 220 target_ulong scounteren; 221 target_ulong mcounteren; 222 223 target_ulong sscratch; 224 target_ulong mscratch; 225 226 /* temporary htif regs */ 227 uint64_t mfromhost; 228 uint64_t mtohost; 229 uint64_t timecmp; 230 231 /* physical memory protection */ 232 pmp_table_t pmp_state; 233 target_ulong mseccfg; 234 235 /* machine specific rdtime callback */ 236 uint64_t (*rdtime_fn)(uint32_t); 237 uint32_t rdtime_fn_arg; 238 239 /* True if in debugger mode. */ 240 bool debugger; 241 242 /* 243 * CSRs for PointerMasking extension 244 */ 245 target_ulong mmte; 246 target_ulong mpmmask; 247 target_ulong mpmbase; 248 target_ulong spmmask; 249 target_ulong spmbase; 250 target_ulong upmmask; 251 target_ulong upmbase; 252 #endif 253 254 float_status fp_status; 255 256 /* Fields from here on are preserved across CPU reset. */ 257 QEMUTimer *timer; /* Internal timer */ 258 }; 259 260 OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass, 261 RISCV_CPU) 262 263 /** 264 * RISCVCPUClass: 265 * @parent_realize: The parent class' realize handler. 266 * @parent_reset: The parent class' reset handler. 267 * 268 * A RISCV CPU model. 269 */ 270 struct RISCVCPUClass { 271 /*< private >*/ 272 CPUClass parent_class; 273 /*< public >*/ 274 DeviceRealize parent_realize; 275 DeviceReset parent_reset; 276 }; 277 278 /** 279 * RISCVCPU: 280 * @env: #CPURISCVState 281 * 282 * A RISCV CPU. 283 */ 284 struct RISCVCPU { 285 /*< private >*/ 286 CPUState parent_obj; 287 /*< public >*/ 288 CPUNegativeOffsetState neg; 289 CPURISCVState env; 290 291 char *dyn_csr_xml; 292 293 /* Configuration Settings */ 294 struct { 295 bool ext_i; 296 bool ext_e; 297 bool ext_g; 298 bool ext_m; 299 bool ext_a; 300 bool ext_f; 301 bool ext_d; 302 bool ext_c; 303 bool ext_s; 304 bool ext_u; 305 bool ext_h; 306 bool ext_j; 307 bool ext_v; 308 bool ext_zba; 309 bool ext_zbb; 310 bool ext_zbc; 311 bool ext_zbs; 312 bool ext_counters; 313 bool ext_ifencei; 314 bool ext_icsr; 315 bool ext_zfh; 316 bool ext_zfhmin; 317 318 char *priv_spec; 319 char *user_spec; 320 char *bext_spec; 321 char *vext_spec; 322 uint16_t vlen; 323 uint16_t elen; 324 bool mmu; 325 bool pmp; 326 bool epmp; 327 uint64_t resetvec; 328 } cfg; 329 }; 330 331 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) 332 { 333 return (env->misa_ext & ext) != 0; 334 } 335 336 static inline bool riscv_feature(CPURISCVState *env, int feature) 337 { 338 return env->features & (1ULL << feature); 339 } 340 341 #include "cpu_user.h" 342 343 extern const char * const riscv_int_regnames[]; 344 extern const char * const riscv_fpr_regnames[]; 345 346 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); 347 void riscv_cpu_do_interrupt(CPUState *cpu); 348 int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 349 int cpuid, void *opaque); 350 int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 351 int cpuid, void *opaque); 352 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 353 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 354 bool riscv_cpu_fp_enabled(CPURISCVState *env); 355 bool riscv_cpu_virt_enabled(CPURISCVState *env); 356 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); 357 bool riscv_cpu_two_stage_lookup(int mmu_idx); 358 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); 359 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 360 void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 361 MMUAccessType access_type, int mmu_idx, 362 uintptr_t retaddr) QEMU_NORETURN; 363 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 364 MMUAccessType access_type, int mmu_idx, 365 bool probe, uintptr_t retaddr); 366 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 367 vaddr addr, unsigned size, 368 MMUAccessType access_type, 369 int mmu_idx, MemTxAttrs attrs, 370 MemTxResult response, uintptr_t retaddr); 371 char *riscv_isa_string(RISCVCPU *cpu); 372 void riscv_cpu_list(void); 373 374 #define cpu_list riscv_cpu_list 375 #define cpu_mmu_index riscv_cpu_mmu_index 376 377 #ifndef CONFIG_USER_ONLY 378 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); 379 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); 380 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts); 381 uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value); 382 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ 383 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t), 384 uint32_t arg); 385 #endif 386 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); 387 388 void riscv_translate_init(void); 389 void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env, 390 uint32_t exception, uintptr_t pc); 391 392 target_ulong riscv_cpu_get_fflags(CPURISCVState *env); 393 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); 394 395 #define TB_FLAGS_PRIV_MMU_MASK 3 396 #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2) 397 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS 398 399 typedef CPURISCVState CPUArchState; 400 typedef RISCVCPU ArchCPU; 401 #include "exec/cpu-all.h" 402 403 FIELD(TB_FLAGS, MEM_IDX, 0, 3) 404 FIELD(TB_FLAGS, VL_EQ_VLMAX, 3, 1) 405 FIELD(TB_FLAGS, LMUL, 4, 2) 406 FIELD(TB_FLAGS, SEW, 6, 3) 407 FIELD(TB_FLAGS, VILL, 9, 1) 408 /* Is a Hypervisor instruction load/store allowed? */ 409 FIELD(TB_FLAGS, HLSX, 10, 1) 410 FIELD(TB_FLAGS, MSTATUS_HS_FS, 11, 2) 411 /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ 412 FIELD(TB_FLAGS, XL, 13, 2) 413 /* If PointerMasking should be applied */ 414 FIELD(TB_FLAGS, PM_ENABLED, 15, 1) 415 416 #ifdef TARGET_RISCV32 417 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) 418 #else 419 static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) 420 { 421 return env->misa_mxl; 422 } 423 #endif 424 425 /* 426 * A simplification for VLMAX 427 * = (1 << LMUL) * VLEN / (8 * (1 << SEW)) 428 * = (VLEN << LMUL) / (8 << SEW) 429 * = (VLEN << LMUL) >> (SEW + 3) 430 * = VLEN >> (SEW + 3 - LMUL) 431 */ 432 static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) 433 { 434 uint8_t sew, lmul; 435 436 sew = FIELD_EX64(vtype, VTYPE, VSEW); 437 lmul = FIELD_EX64(vtype, VTYPE, VLMUL); 438 return cpu->cfg.vlen >> (sew + 3 - lmul); 439 } 440 441 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 442 target_ulong *cs_base, uint32_t *pflags); 443 444 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, 445 target_ulong *ret_value, 446 target_ulong new_value, target_ulong write_mask); 447 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, 448 target_ulong *ret_value, 449 target_ulong new_value, 450 target_ulong write_mask); 451 452 static inline void riscv_csr_write(CPURISCVState *env, int csrno, 453 target_ulong val) 454 { 455 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); 456 } 457 458 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) 459 { 460 target_ulong val = 0; 461 riscv_csrrw(env, csrno, &val, 0, 0); 462 return val; 463 } 464 465 typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, 466 int csrno); 467 typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, 468 target_ulong *ret_value); 469 typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, 470 target_ulong new_value); 471 typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, 472 target_ulong *ret_value, 473 target_ulong new_value, 474 target_ulong write_mask); 475 476 typedef struct { 477 const char *name; 478 riscv_csr_predicate_fn predicate; 479 riscv_csr_read_fn read; 480 riscv_csr_write_fn write; 481 riscv_csr_op_fn op; 482 } riscv_csr_operations; 483 484 /* CSR function table constants */ 485 enum { 486 CSR_TABLE_SIZE = 0x1000 487 }; 488 489 /* CSR function table */ 490 extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; 491 492 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); 493 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); 494 495 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); 496 497 #endif /* RISCV_CPU_H */ 498