1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef RISCV_CPU_H 21 #define RISCV_CPU_H 22 23 #include "hw/core/cpu.h" 24 #include "hw/registerfields.h" 25 #include "hw/qdev-properties.h" 26 #include "exec/cpu-defs.h" 27 #include "exec/gdbstub.h" 28 #include "qemu/cpu-float.h" 29 #include "qom/object.h" 30 #include "qemu/int128.h" 31 #include "cpu_bits.h" 32 #include "cpu_cfg.h" 33 #include "qapi/qapi-types-common.h" 34 #include "cpu-qom.h" 35 36 typedef struct CPUArchState CPURISCVState; 37 38 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU 39 40 #if defined(TARGET_RISCV32) 41 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 42 #elif defined(TARGET_RISCV64) 43 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 44 #endif 45 46 /* 47 * RISC-V-specific extra insn start words: 48 * 1: Original instruction opcode 49 */ 50 #define TARGET_INSN_START_EXTRA_WORDS 1 51 52 #define RV(x) ((target_ulong)1 << (x - 'A')) 53 54 /* 55 * Update misa_bits[], misa_ext_info_arr[] and misa_ext_cfgs[] 56 * when adding new MISA bits here. 57 */ 58 #define RVI RV('I') 59 #define RVE RV('E') /* E and I are mutually exclusive */ 60 #define RVM RV('M') 61 #define RVA RV('A') 62 #define RVF RV('F') 63 #define RVD RV('D') 64 #define RVV RV('V') 65 #define RVC RV('C') 66 #define RVS RV('S') 67 #define RVU RV('U') 68 #define RVH RV('H') 69 #define RVJ RV('J') 70 #define RVG RV('G') 71 #define RVB RV('B') 72 73 extern const uint32_t misa_bits[]; 74 const char *riscv_get_misa_ext_name(uint32_t bit); 75 const char *riscv_get_misa_ext_description(uint32_t bit); 76 77 #define CPU_CFG_OFFSET(_prop) offsetof(struct RISCVCPUConfig, _prop) 78 79 typedef struct riscv_cpu_profile { 80 struct riscv_cpu_profile *parent; 81 const char *name; 82 uint32_t misa_ext; 83 bool enabled; 84 bool user_set; 85 int priv_spec; 86 int satp_mode; 87 const int32_t ext_offsets[]; 88 } RISCVCPUProfile; 89 90 #define RISCV_PROFILE_EXT_LIST_END -1 91 #define RISCV_PROFILE_ATTR_UNUSED -1 92 93 extern RISCVCPUProfile *riscv_profiles[]; 94 95 /* Privileged specification version */ 96 #define PRIV_VER_1_10_0_STR "v1.10.0" 97 #define PRIV_VER_1_11_0_STR "v1.11.0" 98 #define PRIV_VER_1_12_0_STR "v1.12.0" 99 enum { 100 PRIV_VERSION_1_10_0 = 0, 101 PRIV_VERSION_1_11_0, 102 PRIV_VERSION_1_12_0, 103 104 PRIV_VERSION_LATEST = PRIV_VERSION_1_12_0, 105 }; 106 107 #define VEXT_VERSION_1_00_0 0x00010000 108 #define VEXT_VER_1_00_0_STR "v1.0" 109 110 enum { 111 TRANSLATE_SUCCESS, 112 TRANSLATE_FAIL, 113 TRANSLATE_PMP_FAIL, 114 TRANSLATE_G_STAGE_FAIL 115 }; 116 117 /* Extension context status */ 118 typedef enum { 119 EXT_STATUS_DISABLED = 0, 120 EXT_STATUS_INITIAL, 121 EXT_STATUS_CLEAN, 122 EXT_STATUS_DIRTY, 123 } RISCVExtStatus; 124 125 #define MMU_USER_IDX 3 126 127 #define MAX_RISCV_PMPS (16) 128 129 #if !defined(CONFIG_USER_ONLY) 130 #include "pmp.h" 131 #include "debug.h" 132 #endif 133 134 #define RV_VLEN_MAX 1024 135 #define RV_MAX_MHPMEVENTS 32 136 #define RV_MAX_MHPMCOUNTERS 32 137 138 FIELD(VTYPE, VLMUL, 0, 3) 139 FIELD(VTYPE, VSEW, 3, 3) 140 FIELD(VTYPE, VTA, 6, 1) 141 FIELD(VTYPE, VMA, 7, 1) 142 FIELD(VTYPE, VEDIV, 8, 2) 143 FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) 144 145 typedef struct PMUCTRState { 146 /* Current value of a counter */ 147 target_ulong mhpmcounter_val; 148 /* Current value of a counter in RV32 */ 149 target_ulong mhpmcounterh_val; 150 /* Snapshot values of counter */ 151 target_ulong mhpmcounter_prev; 152 /* Snapshort value of a counter in RV32 */ 153 target_ulong mhpmcounterh_prev; 154 bool started; 155 /* Value beyond UINT32_MAX/UINT64_MAX before overflow interrupt trigger */ 156 target_ulong irq_overflow_left; 157 } PMUCTRState; 158 159 struct CPUArchState { 160 target_ulong gpr[32]; 161 target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ 162 163 /* vector coprocessor state. */ 164 uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); 165 target_ulong vxrm; 166 target_ulong vxsat; 167 target_ulong vl; 168 target_ulong vstart; 169 target_ulong vtype; 170 bool vill; 171 172 target_ulong pc; 173 target_ulong load_res; 174 target_ulong load_val; 175 176 /* Floating-Point state */ 177 uint64_t fpr[32]; /* assume both F and D extensions */ 178 target_ulong frm; 179 float_status fp_status; 180 181 target_ulong badaddr; 182 target_ulong bins; 183 184 target_ulong guest_phys_fault_addr; 185 186 target_ulong priv_ver; 187 target_ulong vext_ver; 188 189 /* RISCVMXL, but uint32_t for vmstate migration */ 190 uint32_t misa_mxl; /* current mxl */ 191 uint32_t misa_ext; /* current extensions */ 192 uint32_t misa_ext_mask; /* max ext for this cpu */ 193 uint32_t xl; /* current xlen */ 194 195 /* 128-bit helpers upper part return value */ 196 target_ulong retxh; 197 198 target_ulong jvt; 199 200 #ifdef CONFIG_USER_ONLY 201 uint32_t elf_flags; 202 #endif 203 204 #ifndef CONFIG_USER_ONLY 205 target_ulong priv; 206 /* This contains QEMU specific information about the virt state. */ 207 bool virt_enabled; 208 target_ulong geilen; 209 uint64_t resetvec; 210 211 target_ulong mhartid; 212 /* 213 * For RV32 this is 32-bit mstatus and 32-bit mstatush. 214 * For RV64 this is a 64-bit mstatus. 215 */ 216 uint64_t mstatus; 217 218 uint64_t mip; 219 /* 220 * MIP contains the software writable version of SEIP ORed with the 221 * external interrupt value. The MIP register is always up-to-date. 222 * To keep track of the current source, we also save booleans of the values 223 * here. 224 */ 225 bool external_seip; 226 bool software_seip; 227 228 uint64_t miclaim; 229 230 uint64_t mie; 231 uint64_t mideleg; 232 233 /* 234 * When mideleg[i]=0 and mvien[i]=1, sie[i] is no more 235 * alias of mie[i] and needs to be maintained separately. 236 */ 237 uint64_t sie; 238 239 /* 240 * When hideleg[i]=0 and hvien[i]=1, vsie[i] is no more 241 * alias of sie[i] (mie[i]) and needs to be maintained separately. 242 */ 243 uint64_t vsie; 244 245 target_ulong satp; /* since: priv-1.10.0 */ 246 target_ulong stval; 247 target_ulong medeleg; 248 249 target_ulong stvec; 250 target_ulong sepc; 251 target_ulong scause; 252 253 target_ulong mtvec; 254 target_ulong mepc; 255 target_ulong mcause; 256 target_ulong mtval; /* since: priv-1.10.0 */ 257 258 /* Machine and Supervisor interrupt priorities */ 259 uint8_t miprio[64]; 260 uint8_t siprio[64]; 261 262 /* AIA CSRs */ 263 target_ulong miselect; 264 target_ulong siselect; 265 uint64_t mvien; 266 uint64_t mvip; 267 268 /* Hypervisor CSRs */ 269 target_ulong hstatus; 270 target_ulong hedeleg; 271 uint64_t hideleg; 272 uint32_t hcounteren; 273 target_ulong htval; 274 target_ulong htinst; 275 target_ulong hgatp; 276 target_ulong hgeie; 277 target_ulong hgeip; 278 uint64_t htimedelta; 279 uint64_t hvien; 280 281 /* 282 * Bits VSSIP, VSTIP and VSEIP in hvip are maintained in mip. Other bits 283 * from 0:12 are reserved. Bits 13:63 are not aliased and must be separately 284 * maintain in hvip. 285 */ 286 uint64_t hvip; 287 288 /* Hypervisor controlled virtual interrupt priorities */ 289 target_ulong hvictl; 290 uint8_t hviprio[64]; 291 292 /* Upper 64-bits of 128-bit CSRs */ 293 uint64_t mscratchh; 294 uint64_t sscratchh; 295 296 /* Virtual CSRs */ 297 /* 298 * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. 299 * For RV64 this is a 64-bit vsstatus. 300 */ 301 uint64_t vsstatus; 302 target_ulong vstvec; 303 target_ulong vsscratch; 304 target_ulong vsepc; 305 target_ulong vscause; 306 target_ulong vstval; 307 target_ulong vsatp; 308 309 /* AIA VS-mode CSRs */ 310 target_ulong vsiselect; 311 312 target_ulong mtval2; 313 target_ulong mtinst; 314 315 /* HS Backup CSRs */ 316 target_ulong stvec_hs; 317 target_ulong sscratch_hs; 318 target_ulong sepc_hs; 319 target_ulong scause_hs; 320 target_ulong stval_hs; 321 target_ulong satp_hs; 322 uint64_t mstatus_hs; 323 324 /* 325 * Signals whether the current exception occurred with two-stage address 326 * translation active. 327 */ 328 bool two_stage_lookup; 329 /* 330 * Signals whether the current exception occurred while doing two-stage 331 * address translation for the VS-stage page table walk. 332 */ 333 bool two_stage_indirect_lookup; 334 335 uint32_t scounteren; 336 uint32_t mcounteren; 337 338 uint32_t mcountinhibit; 339 340 /* PMU counter state */ 341 PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS]; 342 343 /* PMU event selector configured values. First three are unused */ 344 target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS]; 345 346 /* PMU event selector configured values for RV32 */ 347 target_ulong mhpmeventh_val[RV_MAX_MHPMEVENTS]; 348 349 target_ulong sscratch; 350 target_ulong mscratch; 351 352 /* Sstc CSRs */ 353 uint64_t stimecmp; 354 355 uint64_t vstimecmp; 356 357 /* physical memory protection */ 358 pmp_table_t pmp_state; 359 target_ulong mseccfg; 360 361 /* trigger module */ 362 target_ulong trigger_cur; 363 target_ulong tdata1[RV_MAX_TRIGGERS]; 364 target_ulong tdata2[RV_MAX_TRIGGERS]; 365 target_ulong tdata3[RV_MAX_TRIGGERS]; 366 target_ulong mcontext; 367 struct CPUBreakpoint *cpu_breakpoint[RV_MAX_TRIGGERS]; 368 struct CPUWatchpoint *cpu_watchpoint[RV_MAX_TRIGGERS]; 369 QEMUTimer *itrigger_timer[RV_MAX_TRIGGERS]; 370 int64_t last_icount; 371 bool itrigger_enabled; 372 373 /* machine specific rdtime callback */ 374 uint64_t (*rdtime_fn)(void *); 375 void *rdtime_fn_arg; 376 377 /* machine specific AIA ireg read-modify-write callback */ 378 #define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \ 379 ((((__xlen) & 0xff) << 24) | \ 380 (((__vgein) & 0x3f) << 20) | \ 381 (((__virt) & 0x1) << 18) | \ 382 (((__priv) & 0x3) << 16) | \ 383 (__isel & 0xffff)) 384 #define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff) 385 #define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3) 386 #define AIA_IREG_VIRT(__ireg) (((__ireg) >> 18) & 0x1) 387 #define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 20) & 0x3f) 388 #define AIA_IREG_XLEN(__ireg) (((__ireg) >> 24) & 0xff) 389 int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg, 390 target_ulong *val, target_ulong new_val, target_ulong write_mask); 391 void *aia_ireg_rmw_fn_arg[4]; 392 393 /* True if in debugger mode. */ 394 bool debugger; 395 396 /* 397 * CSRs for PointerMasking extension 398 */ 399 target_ulong mmte; 400 target_ulong mpmmask; 401 target_ulong mpmbase; 402 target_ulong spmmask; 403 target_ulong spmbase; 404 target_ulong upmmask; 405 target_ulong upmbase; 406 407 /* CSRs for execution environment configuration */ 408 uint64_t menvcfg; 409 uint64_t mstateen[SMSTATEEN_MAX_COUNT]; 410 uint64_t hstateen[SMSTATEEN_MAX_COUNT]; 411 uint64_t sstateen[SMSTATEEN_MAX_COUNT]; 412 target_ulong senvcfg; 413 uint64_t henvcfg; 414 #endif 415 target_ulong cur_pmmask; 416 target_ulong cur_pmbase; 417 418 /* Fields from here on are preserved across CPU reset. */ 419 QEMUTimer *stimer; /* Internal timer for S-mode interrupt */ 420 QEMUTimer *vstimer; /* Internal timer for VS-mode interrupt */ 421 bool vstime_irq; 422 423 hwaddr kernel_addr; 424 hwaddr fdt_addr; 425 426 #ifdef CONFIG_KVM 427 /* kvm timer */ 428 bool kvm_timer_dirty; 429 uint64_t kvm_timer_time; 430 uint64_t kvm_timer_compare; 431 uint64_t kvm_timer_state; 432 uint64_t kvm_timer_frequency; 433 #endif /* CONFIG_KVM */ 434 }; 435 436 /* 437 * RISCVCPU: 438 * @env: #CPURISCVState 439 * 440 * A RISCV CPU. 441 */ 442 struct ArchCPU { 443 CPUState parent_obj; 444 445 CPURISCVState env; 446 447 GDBFeature dyn_csr_feature; 448 GDBFeature dyn_vreg_feature; 449 450 /* Configuration Settings */ 451 RISCVCPUConfig cfg; 452 453 QEMUTimer *pmu_timer; 454 /* A bitmask of Available programmable counters */ 455 uint32_t pmu_avail_ctrs; 456 /* Mapping of events to counters */ 457 GHashTable *pmu_event_ctr_map; 458 }; 459 460 /** 461 * RISCVCPUClass: 462 * @parent_realize: The parent class' realize handler. 463 * @parent_phases: The parent class' reset phase handlers. 464 * 465 * A RISCV CPU model. 466 */ 467 struct RISCVCPUClass { 468 CPUClass parent_class; 469 470 DeviceRealize parent_realize; 471 ResettablePhases parent_phases; 472 uint32_t misa_mxl_max; /* max mxl for this cpu */ 473 }; 474 475 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) 476 { 477 return (env->misa_ext & ext) != 0; 478 } 479 480 #include "cpu_user.h" 481 482 extern const char * const riscv_int_regnames[]; 483 extern const char * const riscv_int_regnamesh[]; 484 extern const char * const riscv_fpr_regnames[]; 485 486 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); 487 void riscv_cpu_do_interrupt(CPUState *cpu); 488 int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 489 int cpuid, DumpState *s); 490 int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 491 int cpuid, DumpState *s); 492 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 493 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 494 int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero); 495 uint8_t riscv_cpu_default_priority(int irq); 496 uint64_t riscv_cpu_all_pending(CPURISCVState *env); 497 int riscv_cpu_mirq_pending(CPURISCVState *env); 498 int riscv_cpu_sirq_pending(CPURISCVState *env); 499 int riscv_cpu_vsirq_pending(CPURISCVState *env); 500 bool riscv_cpu_fp_enabled(CPURISCVState *env); 501 target_ulong riscv_cpu_get_geilen(CPURISCVState *env); 502 void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); 503 bool riscv_cpu_vector_enabled(CPURISCVState *env); 504 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); 505 int riscv_env_mmu_index(CPURISCVState *env, bool ifetch); 506 G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 507 MMUAccessType access_type, 508 int mmu_idx, uintptr_t retaddr); 509 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 510 MMUAccessType access_type, int mmu_idx, 511 bool probe, uintptr_t retaddr); 512 char *riscv_isa_string(RISCVCPU *cpu); 513 int riscv_cpu_max_xlen(RISCVCPUClass *mcc); 514 bool riscv_cpu_option_set(const char *optname); 515 516 #ifndef CONFIG_USER_ONLY 517 void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename); 518 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 519 vaddr addr, unsigned size, 520 MMUAccessType access_type, 521 int mmu_idx, MemTxAttrs attrs, 522 MemTxResult response, uintptr_t retaddr); 523 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 524 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); 525 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); 526 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); 527 uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask, 528 uint64_t value); 529 void riscv_cpu_interrupt(CPURISCVState *env); 530 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ 531 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), 532 void *arg); 533 void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, 534 int (*rmw_fn)(void *arg, 535 target_ulong reg, 536 target_ulong *val, 537 target_ulong new_val, 538 target_ulong write_mask), 539 void *rmw_fn_arg); 540 541 RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit); 542 #endif 543 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); 544 545 void riscv_translate_init(void); 546 G_NORETURN void riscv_raise_exception(CPURISCVState *env, 547 uint32_t exception, uintptr_t pc); 548 549 target_ulong riscv_cpu_get_fflags(CPURISCVState *env); 550 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); 551 552 #include "exec/cpu-all.h" 553 554 FIELD(TB_FLAGS, MEM_IDX, 0, 3) 555 FIELD(TB_FLAGS, FS, 3, 2) 556 /* Vector flags */ 557 FIELD(TB_FLAGS, VS, 5, 2) 558 FIELD(TB_FLAGS, LMUL, 7, 3) 559 FIELD(TB_FLAGS, SEW, 10, 3) 560 FIELD(TB_FLAGS, VL_EQ_VLMAX, 13, 1) 561 FIELD(TB_FLAGS, VILL, 14, 1) 562 FIELD(TB_FLAGS, VSTART_EQ_ZERO, 15, 1) 563 /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ 564 FIELD(TB_FLAGS, XL, 16, 2) 565 /* If PointerMasking should be applied */ 566 FIELD(TB_FLAGS, PM_MASK_ENABLED, 18, 1) 567 FIELD(TB_FLAGS, PM_BASE_ENABLED, 19, 1) 568 FIELD(TB_FLAGS, VTA, 20, 1) 569 FIELD(TB_FLAGS, VMA, 21, 1) 570 /* Native debug itrigger */ 571 FIELD(TB_FLAGS, ITRIGGER, 22, 1) 572 /* Virtual mode enabled */ 573 FIELD(TB_FLAGS, VIRT_ENABLED, 23, 1) 574 FIELD(TB_FLAGS, PRIV, 24, 2) 575 FIELD(TB_FLAGS, AXL, 26, 2) 576 577 #ifdef TARGET_RISCV32 578 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) 579 #else 580 static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) 581 { 582 return env->misa_mxl; 583 } 584 #endif 585 #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env))) 586 587 static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURISCVState *env) 588 { 589 return &env_archcpu(env)->cfg; 590 } 591 592 #if !defined(CONFIG_USER_ONLY) 593 static inline int cpu_address_mode(CPURISCVState *env) 594 { 595 int mode = env->priv; 596 597 if (mode == PRV_M && get_field(env->mstatus, MSTATUS_MPRV)) { 598 mode = get_field(env->mstatus, MSTATUS_MPP); 599 } 600 return mode; 601 } 602 603 static inline RISCVMXL cpu_get_xl(CPURISCVState *env, target_ulong mode) 604 { 605 RISCVMXL xl = env->misa_mxl; 606 /* 607 * When emulating a 32-bit-only cpu, use RV32. 608 * When emulating a 64-bit cpu, and MXL has been reduced to RV32, 609 * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened 610 * back to RV64 for lower privs. 611 */ 612 if (xl != MXL_RV32) { 613 switch (mode) { 614 case PRV_M: 615 break; 616 case PRV_U: 617 xl = get_field(env->mstatus, MSTATUS64_UXL); 618 break; 619 default: /* PRV_S */ 620 xl = get_field(env->mstatus, MSTATUS64_SXL); 621 break; 622 } 623 } 624 return xl; 625 } 626 #endif 627 628 #if defined(TARGET_RISCV32) 629 #define cpu_recompute_xl(env) ((void)(env), MXL_RV32) 630 #else 631 static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) 632 { 633 #if !defined(CONFIG_USER_ONLY) 634 return cpu_get_xl(env, env->priv); 635 #else 636 return env->misa_mxl; 637 #endif 638 } 639 #endif 640 641 #if defined(TARGET_RISCV32) 642 #define cpu_address_xl(env) ((void)(env), MXL_RV32) 643 #else 644 static inline RISCVMXL cpu_address_xl(CPURISCVState *env) 645 { 646 #ifdef CONFIG_USER_ONLY 647 return env->xl; 648 #else 649 int mode = cpu_address_mode(env); 650 651 return cpu_get_xl(env, mode); 652 #endif 653 } 654 #endif 655 656 static inline int riscv_cpu_xlen(CPURISCVState *env) 657 { 658 return 16 << env->xl; 659 } 660 661 #ifdef TARGET_RISCV32 662 #define riscv_cpu_sxl(env) ((void)(env), MXL_RV32) 663 #else 664 static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env) 665 { 666 #ifdef CONFIG_USER_ONLY 667 return env->misa_mxl; 668 #else 669 return get_field(env->mstatus, MSTATUS64_SXL); 670 #endif 671 } 672 #endif 673 674 /* 675 * Encode LMUL to lmul as follows: 676 * LMUL vlmul lmul 677 * 1 000 0 678 * 2 001 1 679 * 4 010 2 680 * 8 011 3 681 * - 100 - 682 * 1/8 101 -3 683 * 1/4 110 -2 684 * 1/2 111 -1 685 * 686 * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul) 687 * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8 688 * => VLMAX = vlen >> (1 + 3 - (-3)) 689 * = 256 >> 7 690 * = 2 691 */ 692 static inline uint32_t vext_get_vlmax(uint32_t vlenb, uint32_t vsew, 693 int8_t lmul) 694 { 695 uint32_t vlen = vlenb << 3; 696 697 /* 698 * We need to use 'vlen' instead of 'vlenb' to 699 * preserve the '+ 3' in the formula. Otherwise 700 * we risk a negative shift if vsew < lmul. 701 */ 702 return vlen >> (vsew + 3 - lmul); 703 } 704 705 void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, 706 uint64_t *cs_base, uint32_t *pflags); 707 708 void riscv_cpu_update_mask(CPURISCVState *env); 709 bool riscv_cpu_is_32bit(RISCVCPU *cpu); 710 711 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, 712 target_ulong *ret_value, 713 target_ulong new_value, target_ulong write_mask); 714 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, 715 target_ulong *ret_value, 716 target_ulong new_value, 717 target_ulong write_mask); 718 719 static inline void riscv_csr_write(CPURISCVState *env, int csrno, 720 target_ulong val) 721 { 722 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); 723 } 724 725 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) 726 { 727 target_ulong val = 0; 728 riscv_csrrw(env, csrno, &val, 0, 0); 729 return val; 730 } 731 732 typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, 733 int csrno); 734 typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, 735 target_ulong *ret_value); 736 typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, 737 target_ulong new_value); 738 typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, 739 target_ulong *ret_value, 740 target_ulong new_value, 741 target_ulong write_mask); 742 743 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, 744 Int128 *ret_value, 745 Int128 new_value, Int128 write_mask); 746 747 typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno, 748 Int128 *ret_value); 749 typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int csrno, 750 Int128 new_value); 751 752 typedef struct { 753 const char *name; 754 riscv_csr_predicate_fn predicate; 755 riscv_csr_read_fn read; 756 riscv_csr_write_fn write; 757 riscv_csr_op_fn op; 758 riscv_csr_read128_fn read128; 759 riscv_csr_write128_fn write128; 760 /* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0) */ 761 uint32_t min_priv_ver; 762 } riscv_csr_operations; 763 764 /* CSR function table constants */ 765 enum { 766 CSR_TABLE_SIZE = 0x1000 767 }; 768 769 /* 770 * The event id are encoded based on the encoding specified in the 771 * SBI specification v0.3 772 */ 773 774 enum riscv_pmu_event_idx { 775 RISCV_PMU_EVENT_HW_CPU_CYCLES = 0x01, 776 RISCV_PMU_EVENT_HW_INSTRUCTIONS = 0x02, 777 RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS = 0x10019, 778 RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS = 0x1001B, 779 RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS = 0x10021, 780 }; 781 782 /* used by tcg/tcg-cpu.c*/ 783 void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en); 784 bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset); 785 void riscv_cpu_set_misa_ext(CPURISCVState *env, uint32_t ext); 786 bool riscv_cpu_is_vendor(Object *cpu_obj); 787 788 typedef struct RISCVCPUMultiExtConfig { 789 const char *name; 790 uint32_t offset; 791 bool enabled; 792 } RISCVCPUMultiExtConfig; 793 794 extern const RISCVCPUMultiExtConfig riscv_cpu_extensions[]; 795 extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[]; 796 extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[]; 797 extern const RISCVCPUMultiExtConfig riscv_cpu_named_features[]; 798 extern const RISCVCPUMultiExtConfig riscv_cpu_deprecated_exts[]; 799 800 typedef struct isa_ext_data { 801 const char *name; 802 int min_version; 803 int ext_enable_offset; 804 } RISCVIsaExtData; 805 extern const RISCVIsaExtData isa_edata_arr[]; 806 char *riscv_cpu_get_name(RISCVCPU *cpu); 807 808 void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp); 809 void riscv_add_satp_mode_properties(Object *obj); 810 bool riscv_cpu_accelerator_compatible(RISCVCPU *cpu); 811 812 /* CSR function table */ 813 extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; 814 815 extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[]; 816 817 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); 818 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); 819 820 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); 821 822 uint8_t satp_mode_max_from_map(uint32_t map); 823 const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); 824 825 #endif /* RISCV_CPU_H */ 826