1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef RISCV_CPU_H 21 #define RISCV_CPU_H 22 23 #include "hw/core/cpu.h" 24 #include "hw/registerfields.h" 25 #include "exec/cpu-defs.h" 26 #include "fpu/softfloat-types.h" 27 #include "qom/object.h" 28 #include "qemu/int128.h" 29 #include "cpu_bits.h" 30 31 #define TCG_GUEST_DEFAULT_MO 0 32 33 #define TYPE_RISCV_CPU "riscv-cpu" 34 35 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU 36 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) 37 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU 38 39 #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") 40 #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") 41 #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") 42 #define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128") 43 #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") 44 #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") 45 #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") 46 #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") 47 #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") 48 #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") 49 #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") 50 51 #if defined(TARGET_RISCV32) 52 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 53 #elif defined(TARGET_RISCV64) 54 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 55 #endif 56 57 #define RV(x) ((target_ulong)1 << (x - 'A')) 58 59 #define RVI RV('I') 60 #define RVE RV('E') /* E and I are mutually exclusive */ 61 #define RVM RV('M') 62 #define RVA RV('A') 63 #define RVF RV('F') 64 #define RVD RV('D') 65 #define RVV RV('V') 66 #define RVC RV('C') 67 #define RVS RV('S') 68 #define RVU RV('U') 69 #define RVH RV('H') 70 #define RVJ RV('J') 71 72 /* S extension denotes that Supervisor mode exists, however it is possible 73 to have a core that support S mode but does not have an MMU and there 74 is currently no bit in misa to indicate whether an MMU exists or not 75 so a cpu features bitfield is required, likewise for optional PMP support */ 76 enum { 77 RISCV_FEATURE_MMU, 78 RISCV_FEATURE_PMP, 79 RISCV_FEATURE_EPMP, 80 RISCV_FEATURE_MISA 81 }; 82 83 #define PRIV_VERSION_1_10_0 0x00011000 84 #define PRIV_VERSION_1_11_0 0x00011100 85 86 #define VEXT_VERSION_1_00_0 0x00010000 87 88 enum { 89 TRANSLATE_SUCCESS, 90 TRANSLATE_FAIL, 91 TRANSLATE_PMP_FAIL, 92 TRANSLATE_G_STAGE_FAIL 93 }; 94 95 #define MMU_USER_IDX 3 96 97 #define MAX_RISCV_PMPS (16) 98 99 typedef struct CPURISCVState CPURISCVState; 100 101 #if !defined(CONFIG_USER_ONLY) 102 #include "pmp.h" 103 #endif 104 105 #define RV_VLEN_MAX 1024 106 107 FIELD(VTYPE, VLMUL, 0, 3) 108 FIELD(VTYPE, VSEW, 3, 3) 109 FIELD(VTYPE, VTA, 6, 1) 110 FIELD(VTYPE, VMA, 7, 1) 111 FIELD(VTYPE, VEDIV, 8, 2) 112 FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) 113 FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1) 114 115 struct CPURISCVState { 116 target_ulong gpr[32]; 117 target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ 118 uint64_t fpr[32]; /* assume both F and D extensions */ 119 120 /* vector coprocessor state. */ 121 uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); 122 target_ulong vxrm; 123 target_ulong vxsat; 124 target_ulong vl; 125 target_ulong vstart; 126 target_ulong vtype; 127 128 target_ulong pc; 129 target_ulong load_res; 130 target_ulong load_val; 131 132 target_ulong frm; 133 134 target_ulong badaddr; 135 target_ulong guest_phys_fault_addr; 136 137 target_ulong priv_ver; 138 target_ulong bext_ver; 139 target_ulong vext_ver; 140 141 /* RISCVMXL, but uint32_t for vmstate migration */ 142 uint32_t misa_mxl; /* current mxl */ 143 uint32_t misa_mxl_max; /* max mxl for this cpu */ 144 uint32_t misa_ext; /* current extensions */ 145 uint32_t misa_ext_mask; /* max ext for this cpu */ 146 147 /* 128-bit helpers upper part return value */ 148 target_ulong retxh; 149 150 uint32_t features; 151 152 #ifdef CONFIG_USER_ONLY 153 uint32_t elf_flags; 154 #endif 155 156 #ifndef CONFIG_USER_ONLY 157 target_ulong priv; 158 /* This contains QEMU specific information about the virt state. */ 159 target_ulong virt; 160 target_ulong resetvec; 161 162 target_ulong mhartid; 163 /* 164 * For RV32 this is 32-bit mstatus and 32-bit mstatush. 165 * For RV64 this is a 64-bit mstatus. 166 */ 167 uint64_t mstatus; 168 169 target_ulong mip; 170 171 uint32_t miclaim; 172 173 target_ulong mie; 174 target_ulong mideleg; 175 176 target_ulong satp; /* since: priv-1.10.0 */ 177 target_ulong stval; 178 target_ulong medeleg; 179 180 target_ulong stvec; 181 target_ulong sepc; 182 target_ulong scause; 183 184 target_ulong mtvec; 185 target_ulong mepc; 186 target_ulong mcause; 187 target_ulong mtval; /* since: priv-1.10.0 */ 188 189 /* Hypervisor CSRs */ 190 target_ulong hstatus; 191 target_ulong hedeleg; 192 target_ulong hideleg; 193 target_ulong hcounteren; 194 target_ulong htval; 195 target_ulong htinst; 196 target_ulong hgatp; 197 uint64_t htimedelta; 198 199 /* Upper 64-bits of 128-bit CSRs */ 200 uint64_t mscratchh; 201 uint64_t sscratchh; 202 203 /* Virtual CSRs */ 204 /* 205 * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. 206 * For RV64 this is a 64-bit vsstatus. 207 */ 208 uint64_t vsstatus; 209 target_ulong vstvec; 210 target_ulong vsscratch; 211 target_ulong vsepc; 212 target_ulong vscause; 213 target_ulong vstval; 214 target_ulong vsatp; 215 216 target_ulong mtval2; 217 target_ulong mtinst; 218 219 /* HS Backup CSRs */ 220 target_ulong stvec_hs; 221 target_ulong sscratch_hs; 222 target_ulong sepc_hs; 223 target_ulong scause_hs; 224 target_ulong stval_hs; 225 target_ulong satp_hs; 226 uint64_t mstatus_hs; 227 228 /* Signals whether the current exception occurred with two-stage address 229 translation active. */ 230 bool two_stage_lookup; 231 232 target_ulong scounteren; 233 target_ulong mcounteren; 234 235 target_ulong sscratch; 236 target_ulong mscratch; 237 238 /* temporary htif regs */ 239 uint64_t mfromhost; 240 uint64_t mtohost; 241 uint64_t timecmp; 242 243 /* physical memory protection */ 244 pmp_table_t pmp_state; 245 target_ulong mseccfg; 246 247 /* machine specific rdtime callback */ 248 uint64_t (*rdtime_fn)(uint32_t); 249 uint32_t rdtime_fn_arg; 250 251 /* True if in debugger mode. */ 252 bool debugger; 253 254 /* 255 * CSRs for PointerMasking extension 256 */ 257 target_ulong mmte; 258 target_ulong mpmmask; 259 target_ulong mpmbase; 260 target_ulong spmmask; 261 target_ulong spmbase; 262 target_ulong upmmask; 263 target_ulong upmbase; 264 #endif 265 266 float_status fp_status; 267 268 /* Fields from here on are preserved across CPU reset. */ 269 QEMUTimer *timer; /* Internal timer */ 270 }; 271 272 OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass, 273 RISCV_CPU) 274 275 /** 276 * RISCVCPUClass: 277 * @parent_realize: The parent class' realize handler. 278 * @parent_reset: The parent class' reset handler. 279 * 280 * A RISCV CPU model. 281 */ 282 struct RISCVCPUClass { 283 /*< private >*/ 284 CPUClass parent_class; 285 /*< public >*/ 286 DeviceRealize parent_realize; 287 DeviceReset parent_reset; 288 }; 289 290 /** 291 * RISCVCPU: 292 * @env: #CPURISCVState 293 * 294 * A RISCV CPU. 295 */ 296 struct RISCVCPU { 297 /*< private >*/ 298 CPUState parent_obj; 299 /*< public >*/ 300 CPUNegativeOffsetState neg; 301 CPURISCVState env; 302 303 char *dyn_csr_xml; 304 char *dyn_vreg_xml; 305 306 /* Configuration Settings */ 307 struct { 308 bool ext_i; 309 bool ext_e; 310 bool ext_g; 311 bool ext_m; 312 bool ext_a; 313 bool ext_f; 314 bool ext_d; 315 bool ext_c; 316 bool ext_s; 317 bool ext_u; 318 bool ext_h; 319 bool ext_j; 320 bool ext_v; 321 bool ext_zba; 322 bool ext_zbb; 323 bool ext_zbc; 324 bool ext_zbs; 325 bool ext_counters; 326 bool ext_ifencei; 327 bool ext_icsr; 328 bool ext_zfh; 329 bool ext_zfhmin; 330 331 char *priv_spec; 332 char *user_spec; 333 char *bext_spec; 334 char *vext_spec; 335 uint16_t vlen; 336 uint16_t elen; 337 bool mmu; 338 bool pmp; 339 bool epmp; 340 uint64_t resetvec; 341 } cfg; 342 }; 343 344 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) 345 { 346 return (env->misa_ext & ext) != 0; 347 } 348 349 static inline bool riscv_feature(CPURISCVState *env, int feature) 350 { 351 return env->features & (1ULL << feature); 352 } 353 354 #include "cpu_user.h" 355 356 extern const char * const riscv_int_regnames[]; 357 extern const char * const riscv_int_regnamesh[]; 358 extern const char * const riscv_fpr_regnames[]; 359 360 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); 361 void riscv_cpu_do_interrupt(CPUState *cpu); 362 int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 363 int cpuid, void *opaque); 364 int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 365 int cpuid, void *opaque); 366 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 367 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 368 bool riscv_cpu_fp_enabled(CPURISCVState *env); 369 bool riscv_cpu_vector_enabled(CPURISCVState *env); 370 bool riscv_cpu_virt_enabled(CPURISCVState *env); 371 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); 372 bool riscv_cpu_two_stage_lookup(int mmu_idx); 373 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); 374 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 375 void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 376 MMUAccessType access_type, int mmu_idx, 377 uintptr_t retaddr) QEMU_NORETURN; 378 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 379 MMUAccessType access_type, int mmu_idx, 380 bool probe, uintptr_t retaddr); 381 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 382 vaddr addr, unsigned size, 383 MMUAccessType access_type, 384 int mmu_idx, MemTxAttrs attrs, 385 MemTxResult response, uintptr_t retaddr); 386 char *riscv_isa_string(RISCVCPU *cpu); 387 void riscv_cpu_list(void); 388 389 #define cpu_list riscv_cpu_list 390 #define cpu_mmu_index riscv_cpu_mmu_index 391 392 #ifndef CONFIG_USER_ONLY 393 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); 394 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); 395 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts); 396 uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value); 397 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ 398 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t), 399 uint32_t arg); 400 #endif 401 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); 402 403 void riscv_translate_init(void); 404 void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env, 405 uint32_t exception, uintptr_t pc); 406 407 target_ulong riscv_cpu_get_fflags(CPURISCVState *env); 408 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); 409 410 #define TB_FLAGS_PRIV_MMU_MASK 3 411 #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2) 412 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS 413 #define TB_FLAGS_MSTATUS_VS MSTATUS_VS 414 415 typedef CPURISCVState CPUArchState; 416 typedef RISCVCPU ArchCPU; 417 #include "exec/cpu-all.h" 418 419 FIELD(TB_FLAGS, MEM_IDX, 0, 3) 420 FIELD(TB_FLAGS, LMUL, 3, 3) 421 FIELD(TB_FLAGS, SEW, 6, 3) 422 /* Skip MSTATUS_VS (0x600) bits */ 423 FIELD(TB_FLAGS, VL_EQ_VLMAX, 11, 1) 424 FIELD(TB_FLAGS, VILL, 12, 1) 425 /* Skip MSTATUS_FS (0x6000) bits */ 426 /* Is a Hypervisor instruction load/store allowed? */ 427 FIELD(TB_FLAGS, HLSX, 15, 1) 428 FIELD(TB_FLAGS, MSTATUS_HS_FS, 16, 2) 429 FIELD(TB_FLAGS, MSTATUS_HS_VS, 18, 2) 430 /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ 431 FIELD(TB_FLAGS, XL, 20, 2) 432 /* If PointerMasking should be applied */ 433 FIELD(TB_FLAGS, PM_ENABLED, 22, 1) 434 435 #ifdef TARGET_RISCV32 436 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) 437 #else 438 static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) 439 { 440 return env->misa_mxl; 441 } 442 #endif 443 444 /* 445 * Encode LMUL to lmul as follows: 446 * LMUL vlmul lmul 447 * 1 000 0 448 * 2 001 1 449 * 4 010 2 450 * 8 011 3 451 * - 100 - 452 * 1/8 101 -3 453 * 1/4 110 -2 454 * 1/2 111 -1 455 * 456 * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul) 457 * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8 458 * => VLMAX = vlen >> (1 + 3 - (-3)) 459 * = 256 >> 7 460 * = 2 461 */ 462 static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) 463 { 464 uint8_t sew = FIELD_EX64(vtype, VTYPE, VSEW); 465 int8_t lmul = sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3); 466 return cpu->cfg.vlen >> (sew + 3 - lmul); 467 } 468 469 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 470 target_ulong *cs_base, uint32_t *pflags); 471 472 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, 473 target_ulong *ret_value, 474 target_ulong new_value, target_ulong write_mask); 475 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, 476 target_ulong *ret_value, 477 target_ulong new_value, 478 target_ulong write_mask); 479 480 static inline void riscv_csr_write(CPURISCVState *env, int csrno, 481 target_ulong val) 482 { 483 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); 484 } 485 486 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) 487 { 488 target_ulong val = 0; 489 riscv_csrrw(env, csrno, &val, 0, 0); 490 return val; 491 } 492 493 typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, 494 int csrno); 495 typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, 496 target_ulong *ret_value); 497 typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, 498 target_ulong new_value); 499 typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, 500 target_ulong *ret_value, 501 target_ulong new_value, 502 target_ulong write_mask); 503 504 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, 505 Int128 *ret_value, 506 Int128 new_value, Int128 write_mask); 507 508 typedef struct { 509 const char *name; 510 riscv_csr_predicate_fn predicate; 511 riscv_csr_read_fn read; 512 riscv_csr_write_fn write; 513 riscv_csr_op_fn op; 514 } riscv_csr_operations; 515 516 /* CSR function table constants */ 517 enum { 518 CSR_TABLE_SIZE = 0x1000 519 }; 520 521 /* CSR function table */ 522 extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; 523 524 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); 525 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); 526 527 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); 528 529 #endif /* RISCV_CPU_H */ 530