1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef RISCV_CPU_H 21 #define RISCV_CPU_H 22 23 #include "hw/core/cpu.h" 24 #include "hw/registerfields.h" 25 #include "exec/cpu-defs.h" 26 #include "qemu/cpu-float.h" 27 #include "qom/object.h" 28 #include "qemu/int128.h" 29 #include "cpu_bits.h" 30 31 #define TCG_GUEST_DEFAULT_MO 0 32 33 #define TYPE_RISCV_CPU "riscv-cpu" 34 35 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU 36 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) 37 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU 38 39 #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") 40 #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") 41 #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") 42 #define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128") 43 #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") 44 #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") 45 #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") 46 #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") 47 #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") 48 #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") 49 #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") 50 #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") 51 52 #if defined(TARGET_RISCV32) 53 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 54 #elif defined(TARGET_RISCV64) 55 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 56 #endif 57 58 #define RV(x) ((target_ulong)1 << (x - 'A')) 59 60 #define RVI RV('I') 61 #define RVE RV('E') /* E and I are mutually exclusive */ 62 #define RVM RV('M') 63 #define RVA RV('A') 64 #define RVF RV('F') 65 #define RVD RV('D') 66 #define RVV RV('V') 67 #define RVC RV('C') 68 #define RVS RV('S') 69 #define RVU RV('U') 70 #define RVH RV('H') 71 #define RVJ RV('J') 72 73 /* S extension denotes that Supervisor mode exists, however it is possible 74 to have a core that support S mode but does not have an MMU and there 75 is currently no bit in misa to indicate whether an MMU exists or not 76 so a cpu features bitfield is required, likewise for optional PMP support */ 77 enum { 78 RISCV_FEATURE_MMU, 79 RISCV_FEATURE_PMP, 80 RISCV_FEATURE_EPMP, 81 RISCV_FEATURE_MISA, 82 RISCV_FEATURE_AIA 83 }; 84 85 /* Privileged specification version */ 86 enum { 87 PRIV_VERSION_1_10_0 = 0, 88 PRIV_VERSION_1_11_0, 89 PRIV_VERSION_1_12_0, 90 }; 91 92 #define VEXT_VERSION_1_00_0 0x00010000 93 94 enum { 95 TRANSLATE_SUCCESS, 96 TRANSLATE_FAIL, 97 TRANSLATE_PMP_FAIL, 98 TRANSLATE_G_STAGE_FAIL 99 }; 100 101 #define MMU_USER_IDX 3 102 103 #define MAX_RISCV_PMPS (16) 104 105 typedef struct CPUArchState CPURISCVState; 106 107 #if !defined(CONFIG_USER_ONLY) 108 #include "pmp.h" 109 #include "debug.h" 110 #endif 111 112 #define RV_VLEN_MAX 1024 113 114 FIELD(VTYPE, VLMUL, 0, 3) 115 FIELD(VTYPE, VSEW, 3, 3) 116 FIELD(VTYPE, VTA, 6, 1) 117 FIELD(VTYPE, VMA, 7, 1) 118 FIELD(VTYPE, VEDIV, 8, 2) 119 FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) 120 121 struct CPUArchState { 122 target_ulong gpr[32]; 123 target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ 124 uint64_t fpr[32]; /* assume both F and D extensions */ 125 126 /* vector coprocessor state. */ 127 uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); 128 target_ulong vxrm; 129 target_ulong vxsat; 130 target_ulong vl; 131 target_ulong vstart; 132 target_ulong vtype; 133 bool vill; 134 135 target_ulong pc; 136 target_ulong load_res; 137 target_ulong load_val; 138 139 target_ulong frm; 140 141 target_ulong badaddr; 142 uint32_t bins; 143 144 target_ulong guest_phys_fault_addr; 145 146 target_ulong priv_ver; 147 target_ulong bext_ver; 148 target_ulong vext_ver; 149 150 /* RISCVMXL, but uint32_t for vmstate migration */ 151 uint32_t misa_mxl; /* current mxl */ 152 uint32_t misa_mxl_max; /* max mxl for this cpu */ 153 uint32_t misa_ext; /* current extensions */ 154 uint32_t misa_ext_mask; /* max ext for this cpu */ 155 uint32_t xl; /* current xlen */ 156 157 /* 128-bit helpers upper part return value */ 158 target_ulong retxh; 159 160 uint32_t features; 161 162 #ifdef CONFIG_USER_ONLY 163 uint32_t elf_flags; 164 #endif 165 166 #ifndef CONFIG_USER_ONLY 167 target_ulong priv; 168 /* This contains QEMU specific information about the virt state. */ 169 target_ulong virt; 170 target_ulong geilen; 171 target_ulong resetvec; 172 173 target_ulong mhartid; 174 /* 175 * For RV32 this is 32-bit mstatus and 32-bit mstatush. 176 * For RV64 this is a 64-bit mstatus. 177 */ 178 uint64_t mstatus; 179 180 uint64_t mip; 181 /* 182 * MIP contains the software writable version of SEIP ORed with the 183 * external interrupt value. The MIP register is always up-to-date. 184 * To keep track of the current source, we also save booleans of the values 185 * here. 186 */ 187 bool external_seip; 188 bool software_seip; 189 190 uint64_t miclaim; 191 192 uint64_t mie; 193 uint64_t mideleg; 194 195 target_ulong satp; /* since: priv-1.10.0 */ 196 target_ulong stval; 197 target_ulong medeleg; 198 199 target_ulong stvec; 200 target_ulong sepc; 201 target_ulong scause; 202 203 target_ulong mtvec; 204 target_ulong mepc; 205 target_ulong mcause; 206 target_ulong mtval; /* since: priv-1.10.0 */ 207 208 /* Machine and Supervisor interrupt priorities */ 209 uint8_t miprio[64]; 210 uint8_t siprio[64]; 211 212 /* AIA CSRs */ 213 target_ulong miselect; 214 target_ulong siselect; 215 216 /* Hypervisor CSRs */ 217 target_ulong hstatus; 218 target_ulong hedeleg; 219 uint64_t hideleg; 220 target_ulong hcounteren; 221 target_ulong htval; 222 target_ulong htinst; 223 target_ulong hgatp; 224 target_ulong hgeie; 225 target_ulong hgeip; 226 uint64_t htimedelta; 227 228 /* Hypervisor controlled virtual interrupt priorities */ 229 target_ulong hvictl; 230 uint8_t hviprio[64]; 231 232 /* Upper 64-bits of 128-bit CSRs */ 233 uint64_t mscratchh; 234 uint64_t sscratchh; 235 236 /* Virtual CSRs */ 237 /* 238 * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. 239 * For RV64 this is a 64-bit vsstatus. 240 */ 241 uint64_t vsstatus; 242 target_ulong vstvec; 243 target_ulong vsscratch; 244 target_ulong vsepc; 245 target_ulong vscause; 246 target_ulong vstval; 247 target_ulong vsatp; 248 249 /* AIA VS-mode CSRs */ 250 target_ulong vsiselect; 251 252 target_ulong mtval2; 253 target_ulong mtinst; 254 255 /* HS Backup CSRs */ 256 target_ulong stvec_hs; 257 target_ulong sscratch_hs; 258 target_ulong sepc_hs; 259 target_ulong scause_hs; 260 target_ulong stval_hs; 261 target_ulong satp_hs; 262 uint64_t mstatus_hs; 263 264 /* Signals whether the current exception occurred with two-stage address 265 translation active. */ 266 bool two_stage_lookup; 267 268 target_ulong scounteren; 269 target_ulong mcounteren; 270 271 target_ulong sscratch; 272 target_ulong mscratch; 273 274 /* temporary htif regs */ 275 uint64_t mfromhost; 276 uint64_t mtohost; 277 uint64_t timecmp; 278 279 /* physical memory protection */ 280 pmp_table_t pmp_state; 281 target_ulong mseccfg; 282 283 /* trigger module */ 284 target_ulong trigger_cur; 285 type2_trigger_t type2_trig[TRIGGER_TYPE2_NUM]; 286 287 /* machine specific rdtime callback */ 288 uint64_t (*rdtime_fn)(uint32_t); 289 uint32_t rdtime_fn_arg; 290 291 /* machine specific AIA ireg read-modify-write callback */ 292 #define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \ 293 ((((__xlen) & 0xff) << 24) | \ 294 (((__vgein) & 0x3f) << 20) | \ 295 (((__virt) & 0x1) << 18) | \ 296 (((__priv) & 0x3) << 16) | \ 297 (__isel & 0xffff)) 298 #define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff) 299 #define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3) 300 #define AIA_IREG_VIRT(__ireg) (((__ireg) >> 18) & 0x1) 301 #define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 20) & 0x3f) 302 #define AIA_IREG_XLEN(__ireg) (((__ireg) >> 24) & 0xff) 303 int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg, 304 target_ulong *val, target_ulong new_val, target_ulong write_mask); 305 void *aia_ireg_rmw_fn_arg[4]; 306 307 /* True if in debugger mode. */ 308 bool debugger; 309 310 /* 311 * CSRs for PointerMasking extension 312 */ 313 target_ulong mmte; 314 target_ulong mpmmask; 315 target_ulong mpmbase; 316 target_ulong spmmask; 317 target_ulong spmbase; 318 target_ulong upmmask; 319 target_ulong upmbase; 320 321 /* CSRs for execution enviornment configuration */ 322 uint64_t menvcfg; 323 target_ulong senvcfg; 324 uint64_t henvcfg; 325 #endif 326 target_ulong cur_pmmask; 327 target_ulong cur_pmbase; 328 329 float_status fp_status; 330 331 /* Fields from here on are preserved across CPU reset. */ 332 QEMUTimer *timer; /* Internal timer */ 333 334 hwaddr kernel_addr; 335 hwaddr fdt_addr; 336 337 /* kvm timer */ 338 bool kvm_timer_dirty; 339 uint64_t kvm_timer_time; 340 uint64_t kvm_timer_compare; 341 uint64_t kvm_timer_state; 342 uint64_t kvm_timer_frequency; 343 }; 344 345 OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) 346 347 /** 348 * RISCVCPUClass: 349 * @parent_realize: The parent class' realize handler. 350 * @parent_reset: The parent class' reset handler. 351 * 352 * A RISCV CPU model. 353 */ 354 struct RISCVCPUClass { 355 /*< private >*/ 356 CPUClass parent_class; 357 /*< public >*/ 358 DeviceRealize parent_realize; 359 DeviceReset parent_reset; 360 }; 361 362 struct RISCVCPUConfig { 363 bool ext_i; 364 bool ext_e; 365 bool ext_g; 366 bool ext_m; 367 bool ext_a; 368 bool ext_f; 369 bool ext_d; 370 bool ext_c; 371 bool ext_s; 372 bool ext_u; 373 bool ext_h; 374 bool ext_j; 375 bool ext_v; 376 bool ext_zba; 377 bool ext_zbb; 378 bool ext_zbc; 379 bool ext_zbs; 380 bool ext_counters; 381 bool ext_ifencei; 382 bool ext_icsr; 383 bool ext_svinval; 384 bool ext_svnapot; 385 bool ext_svpbmt; 386 bool ext_zdinx; 387 bool ext_zfh; 388 bool ext_zfhmin; 389 bool ext_zfinx; 390 bool ext_zhinx; 391 bool ext_zhinxmin; 392 bool ext_zve32f; 393 bool ext_zve64f; 394 395 /* Vendor-specific custom extensions */ 396 bool ext_XVentanaCondOps; 397 398 char *priv_spec; 399 char *user_spec; 400 char *bext_spec; 401 char *vext_spec; 402 uint16_t vlen; 403 uint16_t elen; 404 bool mmu; 405 bool pmp; 406 bool epmp; 407 bool aia; 408 uint64_t resetvec; 409 }; 410 411 typedef struct RISCVCPUConfig RISCVCPUConfig; 412 413 /** 414 * RISCVCPU: 415 * @env: #CPURISCVState 416 * 417 * A RISCV CPU. 418 */ 419 struct ArchCPU { 420 /*< private >*/ 421 CPUState parent_obj; 422 /*< public >*/ 423 CPUNegativeOffsetState neg; 424 CPURISCVState env; 425 426 char *dyn_csr_xml; 427 char *dyn_vreg_xml; 428 429 /* Configuration Settings */ 430 RISCVCPUConfig cfg; 431 }; 432 433 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) 434 { 435 return (env->misa_ext & ext) != 0; 436 } 437 438 static inline bool riscv_feature(CPURISCVState *env, int feature) 439 { 440 return env->features & (1ULL << feature); 441 } 442 443 static inline void riscv_set_feature(CPURISCVState *env, int feature) 444 { 445 env->features |= (1ULL << feature); 446 } 447 448 #include "cpu_user.h" 449 450 extern const char * const riscv_int_regnames[]; 451 extern const char * const riscv_int_regnamesh[]; 452 extern const char * const riscv_fpr_regnames[]; 453 454 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); 455 void riscv_cpu_do_interrupt(CPUState *cpu); 456 int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 457 int cpuid, void *opaque); 458 int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 459 int cpuid, void *opaque); 460 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 461 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 462 int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero); 463 uint8_t riscv_cpu_default_priority(int irq); 464 int riscv_cpu_mirq_pending(CPURISCVState *env); 465 int riscv_cpu_sirq_pending(CPURISCVState *env); 466 int riscv_cpu_vsirq_pending(CPURISCVState *env); 467 bool riscv_cpu_fp_enabled(CPURISCVState *env); 468 target_ulong riscv_cpu_get_geilen(CPURISCVState *env); 469 void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); 470 bool riscv_cpu_vector_enabled(CPURISCVState *env); 471 bool riscv_cpu_virt_enabled(CPURISCVState *env); 472 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); 473 bool riscv_cpu_two_stage_lookup(int mmu_idx); 474 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); 475 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 476 G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 477 MMUAccessType access_type, int mmu_idx, 478 uintptr_t retaddr); 479 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 480 MMUAccessType access_type, int mmu_idx, 481 bool probe, uintptr_t retaddr); 482 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 483 vaddr addr, unsigned size, 484 MMUAccessType access_type, 485 int mmu_idx, MemTxAttrs attrs, 486 MemTxResult response, uintptr_t retaddr); 487 char *riscv_isa_string(RISCVCPU *cpu); 488 void riscv_cpu_list(void); 489 490 #define cpu_list riscv_cpu_list 491 #define cpu_mmu_index riscv_cpu_mmu_index 492 493 #ifndef CONFIG_USER_ONLY 494 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); 495 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); 496 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); 497 uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value); 498 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ 499 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t), 500 uint32_t arg); 501 void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, 502 int (*rmw_fn)(void *arg, 503 target_ulong reg, 504 target_ulong *val, 505 target_ulong new_val, 506 target_ulong write_mask), 507 void *rmw_fn_arg); 508 #endif 509 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); 510 511 void riscv_translate_init(void); 512 G_NORETURN void riscv_raise_exception(CPURISCVState *env, 513 uint32_t exception, uintptr_t pc); 514 515 target_ulong riscv_cpu_get_fflags(CPURISCVState *env); 516 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); 517 518 #define TB_FLAGS_PRIV_MMU_MASK 3 519 #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2) 520 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS 521 #define TB_FLAGS_MSTATUS_VS MSTATUS_VS 522 523 #include "exec/cpu-all.h" 524 525 FIELD(TB_FLAGS, MEM_IDX, 0, 3) 526 FIELD(TB_FLAGS, LMUL, 3, 3) 527 FIELD(TB_FLAGS, SEW, 6, 3) 528 /* Skip MSTATUS_VS (0x600) bits */ 529 FIELD(TB_FLAGS, VL_EQ_VLMAX, 11, 1) 530 FIELD(TB_FLAGS, VILL, 12, 1) 531 /* Skip MSTATUS_FS (0x6000) bits */ 532 /* Is a Hypervisor instruction load/store allowed? */ 533 FIELD(TB_FLAGS, HLSX, 15, 1) 534 FIELD(TB_FLAGS, MSTATUS_HS_FS, 16, 2) 535 FIELD(TB_FLAGS, MSTATUS_HS_VS, 18, 2) 536 /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ 537 FIELD(TB_FLAGS, XL, 20, 2) 538 /* If PointerMasking should be applied */ 539 FIELD(TB_FLAGS, PM_MASK_ENABLED, 22, 1) 540 FIELD(TB_FLAGS, PM_BASE_ENABLED, 23, 1) 541 542 #ifdef TARGET_RISCV32 543 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) 544 #else 545 static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) 546 { 547 return env->misa_mxl; 548 } 549 #endif 550 #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env))) 551 552 #if defined(TARGET_RISCV32) 553 #define cpu_recompute_xl(env) ((void)(env), MXL_RV32) 554 #else 555 static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) 556 { 557 RISCVMXL xl = env->misa_mxl; 558 #if !defined(CONFIG_USER_ONLY) 559 /* 560 * When emulating a 32-bit-only cpu, use RV32. 561 * When emulating a 64-bit cpu, and MXL has been reduced to RV32, 562 * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened 563 * back to RV64 for lower privs. 564 */ 565 if (xl != MXL_RV32) { 566 switch (env->priv) { 567 case PRV_M: 568 break; 569 case PRV_U: 570 xl = get_field(env->mstatus, MSTATUS64_UXL); 571 break; 572 default: /* PRV_S | PRV_H */ 573 xl = get_field(env->mstatus, MSTATUS64_SXL); 574 break; 575 } 576 } 577 #endif 578 return xl; 579 } 580 #endif 581 582 static inline int riscv_cpu_xlen(CPURISCVState *env) 583 { 584 return 16 << env->xl; 585 } 586 587 #ifdef TARGET_RISCV32 588 #define riscv_cpu_sxl(env) ((void)(env), MXL_RV32) 589 #else 590 static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env) 591 { 592 #ifdef CONFIG_USER_ONLY 593 return env->misa_mxl; 594 #else 595 return get_field(env->mstatus, MSTATUS64_SXL); 596 #endif 597 } 598 #endif 599 600 /* 601 * Encode LMUL to lmul as follows: 602 * LMUL vlmul lmul 603 * 1 000 0 604 * 2 001 1 605 * 4 010 2 606 * 8 011 3 607 * - 100 - 608 * 1/8 101 -3 609 * 1/4 110 -2 610 * 1/2 111 -1 611 * 612 * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul) 613 * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8 614 * => VLMAX = vlen >> (1 + 3 - (-3)) 615 * = 256 >> 7 616 * = 2 617 */ 618 static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) 619 { 620 uint8_t sew = FIELD_EX64(vtype, VTYPE, VSEW); 621 int8_t lmul = sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3); 622 return cpu->cfg.vlen >> (sew + 3 - lmul); 623 } 624 625 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 626 target_ulong *cs_base, uint32_t *pflags); 627 628 void riscv_cpu_update_mask(CPURISCVState *env); 629 630 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, 631 target_ulong *ret_value, 632 target_ulong new_value, target_ulong write_mask); 633 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, 634 target_ulong *ret_value, 635 target_ulong new_value, 636 target_ulong write_mask); 637 638 static inline void riscv_csr_write(CPURISCVState *env, int csrno, 639 target_ulong val) 640 { 641 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); 642 } 643 644 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) 645 { 646 target_ulong val = 0; 647 riscv_csrrw(env, csrno, &val, 0, 0); 648 return val; 649 } 650 651 typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, 652 int csrno); 653 typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, 654 target_ulong *ret_value); 655 typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, 656 target_ulong new_value); 657 typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, 658 target_ulong *ret_value, 659 target_ulong new_value, 660 target_ulong write_mask); 661 662 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, 663 Int128 *ret_value, 664 Int128 new_value, Int128 write_mask); 665 666 typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno, 667 Int128 *ret_value); 668 typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int csrno, 669 Int128 new_value); 670 671 typedef struct { 672 const char *name; 673 riscv_csr_predicate_fn predicate; 674 riscv_csr_read_fn read; 675 riscv_csr_write_fn write; 676 riscv_csr_op_fn op; 677 riscv_csr_read128_fn read128; 678 riscv_csr_write128_fn write128; 679 /* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0) */ 680 uint32_t min_priv_ver; 681 } riscv_csr_operations; 682 683 /* CSR function table constants */ 684 enum { 685 CSR_TABLE_SIZE = 0x1000 686 }; 687 688 /* CSR function table */ 689 extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; 690 691 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); 692 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); 693 694 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); 695 696 #endif /* RISCV_CPU_H */ 697