1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef RISCV_CPU_H 21 #define RISCV_CPU_H 22 23 #include "hw/core/cpu.h" 24 #include "hw/registerfields.h" 25 #include "exec/cpu-defs.h" 26 #include "fpu/softfloat-types.h" 27 #include "qom/object.h" 28 29 #define TCG_GUEST_DEFAULT_MO 0 30 31 #define TYPE_RISCV_CPU "riscv-cpu" 32 33 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU 34 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) 35 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU 36 37 #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") 38 #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") 39 #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") 40 #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") 41 #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") 42 #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") 43 #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") 44 #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") 45 #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") 46 47 #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2)) 48 #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2)) 49 50 #if defined(TARGET_RISCV32) 51 #define RVXLEN RV32 52 #elif defined(TARGET_RISCV64) 53 #define RVXLEN RV64 54 #endif 55 56 #define RV(x) ((target_ulong)1 << (x - 'A')) 57 58 #define RVI RV('I') 59 #define RVE RV('E') /* E and I are mutually exclusive */ 60 #define RVM RV('M') 61 #define RVA RV('A') 62 #define RVF RV('F') 63 #define RVD RV('D') 64 #define RVV RV('V') 65 #define RVC RV('C') 66 #define RVS RV('S') 67 #define RVU RV('U') 68 #define RVH RV('H') 69 70 /* S extension denotes that Supervisor mode exists, however it is possible 71 to have a core that support S mode but does not have an MMU and there 72 is currently no bit in misa to indicate whether an MMU exists or not 73 so a cpu features bitfield is required, likewise for optional PMP support */ 74 enum { 75 RISCV_FEATURE_MMU, 76 RISCV_FEATURE_PMP, 77 RISCV_FEATURE_MISA 78 }; 79 80 #define PRIV_VERSION_1_10_0 0x00011000 81 #define PRIV_VERSION_1_11_0 0x00011100 82 83 #define VEXT_VERSION_0_07_1 0x00000701 84 85 #define TRANSLATE_PMP_FAIL 2 86 #define TRANSLATE_FAIL 1 87 #define TRANSLATE_SUCCESS 0 88 #define MMU_USER_IDX 3 89 90 #define MAX_RISCV_PMPS (16) 91 92 typedef struct CPURISCVState CPURISCVState; 93 94 #include "pmp.h" 95 96 #define RV_VLEN_MAX 256 97 98 FIELD(VTYPE, VLMUL, 0, 2) 99 FIELD(VTYPE, VSEW, 2, 3) 100 FIELD(VTYPE, VEDIV, 5, 2) 101 FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 9) 102 FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1) 103 104 struct CPURISCVState { 105 target_ulong gpr[32]; 106 uint64_t fpr[32]; /* assume both F and D extensions */ 107 108 /* vector coprocessor state. */ 109 uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); 110 target_ulong vxrm; 111 target_ulong vxsat; 112 target_ulong vl; 113 target_ulong vstart; 114 target_ulong vtype; 115 116 target_ulong pc; 117 target_ulong load_res; 118 target_ulong load_val; 119 120 target_ulong frm; 121 122 target_ulong badaddr; 123 target_ulong guest_phys_fault_addr; 124 125 target_ulong priv_ver; 126 target_ulong vext_ver; 127 target_ulong misa; 128 target_ulong misa_mask; 129 130 uint32_t features; 131 132 #ifdef CONFIG_USER_ONLY 133 uint32_t elf_flags; 134 #endif 135 136 #ifndef CONFIG_USER_ONLY 137 target_ulong priv; 138 /* This contains QEMU specific information about the virt state. */ 139 target_ulong virt; 140 target_ulong resetvec; 141 142 target_ulong mhartid; 143 target_ulong mstatus; 144 145 target_ulong mip; 146 147 #ifdef TARGET_RISCV32 148 target_ulong mstatush; 149 #endif 150 151 uint32_t miclaim; 152 153 target_ulong mie; 154 target_ulong mideleg; 155 156 target_ulong sptbr; /* until: priv-1.9.1 */ 157 target_ulong satp; /* since: priv-1.10.0 */ 158 target_ulong sbadaddr; 159 target_ulong mbadaddr; 160 target_ulong medeleg; 161 162 target_ulong stvec; 163 target_ulong sepc; 164 target_ulong scause; 165 166 target_ulong mtvec; 167 target_ulong mepc; 168 target_ulong mcause; 169 target_ulong mtval; /* since: priv-1.10.0 */ 170 171 /* Hypervisor CSRs */ 172 target_ulong hstatus; 173 target_ulong hedeleg; 174 target_ulong hideleg; 175 target_ulong hcounteren; 176 target_ulong htval; 177 target_ulong htinst; 178 target_ulong hgatp; 179 uint64_t htimedelta; 180 181 /* Virtual CSRs */ 182 target_ulong vsstatus; 183 target_ulong vstvec; 184 target_ulong vsscratch; 185 target_ulong vsepc; 186 target_ulong vscause; 187 target_ulong vstval; 188 target_ulong vsatp; 189 #ifdef TARGET_RISCV32 190 target_ulong vsstatush; 191 #endif 192 193 target_ulong mtval2; 194 target_ulong mtinst; 195 196 /* HS Backup CSRs */ 197 target_ulong stvec_hs; 198 target_ulong sscratch_hs; 199 target_ulong sepc_hs; 200 target_ulong scause_hs; 201 target_ulong stval_hs; 202 target_ulong satp_hs; 203 target_ulong mstatus_hs; 204 #ifdef TARGET_RISCV32 205 target_ulong mstatush_hs; 206 #endif 207 208 target_ulong scounteren; 209 target_ulong mcounteren; 210 211 target_ulong sscratch; 212 target_ulong mscratch; 213 214 /* temporary htif regs */ 215 uint64_t mfromhost; 216 uint64_t mtohost; 217 uint64_t timecmp; 218 219 /* physical memory protection */ 220 pmp_table_t pmp_state; 221 222 /* machine specific rdtime callback */ 223 uint64_t (*rdtime_fn)(void); 224 225 /* True if in debugger mode. */ 226 bool debugger; 227 #endif 228 229 float_status fp_status; 230 231 /* Fields from here on are preserved across CPU reset. */ 232 QEMUTimer *timer; /* Internal timer */ 233 }; 234 235 OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass, 236 riscv_cpu, RISCV_CPU) 237 238 /** 239 * RISCVCPUClass: 240 * @parent_realize: The parent class' realize handler. 241 * @parent_reset: The parent class' reset handler. 242 * 243 * A RISCV CPU model. 244 */ 245 struct RISCVCPUClass { 246 /*< private >*/ 247 CPUClass parent_class; 248 /*< public >*/ 249 DeviceRealize parent_realize; 250 DeviceReset parent_reset; 251 }; 252 253 /** 254 * RISCVCPU: 255 * @env: #CPURISCVState 256 * 257 * A RISCV CPU. 258 */ 259 struct RISCVCPU { 260 /*< private >*/ 261 CPUState parent_obj; 262 /*< public >*/ 263 CPUNegativeOffsetState neg; 264 CPURISCVState env; 265 266 /* Configuration Settings */ 267 struct { 268 bool ext_i; 269 bool ext_e; 270 bool ext_g; 271 bool ext_m; 272 bool ext_a; 273 bool ext_f; 274 bool ext_d; 275 bool ext_c; 276 bool ext_s; 277 bool ext_u; 278 bool ext_h; 279 bool ext_v; 280 bool ext_counters; 281 bool ext_ifencei; 282 bool ext_icsr; 283 284 char *priv_spec; 285 char *user_spec; 286 char *vext_spec; 287 uint16_t vlen; 288 uint16_t elen; 289 bool mmu; 290 bool pmp; 291 } cfg; 292 }; 293 294 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) 295 { 296 return (env->misa & ext) != 0; 297 } 298 299 static inline bool riscv_feature(CPURISCVState *env, int feature) 300 { 301 return env->features & (1ULL << feature); 302 } 303 304 #include "cpu_user.h" 305 #include "cpu_bits.h" 306 307 extern const char * const riscv_int_regnames[]; 308 extern const char * const riscv_fpr_regnames[]; 309 extern const char * const riscv_excp_names[]; 310 extern const char * const riscv_intr_names[]; 311 312 void riscv_cpu_do_interrupt(CPUState *cpu); 313 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 314 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 315 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); 316 bool riscv_cpu_fp_enabled(CPURISCVState *env); 317 bool riscv_cpu_virt_enabled(CPURISCVState *env); 318 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); 319 bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env); 320 void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable); 321 bool riscv_cpu_two_stage_lookup(CPURISCVState *env); 322 void riscv_cpu_set_two_stage_lookup(CPURISCVState *env, bool enable); 323 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); 324 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 325 void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 326 MMUAccessType access_type, int mmu_idx, 327 uintptr_t retaddr); 328 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 329 MMUAccessType access_type, int mmu_idx, 330 bool probe, uintptr_t retaddr); 331 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 332 vaddr addr, unsigned size, 333 MMUAccessType access_type, 334 int mmu_idx, MemTxAttrs attrs, 335 MemTxResult response, uintptr_t retaddr); 336 char *riscv_isa_string(RISCVCPU *cpu); 337 void riscv_cpu_list(void); 338 339 #define cpu_signal_handler riscv_cpu_signal_handler 340 #define cpu_list riscv_cpu_list 341 #define cpu_mmu_index riscv_cpu_mmu_index 342 343 #ifndef CONFIG_USER_ONLY 344 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); 345 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts); 346 uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value); 347 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ 348 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void)); 349 #endif 350 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); 351 352 void riscv_translate_init(void); 353 int riscv_cpu_signal_handler(int host_signum, void *pinfo, void *puc); 354 void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env, 355 uint32_t exception, uintptr_t pc); 356 357 target_ulong riscv_cpu_get_fflags(CPURISCVState *env); 358 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); 359 360 #define TB_FLAGS_MMU_MASK 3 361 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS 362 363 typedef CPURISCVState CPUArchState; 364 typedef RISCVCPU ArchCPU; 365 #include "exec/cpu-all.h" 366 367 FIELD(TB_FLAGS, VL_EQ_VLMAX, 2, 1) 368 FIELD(TB_FLAGS, LMUL, 3, 2) 369 FIELD(TB_FLAGS, SEW, 5, 3) 370 FIELD(TB_FLAGS, VILL, 8, 1) 371 372 /* 373 * A simplification for VLMAX 374 * = (1 << LMUL) * VLEN / (8 * (1 << SEW)) 375 * = (VLEN << LMUL) / (8 << SEW) 376 * = (VLEN << LMUL) >> (SEW + 3) 377 * = VLEN >> (SEW + 3 - LMUL) 378 */ 379 static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) 380 { 381 uint8_t sew, lmul; 382 383 sew = FIELD_EX64(vtype, VTYPE, VSEW); 384 lmul = FIELD_EX64(vtype, VTYPE, VLMUL); 385 return cpu->cfg.vlen >> (sew + 3 - lmul); 386 } 387 388 static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 389 target_ulong *cs_base, uint32_t *pflags) 390 { 391 uint32_t flags = 0; 392 393 *pc = env->pc; 394 *cs_base = 0; 395 396 if (riscv_has_ext(env, RVV)) { 397 uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype); 398 bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl); 399 flags = FIELD_DP32(flags, TB_FLAGS, VILL, 400 FIELD_EX64(env->vtype, VTYPE, VILL)); 401 flags = FIELD_DP32(flags, TB_FLAGS, SEW, 402 FIELD_EX64(env->vtype, VTYPE, VSEW)); 403 flags = FIELD_DP32(flags, TB_FLAGS, LMUL, 404 FIELD_EX64(env->vtype, VTYPE, VLMUL)); 405 flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); 406 } else { 407 flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1); 408 } 409 410 #ifdef CONFIG_USER_ONLY 411 flags |= TB_FLAGS_MSTATUS_FS; 412 #else 413 flags |= cpu_mmu_index(env, 0); 414 if (riscv_cpu_fp_enabled(env)) { 415 flags |= env->mstatus & MSTATUS_FS; 416 } 417 #endif 418 *pflags = flags; 419 } 420 421 int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, 422 target_ulong new_value, target_ulong write_mask); 423 int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value, 424 target_ulong new_value, target_ulong write_mask); 425 426 static inline void riscv_csr_write(CPURISCVState *env, int csrno, 427 target_ulong val) 428 { 429 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); 430 } 431 432 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) 433 { 434 target_ulong val = 0; 435 riscv_csrrw(env, csrno, &val, 0, 0); 436 return val; 437 } 438 439 typedef int (*riscv_csr_predicate_fn)(CPURISCVState *env, int csrno); 440 typedef int (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, 441 target_ulong *ret_value); 442 typedef int (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, 443 target_ulong new_value); 444 typedef int (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, 445 target_ulong *ret_value, target_ulong new_value, target_ulong write_mask); 446 447 typedef struct { 448 riscv_csr_predicate_fn predicate; 449 riscv_csr_read_fn read; 450 riscv_csr_write_fn write; 451 riscv_csr_op_fn op; 452 } riscv_csr_operations; 453 454 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); 455 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); 456 457 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); 458 459 #endif /* RISCV_CPU_H */ 460