xref: /openbmc/qemu/target/riscv/cpu.h (revision 8f42415f)
1 /*
2  * QEMU RISC-V CPU
3  *
4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5  * Copyright (c) 2017-2018 SiFive, Inc.
6  *
7  * This program is free software; you can redistribute it and/or modify it
8  * under the terms and conditions of the GNU General Public License,
9  * version 2 or later, as published by the Free Software Foundation.
10  *
11  * This program is distributed in the hope it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along with
17  * this program.  If not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 #ifndef RISCV_CPU_H
21 #define RISCV_CPU_H
22 
23 #include "hw/core/cpu.h"
24 #include "hw/registerfields.h"
25 #include "exec/cpu-defs.h"
26 #include "qemu/cpu-float.h"
27 #include "qom/object.h"
28 #include "qemu/int128.h"
29 #include "cpu_bits.h"
30 
31 #define TCG_GUEST_DEFAULT_MO 0
32 
33 /*
34  * RISC-V-specific extra insn start words:
35  * 1: Original instruction opcode
36  */
37 #define TARGET_INSN_START_EXTRA_WORDS 1
38 
39 #define TYPE_RISCV_CPU "riscv-cpu"
40 
41 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
42 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
43 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
44 
45 #define TYPE_RISCV_CPU_ANY              RISCV_CPU_TYPE_NAME("any")
46 #define TYPE_RISCV_CPU_BASE32           RISCV_CPU_TYPE_NAME("rv32")
47 #define TYPE_RISCV_CPU_BASE64           RISCV_CPU_TYPE_NAME("rv64")
48 #define TYPE_RISCV_CPU_BASE128          RISCV_CPU_TYPE_NAME("x-rv128")
49 #define TYPE_RISCV_CPU_IBEX             RISCV_CPU_TYPE_NAME("lowrisc-ibex")
50 #define TYPE_RISCV_CPU_SHAKTI_C         RISCV_CPU_TYPE_NAME("shakti-c")
51 #define TYPE_RISCV_CPU_SIFIVE_E31       RISCV_CPU_TYPE_NAME("sifive-e31")
52 #define TYPE_RISCV_CPU_SIFIVE_E34       RISCV_CPU_TYPE_NAME("sifive-e34")
53 #define TYPE_RISCV_CPU_SIFIVE_E51       RISCV_CPU_TYPE_NAME("sifive-e51")
54 #define TYPE_RISCV_CPU_SIFIVE_U34       RISCV_CPU_TYPE_NAME("sifive-u34")
55 #define TYPE_RISCV_CPU_SIFIVE_U54       RISCV_CPU_TYPE_NAME("sifive-u54")
56 #define TYPE_RISCV_CPU_HOST             RISCV_CPU_TYPE_NAME("host")
57 
58 #if defined(TARGET_RISCV32)
59 # define TYPE_RISCV_CPU_BASE            TYPE_RISCV_CPU_BASE32
60 #elif defined(TARGET_RISCV64)
61 # define TYPE_RISCV_CPU_BASE            TYPE_RISCV_CPU_BASE64
62 #endif
63 
64 #define RV(x) ((target_ulong)1 << (x - 'A'))
65 
66 #define RVI RV('I')
67 #define RVE RV('E') /* E and I are mutually exclusive */
68 #define RVM RV('M')
69 #define RVA RV('A')
70 #define RVF RV('F')
71 #define RVD RV('D')
72 #define RVV RV('V')
73 #define RVC RV('C')
74 #define RVS RV('S')
75 #define RVU RV('U')
76 #define RVH RV('H')
77 #define RVJ RV('J')
78 
79 /* S extension denotes that Supervisor mode exists, however it is possible
80    to have a core that support S mode but does not have an MMU and there
81    is currently no bit in misa to indicate whether an MMU exists or not
82    so a cpu features bitfield is required, likewise for optional PMP support */
83 enum {
84     RISCV_FEATURE_MMU,
85     RISCV_FEATURE_PMP,
86     RISCV_FEATURE_EPMP,
87     RISCV_FEATURE_MISA,
88     RISCV_FEATURE_AIA,
89     RISCV_FEATURE_DEBUG
90 };
91 
92 /* Privileged specification version */
93 enum {
94     PRIV_VERSION_1_10_0 = 0,
95     PRIV_VERSION_1_11_0,
96     PRIV_VERSION_1_12_0,
97 };
98 
99 #define VEXT_VERSION_1_00_0 0x00010000
100 
101 enum {
102     TRANSLATE_SUCCESS,
103     TRANSLATE_FAIL,
104     TRANSLATE_PMP_FAIL,
105     TRANSLATE_G_STAGE_FAIL
106 };
107 
108 #define MMU_USER_IDX 3
109 
110 #define MAX_RISCV_PMPS (16)
111 
112 typedef struct CPUArchState CPURISCVState;
113 
114 #if !defined(CONFIG_USER_ONLY)
115 #include "pmp.h"
116 #include "debug.h"
117 #endif
118 
119 #define RV_VLEN_MAX 1024
120 
121 FIELD(VTYPE, VLMUL, 0, 3)
122 FIELD(VTYPE, VSEW, 3, 3)
123 FIELD(VTYPE, VTA, 6, 1)
124 FIELD(VTYPE, VMA, 7, 1)
125 FIELD(VTYPE, VEDIV, 8, 2)
126 FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11)
127 
128 struct CPUArchState {
129     target_ulong gpr[32];
130     target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */
131     uint64_t fpr[32]; /* assume both F and D extensions */
132 
133     /* vector coprocessor state. */
134     uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16);
135     target_ulong vxrm;
136     target_ulong vxsat;
137     target_ulong vl;
138     target_ulong vstart;
139     target_ulong vtype;
140     bool vill;
141 
142     target_ulong pc;
143     target_ulong load_res;
144     target_ulong load_val;
145 
146     target_ulong frm;
147 
148     target_ulong badaddr;
149     target_ulong bins;
150 
151     target_ulong guest_phys_fault_addr;
152 
153     target_ulong priv_ver;
154     target_ulong bext_ver;
155     target_ulong vext_ver;
156 
157     /* RISCVMXL, but uint32_t for vmstate migration */
158     uint32_t misa_mxl;      /* current mxl */
159     uint32_t misa_mxl_max;  /* max mxl for this cpu */
160     uint32_t misa_ext;      /* current extensions */
161     uint32_t misa_ext_mask; /* max ext for this cpu */
162     uint32_t xl;            /* current xlen */
163 
164     /* 128-bit helpers upper part return value */
165     target_ulong retxh;
166 
167     uint32_t features;
168 
169 #ifdef CONFIG_USER_ONLY
170     uint32_t elf_flags;
171 #endif
172 
173 #ifndef CONFIG_USER_ONLY
174     target_ulong priv;
175     /* This contains QEMU specific information about the virt state. */
176     target_ulong virt;
177     target_ulong geilen;
178     target_ulong resetvec;
179 
180     target_ulong mhartid;
181     /*
182      * For RV32 this is 32-bit mstatus and 32-bit mstatush.
183      * For RV64 this is a 64-bit mstatus.
184      */
185     uint64_t mstatus;
186 
187     uint64_t mip;
188     /*
189      * MIP contains the software writable version of SEIP ORed with the
190      * external interrupt value. The MIP register is always up-to-date.
191      * To keep track of the current source, we also save booleans of the values
192      * here.
193      */
194     bool external_seip;
195     bool software_seip;
196 
197     uint64_t miclaim;
198 
199     uint64_t mie;
200     uint64_t mideleg;
201 
202     target_ulong satp;   /* since: priv-1.10.0 */
203     target_ulong stval;
204     target_ulong medeleg;
205 
206     target_ulong stvec;
207     target_ulong sepc;
208     target_ulong scause;
209 
210     target_ulong mtvec;
211     target_ulong mepc;
212     target_ulong mcause;
213     target_ulong mtval;  /* since: priv-1.10.0 */
214 
215     /* Machine and Supervisor interrupt priorities */
216     uint8_t miprio[64];
217     uint8_t siprio[64];
218 
219     /* AIA CSRs */
220     target_ulong miselect;
221     target_ulong siselect;
222 
223     /* Hypervisor CSRs */
224     target_ulong hstatus;
225     target_ulong hedeleg;
226     uint64_t hideleg;
227     target_ulong hcounteren;
228     target_ulong htval;
229     target_ulong htinst;
230     target_ulong hgatp;
231     target_ulong hgeie;
232     target_ulong hgeip;
233     uint64_t htimedelta;
234 
235     /* Hypervisor controlled virtual interrupt priorities */
236     target_ulong hvictl;
237     uint8_t hviprio[64];
238 
239     /* Upper 64-bits of 128-bit CSRs */
240     uint64_t mscratchh;
241     uint64_t sscratchh;
242 
243     /* Virtual CSRs */
244     /*
245      * For RV32 this is 32-bit vsstatus and 32-bit vsstatush.
246      * For RV64 this is a 64-bit vsstatus.
247      */
248     uint64_t vsstatus;
249     target_ulong vstvec;
250     target_ulong vsscratch;
251     target_ulong vsepc;
252     target_ulong vscause;
253     target_ulong vstval;
254     target_ulong vsatp;
255 
256     /* AIA VS-mode CSRs */
257     target_ulong vsiselect;
258 
259     target_ulong mtval2;
260     target_ulong mtinst;
261 
262     /* HS Backup CSRs */
263     target_ulong stvec_hs;
264     target_ulong sscratch_hs;
265     target_ulong sepc_hs;
266     target_ulong scause_hs;
267     target_ulong stval_hs;
268     target_ulong satp_hs;
269     uint64_t mstatus_hs;
270 
271     /* Signals whether the current exception occurred with two-stage address
272        translation active. */
273     bool two_stage_lookup;
274 
275     target_ulong scounteren;
276     target_ulong mcounteren;
277 
278     target_ulong sscratch;
279     target_ulong mscratch;
280 
281     /* temporary htif regs */
282     uint64_t mfromhost;
283     uint64_t mtohost;
284     uint64_t timecmp;
285 
286     /* physical memory protection */
287     pmp_table_t pmp_state;
288     target_ulong mseccfg;
289 
290     /* trigger module */
291     target_ulong trigger_cur;
292     type2_trigger_t type2_trig[TRIGGER_TYPE2_NUM];
293 
294     /* machine specific rdtime callback */
295     uint64_t (*rdtime_fn)(void *);
296     void *rdtime_fn_arg;
297 
298     /* machine specific AIA ireg read-modify-write callback */
299 #define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \
300     ((((__xlen) & 0xff) << 24) | \
301      (((__vgein) & 0x3f) << 20) | \
302      (((__virt) & 0x1) << 18) | \
303      (((__priv) & 0x3) << 16) | \
304      (__isel & 0xffff))
305 #define AIA_IREG_ISEL(__ireg)                  ((__ireg) & 0xffff)
306 #define AIA_IREG_PRIV(__ireg)                  (((__ireg) >> 16) & 0x3)
307 #define AIA_IREG_VIRT(__ireg)                  (((__ireg) >> 18) & 0x1)
308 #define AIA_IREG_VGEIN(__ireg)                 (((__ireg) >> 20) & 0x3f)
309 #define AIA_IREG_XLEN(__ireg)                  (((__ireg) >> 24) & 0xff)
310     int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg,
311         target_ulong *val, target_ulong new_val, target_ulong write_mask);
312     void *aia_ireg_rmw_fn_arg[4];
313 
314     /* True if in debugger mode.  */
315     bool debugger;
316 
317     /*
318      * CSRs for PointerMasking extension
319      */
320     target_ulong mmte;
321     target_ulong mpmmask;
322     target_ulong mpmbase;
323     target_ulong spmmask;
324     target_ulong spmbase;
325     target_ulong upmmask;
326     target_ulong upmbase;
327 
328     /* CSRs for execution enviornment configuration */
329     uint64_t menvcfg;
330     target_ulong senvcfg;
331     uint64_t henvcfg;
332 #endif
333     target_ulong cur_pmmask;
334     target_ulong cur_pmbase;
335 
336     float_status fp_status;
337 
338     /* Fields from here on are preserved across CPU reset. */
339     QEMUTimer *timer; /* Internal timer */
340 
341     hwaddr kernel_addr;
342     hwaddr fdt_addr;
343 
344     /* kvm timer */
345     bool kvm_timer_dirty;
346     uint64_t kvm_timer_time;
347     uint64_t kvm_timer_compare;
348     uint64_t kvm_timer_state;
349     uint64_t kvm_timer_frequency;
350 };
351 
352 OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
353 
354 /**
355  * RISCVCPUClass:
356  * @parent_realize: The parent class' realize handler.
357  * @parent_reset: The parent class' reset handler.
358  *
359  * A RISCV CPU model.
360  */
361 struct RISCVCPUClass {
362     /*< private >*/
363     CPUClass parent_class;
364     /*< public >*/
365     DeviceRealize parent_realize;
366     DeviceReset parent_reset;
367 };
368 
369 struct RISCVCPUConfig {
370     bool ext_i;
371     bool ext_e;
372     bool ext_g;
373     bool ext_m;
374     bool ext_a;
375     bool ext_f;
376     bool ext_d;
377     bool ext_c;
378     bool ext_s;
379     bool ext_u;
380     bool ext_h;
381     bool ext_j;
382     bool ext_v;
383     bool ext_zba;
384     bool ext_zbb;
385     bool ext_zbc;
386     bool ext_zbkb;
387     bool ext_zbkc;
388     bool ext_zbkx;
389     bool ext_zbs;
390     bool ext_zk;
391     bool ext_zkn;
392     bool ext_zknd;
393     bool ext_zkne;
394     bool ext_zknh;
395     bool ext_zkr;
396     bool ext_zks;
397     bool ext_zksed;
398     bool ext_zksh;
399     bool ext_zkt;
400     bool ext_counters;
401     bool ext_ifencei;
402     bool ext_icsr;
403     bool ext_svinval;
404     bool ext_svnapot;
405     bool ext_svpbmt;
406     bool ext_zdinx;
407     bool ext_zfh;
408     bool ext_zfhmin;
409     bool ext_zfinx;
410     bool ext_zhinx;
411     bool ext_zhinxmin;
412     bool ext_zve32f;
413     bool ext_zve64f;
414     bool ext_zmmul;
415 
416     uint32_t mvendorid;
417     uint64_t marchid;
418     uint64_t mimpid;
419 
420     /* Vendor-specific custom extensions */
421     bool ext_XVentanaCondOps;
422 
423     char *priv_spec;
424     char *user_spec;
425     char *bext_spec;
426     char *vext_spec;
427     uint16_t vlen;
428     uint16_t elen;
429     bool mmu;
430     bool pmp;
431     bool epmp;
432     bool aia;
433     bool debug;
434     uint64_t resetvec;
435 
436     bool short_isa_string;
437 };
438 
439 typedef struct RISCVCPUConfig RISCVCPUConfig;
440 
441 /**
442  * RISCVCPU:
443  * @env: #CPURISCVState
444  *
445  * A RISCV CPU.
446  */
447 struct ArchCPU {
448     /*< private >*/
449     CPUState parent_obj;
450     /*< public >*/
451     CPUNegativeOffsetState neg;
452     CPURISCVState env;
453 
454     char *dyn_csr_xml;
455     char *dyn_vreg_xml;
456 
457     /* Configuration Settings */
458     RISCVCPUConfig cfg;
459 };
460 
461 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
462 {
463     return (env->misa_ext & ext) != 0;
464 }
465 
466 static inline bool riscv_feature(CPURISCVState *env, int feature)
467 {
468     return env->features & (1ULL << feature);
469 }
470 
471 static inline void riscv_set_feature(CPURISCVState *env, int feature)
472 {
473     env->features |= (1ULL << feature);
474 }
475 
476 #include "cpu_user.h"
477 
478 extern const char * const riscv_int_regnames[];
479 extern const char * const riscv_int_regnamesh[];
480 extern const char * const riscv_fpr_regnames[];
481 
482 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async);
483 void riscv_cpu_do_interrupt(CPUState *cpu);
484 int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
485                                int cpuid, void *opaque);
486 int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
487                                int cpuid, void *opaque);
488 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
489 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
490 int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero);
491 uint8_t riscv_cpu_default_priority(int irq);
492 uint64_t riscv_cpu_all_pending(CPURISCVState *env);
493 int riscv_cpu_mirq_pending(CPURISCVState *env);
494 int riscv_cpu_sirq_pending(CPURISCVState *env);
495 int riscv_cpu_vsirq_pending(CPURISCVState *env);
496 bool riscv_cpu_fp_enabled(CPURISCVState *env);
497 target_ulong riscv_cpu_get_geilen(CPURISCVState *env);
498 void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen);
499 bool riscv_cpu_vector_enabled(CPURISCVState *env);
500 bool riscv_cpu_virt_enabled(CPURISCVState *env);
501 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
502 bool riscv_cpu_two_stage_lookup(int mmu_idx);
503 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
504 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
505 G_NORETURN void  riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
506                                                MMUAccessType access_type, int mmu_idx,
507                                                uintptr_t retaddr);
508 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
509                         MMUAccessType access_type, int mmu_idx,
510                         bool probe, uintptr_t retaddr);
511 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
512                                      vaddr addr, unsigned size,
513                                      MMUAccessType access_type,
514                                      int mmu_idx, MemTxAttrs attrs,
515                                      MemTxResult response, uintptr_t retaddr);
516 char *riscv_isa_string(RISCVCPU *cpu);
517 void riscv_cpu_list(void);
518 
519 #define cpu_list riscv_cpu_list
520 #define cpu_mmu_index riscv_cpu_mmu_index
521 
522 #ifndef CONFIG_USER_ONLY
523 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
524 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env);
525 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts);
526 uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value);
527 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
528 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *),
529                              void *arg);
530 void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv,
531                                    int (*rmw_fn)(void *arg,
532                                                  target_ulong reg,
533                                                  target_ulong *val,
534                                                  target_ulong new_val,
535                                                  target_ulong write_mask),
536                                    void *rmw_fn_arg);
537 #endif
538 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);
539 
540 void riscv_translate_init(void);
541 G_NORETURN void riscv_raise_exception(CPURISCVState *env,
542                                       uint32_t exception, uintptr_t pc);
543 
544 target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
545 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
546 
547 #define TB_FLAGS_PRIV_MMU_MASK                3
548 #define TB_FLAGS_PRIV_HYP_ACCESS_MASK   (1 << 2)
549 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS
550 #define TB_FLAGS_MSTATUS_VS MSTATUS_VS
551 
552 #include "exec/cpu-all.h"
553 
554 FIELD(TB_FLAGS, MEM_IDX, 0, 3)
555 FIELD(TB_FLAGS, LMUL, 3, 3)
556 FIELD(TB_FLAGS, SEW, 6, 3)
557 /* Skip MSTATUS_VS (0x600) bits */
558 FIELD(TB_FLAGS, VL_EQ_VLMAX, 11, 1)
559 FIELD(TB_FLAGS, VILL, 12, 1)
560 /* Skip MSTATUS_FS (0x6000) bits */
561 /* Is a Hypervisor instruction load/store allowed? */
562 FIELD(TB_FLAGS, HLSX, 15, 1)
563 FIELD(TB_FLAGS, MSTATUS_HS_FS, 16, 2)
564 FIELD(TB_FLAGS, MSTATUS_HS_VS, 18, 2)
565 /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */
566 FIELD(TB_FLAGS, XL, 20, 2)
567 /* If PointerMasking should be applied */
568 FIELD(TB_FLAGS, PM_MASK_ENABLED, 22, 1)
569 FIELD(TB_FLAGS, PM_BASE_ENABLED, 23, 1)
570 
571 #ifdef TARGET_RISCV32
572 #define riscv_cpu_mxl(env)  ((void)(env), MXL_RV32)
573 #else
574 static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env)
575 {
576     return env->misa_mxl;
577 }
578 #endif
579 #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env)))
580 
581 #if defined(TARGET_RISCV32)
582 #define cpu_recompute_xl(env)  ((void)(env), MXL_RV32)
583 #else
584 static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env)
585 {
586     RISCVMXL xl = env->misa_mxl;
587 #if !defined(CONFIG_USER_ONLY)
588     /*
589      * When emulating a 32-bit-only cpu, use RV32.
590      * When emulating a 64-bit cpu, and MXL has been reduced to RV32,
591      * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened
592      * back to RV64 for lower privs.
593      */
594     if (xl != MXL_RV32) {
595         switch (env->priv) {
596         case PRV_M:
597             break;
598         case PRV_U:
599             xl = get_field(env->mstatus, MSTATUS64_UXL);
600             break;
601         default: /* PRV_S | PRV_H */
602             xl = get_field(env->mstatus, MSTATUS64_SXL);
603             break;
604         }
605     }
606 #endif
607     return xl;
608 }
609 #endif
610 
611 static inline int riscv_cpu_xlen(CPURISCVState *env)
612 {
613     return 16 << env->xl;
614 }
615 
616 #ifdef TARGET_RISCV32
617 #define riscv_cpu_sxl(env)  ((void)(env), MXL_RV32)
618 #else
619 static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env)
620 {
621 #ifdef CONFIG_USER_ONLY
622     return env->misa_mxl;
623 #else
624     return get_field(env->mstatus, MSTATUS64_SXL);
625 #endif
626 }
627 #endif
628 
629 /*
630  * Encode LMUL to lmul as follows:
631  *     LMUL    vlmul    lmul
632  *      1       000       0
633  *      2       001       1
634  *      4       010       2
635  *      8       011       3
636  *      -       100       -
637  *     1/8      101      -3
638  *     1/4      110      -2
639  *     1/2      111      -1
640  *
641  * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul)
642  * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8
643  *      => VLMAX = vlen >> (1 + 3 - (-3))
644  *               = 256 >> 7
645  *               = 2
646  */
647 static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype)
648 {
649     uint8_t sew = FIELD_EX64(vtype, VTYPE, VSEW);
650     int8_t lmul = sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3);
651     return cpu->cfg.vlen >> (sew + 3 - lmul);
652 }
653 
654 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
655                           target_ulong *cs_base, uint32_t *pflags);
656 
657 void riscv_cpu_update_mask(CPURISCVState *env);
658 
659 RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
660                            target_ulong *ret_value,
661                            target_ulong new_value, target_ulong write_mask);
662 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno,
663                                  target_ulong *ret_value,
664                                  target_ulong new_value,
665                                  target_ulong write_mask);
666 
667 static inline void riscv_csr_write(CPURISCVState *env, int csrno,
668                                    target_ulong val)
669 {
670     riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS));
671 }
672 
673 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno)
674 {
675     target_ulong val = 0;
676     riscv_csrrw(env, csrno, &val, 0, 0);
677     return val;
678 }
679 
680 typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env,
681                                                  int csrno);
682 typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno,
683                                             target_ulong *ret_value);
684 typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno,
685                                              target_ulong new_value);
686 typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
687                                           target_ulong *ret_value,
688                                           target_ulong new_value,
689                                           target_ulong write_mask);
690 
691 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
692                                 Int128 *ret_value,
693                                 Int128 new_value, Int128 write_mask);
694 
695 typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno,
696                                                Int128 *ret_value);
697 typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int csrno,
698                                              Int128 new_value);
699 
700 typedef struct {
701     const char *name;
702     riscv_csr_predicate_fn predicate;
703     riscv_csr_read_fn read;
704     riscv_csr_write_fn write;
705     riscv_csr_op_fn op;
706     riscv_csr_read128_fn read128;
707     riscv_csr_write128_fn write128;
708     /* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0) */
709     uint32_t min_priv_ver;
710 } riscv_csr_operations;
711 
712 /* CSR function table constants */
713 enum {
714     CSR_TABLE_SIZE = 0x1000
715 };
716 
717 /* CSR function table */
718 extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE];
719 
720 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops);
721 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
722 
723 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
724 
725 #endif /* RISCV_CPU_H */
726