1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef RISCV_CPU_H 21 #define RISCV_CPU_H 22 23 #include "hw/core/cpu.h" 24 #include "hw/registerfields.h" 25 #include "exec/cpu-defs.h" 26 #include "qemu/cpu-float.h" 27 #include "qom/object.h" 28 #include "qemu/int128.h" 29 #include "cpu_bits.h" 30 31 #define TCG_GUEST_DEFAULT_MO 0 32 33 /* 34 * RISC-V-specific extra insn start words: 35 * 1: Original instruction opcode 36 */ 37 #define TARGET_INSN_START_EXTRA_WORDS 1 38 39 #define TYPE_RISCV_CPU "riscv-cpu" 40 41 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU 42 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) 43 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU 44 45 #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") 46 #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") 47 #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") 48 #define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128") 49 #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") 50 #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") 51 #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") 52 #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") 53 #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") 54 #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") 55 #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") 56 #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") 57 58 #if defined(TARGET_RISCV32) 59 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 60 #elif defined(TARGET_RISCV64) 61 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 62 #endif 63 64 #define RV(x) ((target_ulong)1 << (x - 'A')) 65 66 #define RVI RV('I') 67 #define RVE RV('E') /* E and I are mutually exclusive */ 68 #define RVM RV('M') 69 #define RVA RV('A') 70 #define RVF RV('F') 71 #define RVD RV('D') 72 #define RVV RV('V') 73 #define RVC RV('C') 74 #define RVS RV('S') 75 #define RVU RV('U') 76 #define RVH RV('H') 77 #define RVJ RV('J') 78 79 /* S extension denotes that Supervisor mode exists, however it is possible 80 to have a core that support S mode but does not have an MMU and there 81 is currently no bit in misa to indicate whether an MMU exists or not 82 so a cpu features bitfield is required, likewise for optional PMP support */ 83 enum { 84 RISCV_FEATURE_MMU, 85 RISCV_FEATURE_PMP, 86 RISCV_FEATURE_EPMP, 87 RISCV_FEATURE_MISA, 88 RISCV_FEATURE_AIA, 89 RISCV_FEATURE_DEBUG 90 }; 91 92 /* Privileged specification version */ 93 enum { 94 PRIV_VERSION_1_10_0 = 0, 95 PRIV_VERSION_1_11_0, 96 PRIV_VERSION_1_12_0, 97 }; 98 99 #define VEXT_VERSION_1_00_0 0x00010000 100 101 enum { 102 TRANSLATE_SUCCESS, 103 TRANSLATE_FAIL, 104 TRANSLATE_PMP_FAIL, 105 TRANSLATE_G_STAGE_FAIL 106 }; 107 108 #define MMU_USER_IDX 3 109 110 #define MAX_RISCV_PMPS (16) 111 112 typedef struct CPUArchState CPURISCVState; 113 114 #if !defined(CONFIG_USER_ONLY) 115 #include "pmp.h" 116 #include "debug.h" 117 #endif 118 119 #define RV_VLEN_MAX 1024 120 #define RV_MAX_MHPMEVENTS 32 121 #define RV_MAX_MHPMCOUNTERS 32 122 123 FIELD(VTYPE, VLMUL, 0, 3) 124 FIELD(VTYPE, VSEW, 3, 3) 125 FIELD(VTYPE, VTA, 6, 1) 126 FIELD(VTYPE, VMA, 7, 1) 127 FIELD(VTYPE, VEDIV, 8, 2) 128 FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) 129 130 typedef struct PMUCTRState { 131 /* Current value of a counter */ 132 target_ulong mhpmcounter_val; 133 /* Current value of a counter in RV32*/ 134 target_ulong mhpmcounterh_val; 135 /* Snapshot values of counter */ 136 target_ulong mhpmcounter_prev; 137 /* Snapshort value of a counter in RV32 */ 138 target_ulong mhpmcounterh_prev; 139 bool started; 140 } PMUCTRState; 141 142 struct CPUArchState { 143 target_ulong gpr[32]; 144 target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ 145 uint64_t fpr[32]; /* assume both F and D extensions */ 146 147 /* vector coprocessor state. */ 148 uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); 149 target_ulong vxrm; 150 target_ulong vxsat; 151 target_ulong vl; 152 target_ulong vstart; 153 target_ulong vtype; 154 bool vill; 155 156 target_ulong pc; 157 target_ulong load_res; 158 target_ulong load_val; 159 160 target_ulong frm; 161 162 target_ulong badaddr; 163 target_ulong bins; 164 165 target_ulong guest_phys_fault_addr; 166 167 target_ulong priv_ver; 168 target_ulong bext_ver; 169 target_ulong vext_ver; 170 171 /* RISCVMXL, but uint32_t for vmstate migration */ 172 uint32_t misa_mxl; /* current mxl */ 173 uint32_t misa_mxl_max; /* max mxl for this cpu */ 174 uint32_t misa_ext; /* current extensions */ 175 uint32_t misa_ext_mask; /* max ext for this cpu */ 176 uint32_t xl; /* current xlen */ 177 178 /* 128-bit helpers upper part return value */ 179 target_ulong retxh; 180 181 uint32_t features; 182 183 #ifdef CONFIG_USER_ONLY 184 uint32_t elf_flags; 185 #endif 186 187 #ifndef CONFIG_USER_ONLY 188 target_ulong priv; 189 /* This contains QEMU specific information about the virt state. */ 190 target_ulong virt; 191 target_ulong geilen; 192 target_ulong resetvec; 193 194 target_ulong mhartid; 195 /* 196 * For RV32 this is 32-bit mstatus and 32-bit mstatush. 197 * For RV64 this is a 64-bit mstatus. 198 */ 199 uint64_t mstatus; 200 201 uint64_t mip; 202 /* 203 * MIP contains the software writable version of SEIP ORed with the 204 * external interrupt value. The MIP register is always up-to-date. 205 * To keep track of the current source, we also save booleans of the values 206 * here. 207 */ 208 bool external_seip; 209 bool software_seip; 210 211 uint64_t miclaim; 212 213 uint64_t mie; 214 uint64_t mideleg; 215 216 target_ulong satp; /* since: priv-1.10.0 */ 217 target_ulong stval; 218 target_ulong medeleg; 219 220 target_ulong stvec; 221 target_ulong sepc; 222 target_ulong scause; 223 224 target_ulong mtvec; 225 target_ulong mepc; 226 target_ulong mcause; 227 target_ulong mtval; /* since: priv-1.10.0 */ 228 229 /* Machine and Supervisor interrupt priorities */ 230 uint8_t miprio[64]; 231 uint8_t siprio[64]; 232 233 /* AIA CSRs */ 234 target_ulong miselect; 235 target_ulong siselect; 236 237 /* Hypervisor CSRs */ 238 target_ulong hstatus; 239 target_ulong hedeleg; 240 uint64_t hideleg; 241 target_ulong hcounteren; 242 target_ulong htval; 243 target_ulong htinst; 244 target_ulong hgatp; 245 target_ulong hgeie; 246 target_ulong hgeip; 247 uint64_t htimedelta; 248 249 /* Hypervisor controlled virtual interrupt priorities */ 250 target_ulong hvictl; 251 uint8_t hviprio[64]; 252 253 /* Upper 64-bits of 128-bit CSRs */ 254 uint64_t mscratchh; 255 uint64_t sscratchh; 256 257 /* Virtual CSRs */ 258 /* 259 * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. 260 * For RV64 this is a 64-bit vsstatus. 261 */ 262 uint64_t vsstatus; 263 target_ulong vstvec; 264 target_ulong vsscratch; 265 target_ulong vsepc; 266 target_ulong vscause; 267 target_ulong vstval; 268 target_ulong vsatp; 269 270 /* AIA VS-mode CSRs */ 271 target_ulong vsiselect; 272 273 target_ulong mtval2; 274 target_ulong mtinst; 275 276 /* HS Backup CSRs */ 277 target_ulong stvec_hs; 278 target_ulong sscratch_hs; 279 target_ulong sepc_hs; 280 target_ulong scause_hs; 281 target_ulong stval_hs; 282 target_ulong satp_hs; 283 uint64_t mstatus_hs; 284 285 /* Signals whether the current exception occurred with two-stage address 286 translation active. */ 287 bool two_stage_lookup; 288 /* 289 * Signals whether the current exception occurred while doing two-stage 290 * address translation for the VS-stage page table walk. 291 */ 292 bool two_stage_indirect_lookup; 293 294 target_ulong scounteren; 295 target_ulong mcounteren; 296 297 target_ulong mcountinhibit; 298 299 /* PMU counter state */ 300 PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS]; 301 302 /* PMU event selector configured values. First three are unused*/ 303 target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS]; 304 305 target_ulong sscratch; 306 target_ulong mscratch; 307 308 /* temporary htif regs */ 309 uint64_t mfromhost; 310 uint64_t mtohost; 311 uint64_t timecmp; 312 313 /* physical memory protection */ 314 pmp_table_t pmp_state; 315 target_ulong mseccfg; 316 317 /* trigger module */ 318 target_ulong trigger_cur; 319 type2_trigger_t type2_trig[TRIGGER_TYPE2_NUM]; 320 321 /* machine specific rdtime callback */ 322 uint64_t (*rdtime_fn)(void *); 323 void *rdtime_fn_arg; 324 325 /* machine specific AIA ireg read-modify-write callback */ 326 #define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \ 327 ((((__xlen) & 0xff) << 24) | \ 328 (((__vgein) & 0x3f) << 20) | \ 329 (((__virt) & 0x1) << 18) | \ 330 (((__priv) & 0x3) << 16) | \ 331 (__isel & 0xffff)) 332 #define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff) 333 #define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3) 334 #define AIA_IREG_VIRT(__ireg) (((__ireg) >> 18) & 0x1) 335 #define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 20) & 0x3f) 336 #define AIA_IREG_XLEN(__ireg) (((__ireg) >> 24) & 0xff) 337 int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg, 338 target_ulong *val, target_ulong new_val, target_ulong write_mask); 339 void *aia_ireg_rmw_fn_arg[4]; 340 341 /* True if in debugger mode. */ 342 bool debugger; 343 344 /* 345 * CSRs for PointerMasking extension 346 */ 347 target_ulong mmte; 348 target_ulong mpmmask; 349 target_ulong mpmbase; 350 target_ulong spmmask; 351 target_ulong spmbase; 352 target_ulong upmmask; 353 target_ulong upmbase; 354 355 /* CSRs for execution enviornment configuration */ 356 uint64_t menvcfg; 357 target_ulong senvcfg; 358 uint64_t henvcfg; 359 #endif 360 target_ulong cur_pmmask; 361 target_ulong cur_pmbase; 362 363 float_status fp_status; 364 365 /* Fields from here on are preserved across CPU reset. */ 366 QEMUTimer *timer; /* Internal timer */ 367 368 hwaddr kernel_addr; 369 hwaddr fdt_addr; 370 371 /* kvm timer */ 372 bool kvm_timer_dirty; 373 uint64_t kvm_timer_time; 374 uint64_t kvm_timer_compare; 375 uint64_t kvm_timer_state; 376 uint64_t kvm_timer_frequency; 377 }; 378 379 OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) 380 381 /** 382 * RISCVCPUClass: 383 * @parent_realize: The parent class' realize handler. 384 * @parent_reset: The parent class' reset handler. 385 * 386 * A RISCV CPU model. 387 */ 388 struct RISCVCPUClass { 389 /*< private >*/ 390 CPUClass parent_class; 391 /*< public >*/ 392 DeviceRealize parent_realize; 393 DeviceReset parent_reset; 394 }; 395 396 struct RISCVCPUConfig { 397 bool ext_i; 398 bool ext_e; 399 bool ext_g; 400 bool ext_m; 401 bool ext_a; 402 bool ext_f; 403 bool ext_d; 404 bool ext_c; 405 bool ext_s; 406 bool ext_u; 407 bool ext_h; 408 bool ext_j; 409 bool ext_v; 410 bool ext_zba; 411 bool ext_zbb; 412 bool ext_zbc; 413 bool ext_zbkb; 414 bool ext_zbkc; 415 bool ext_zbkx; 416 bool ext_zbs; 417 bool ext_zk; 418 bool ext_zkn; 419 bool ext_zknd; 420 bool ext_zkne; 421 bool ext_zknh; 422 bool ext_zkr; 423 bool ext_zks; 424 bool ext_zksed; 425 bool ext_zksh; 426 bool ext_zkt; 427 bool ext_ifencei; 428 bool ext_icsr; 429 bool ext_svinval; 430 bool ext_svnapot; 431 bool ext_svpbmt; 432 bool ext_zdinx; 433 bool ext_zfh; 434 bool ext_zfhmin; 435 bool ext_zfinx; 436 bool ext_zhinx; 437 bool ext_zhinxmin; 438 bool ext_zve32f; 439 bool ext_zve64f; 440 bool ext_zmmul; 441 bool rvv_ta_all_1s; 442 443 uint32_t mvendorid; 444 uint64_t marchid; 445 uint64_t mimpid; 446 447 /* Vendor-specific custom extensions */ 448 bool ext_XVentanaCondOps; 449 450 uint8_t pmu_num; 451 char *priv_spec; 452 char *user_spec; 453 char *bext_spec; 454 char *vext_spec; 455 uint16_t vlen; 456 uint16_t elen; 457 bool mmu; 458 bool pmp; 459 bool epmp; 460 bool aia; 461 bool debug; 462 uint64_t resetvec; 463 464 bool short_isa_string; 465 }; 466 467 typedef struct RISCVCPUConfig RISCVCPUConfig; 468 469 /** 470 * RISCVCPU: 471 * @env: #CPURISCVState 472 * 473 * A RISCV CPU. 474 */ 475 struct ArchCPU { 476 /*< private >*/ 477 CPUState parent_obj; 478 /*< public >*/ 479 CPUNegativeOffsetState neg; 480 CPURISCVState env; 481 482 char *dyn_csr_xml; 483 char *dyn_vreg_xml; 484 485 /* Configuration Settings */ 486 RISCVCPUConfig cfg; 487 }; 488 489 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) 490 { 491 return (env->misa_ext & ext) != 0; 492 } 493 494 static inline bool riscv_feature(CPURISCVState *env, int feature) 495 { 496 return env->features & (1ULL << feature); 497 } 498 499 static inline void riscv_set_feature(CPURISCVState *env, int feature) 500 { 501 env->features |= (1ULL << feature); 502 } 503 504 #include "cpu_user.h" 505 506 extern const char * const riscv_int_regnames[]; 507 extern const char * const riscv_int_regnamesh[]; 508 extern const char * const riscv_fpr_regnames[]; 509 510 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); 511 void riscv_cpu_do_interrupt(CPUState *cpu); 512 int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 513 int cpuid, void *opaque); 514 int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 515 int cpuid, void *opaque); 516 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 517 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 518 int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero); 519 uint8_t riscv_cpu_default_priority(int irq); 520 uint64_t riscv_cpu_all_pending(CPURISCVState *env); 521 int riscv_cpu_mirq_pending(CPURISCVState *env); 522 int riscv_cpu_sirq_pending(CPURISCVState *env); 523 int riscv_cpu_vsirq_pending(CPURISCVState *env); 524 bool riscv_cpu_fp_enabled(CPURISCVState *env); 525 target_ulong riscv_cpu_get_geilen(CPURISCVState *env); 526 void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); 527 bool riscv_cpu_vector_enabled(CPURISCVState *env); 528 bool riscv_cpu_virt_enabled(CPURISCVState *env); 529 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); 530 bool riscv_cpu_two_stage_lookup(int mmu_idx); 531 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); 532 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 533 G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 534 MMUAccessType access_type, int mmu_idx, 535 uintptr_t retaddr); 536 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 537 MMUAccessType access_type, int mmu_idx, 538 bool probe, uintptr_t retaddr); 539 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 540 vaddr addr, unsigned size, 541 MMUAccessType access_type, 542 int mmu_idx, MemTxAttrs attrs, 543 MemTxResult response, uintptr_t retaddr); 544 char *riscv_isa_string(RISCVCPU *cpu); 545 void riscv_cpu_list(void); 546 547 #define cpu_list riscv_cpu_list 548 #define cpu_mmu_index riscv_cpu_mmu_index 549 550 #ifndef CONFIG_USER_ONLY 551 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); 552 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); 553 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); 554 uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value); 555 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ 556 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), 557 void *arg); 558 void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, 559 int (*rmw_fn)(void *arg, 560 target_ulong reg, 561 target_ulong *val, 562 target_ulong new_val, 563 target_ulong write_mask), 564 void *rmw_fn_arg); 565 #endif 566 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); 567 568 void riscv_translate_init(void); 569 G_NORETURN void riscv_raise_exception(CPURISCVState *env, 570 uint32_t exception, uintptr_t pc); 571 572 target_ulong riscv_cpu_get_fflags(CPURISCVState *env); 573 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); 574 575 #define TB_FLAGS_PRIV_MMU_MASK 3 576 #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2) 577 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS 578 #define TB_FLAGS_MSTATUS_VS MSTATUS_VS 579 580 #include "exec/cpu-all.h" 581 582 FIELD(TB_FLAGS, MEM_IDX, 0, 3) 583 FIELD(TB_FLAGS, LMUL, 3, 3) 584 FIELD(TB_FLAGS, SEW, 6, 3) 585 /* Skip MSTATUS_VS (0x600) bits */ 586 FIELD(TB_FLAGS, VL_EQ_VLMAX, 11, 1) 587 FIELD(TB_FLAGS, VILL, 12, 1) 588 /* Skip MSTATUS_FS (0x6000) bits */ 589 /* Is a Hypervisor instruction load/store allowed? */ 590 FIELD(TB_FLAGS, HLSX, 15, 1) 591 FIELD(TB_FLAGS, MSTATUS_HS_FS, 16, 2) 592 FIELD(TB_FLAGS, MSTATUS_HS_VS, 18, 2) 593 /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ 594 FIELD(TB_FLAGS, XL, 20, 2) 595 /* If PointerMasking should be applied */ 596 FIELD(TB_FLAGS, PM_MASK_ENABLED, 22, 1) 597 FIELD(TB_FLAGS, PM_BASE_ENABLED, 23, 1) 598 FIELD(TB_FLAGS, VTA, 24, 1) 599 600 #ifdef TARGET_RISCV32 601 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) 602 #else 603 static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) 604 { 605 return env->misa_mxl; 606 } 607 #endif 608 #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env))) 609 610 #if defined(TARGET_RISCV32) 611 #define cpu_recompute_xl(env) ((void)(env), MXL_RV32) 612 #else 613 static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) 614 { 615 RISCVMXL xl = env->misa_mxl; 616 #if !defined(CONFIG_USER_ONLY) 617 /* 618 * When emulating a 32-bit-only cpu, use RV32. 619 * When emulating a 64-bit cpu, and MXL has been reduced to RV32, 620 * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened 621 * back to RV64 for lower privs. 622 */ 623 if (xl != MXL_RV32) { 624 switch (env->priv) { 625 case PRV_M: 626 break; 627 case PRV_U: 628 xl = get_field(env->mstatus, MSTATUS64_UXL); 629 break; 630 default: /* PRV_S | PRV_H */ 631 xl = get_field(env->mstatus, MSTATUS64_SXL); 632 break; 633 } 634 } 635 #endif 636 return xl; 637 } 638 #endif 639 640 static inline int riscv_cpu_xlen(CPURISCVState *env) 641 { 642 return 16 << env->xl; 643 } 644 645 #ifdef TARGET_RISCV32 646 #define riscv_cpu_sxl(env) ((void)(env), MXL_RV32) 647 #else 648 static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env) 649 { 650 #ifdef CONFIG_USER_ONLY 651 return env->misa_mxl; 652 #else 653 return get_field(env->mstatus, MSTATUS64_SXL); 654 #endif 655 } 656 #endif 657 658 /* 659 * Encode LMUL to lmul as follows: 660 * LMUL vlmul lmul 661 * 1 000 0 662 * 2 001 1 663 * 4 010 2 664 * 8 011 3 665 * - 100 - 666 * 1/8 101 -3 667 * 1/4 110 -2 668 * 1/2 111 -1 669 * 670 * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul) 671 * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8 672 * => VLMAX = vlen >> (1 + 3 - (-3)) 673 * = 256 >> 7 674 * = 2 675 */ 676 static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) 677 { 678 uint8_t sew = FIELD_EX64(vtype, VTYPE, VSEW); 679 int8_t lmul = sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3); 680 return cpu->cfg.vlen >> (sew + 3 - lmul); 681 } 682 683 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 684 target_ulong *cs_base, uint32_t *pflags); 685 686 void riscv_cpu_update_mask(CPURISCVState *env); 687 688 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, 689 target_ulong *ret_value, 690 target_ulong new_value, target_ulong write_mask); 691 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, 692 target_ulong *ret_value, 693 target_ulong new_value, 694 target_ulong write_mask); 695 696 static inline void riscv_csr_write(CPURISCVState *env, int csrno, 697 target_ulong val) 698 { 699 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); 700 } 701 702 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) 703 { 704 target_ulong val = 0; 705 riscv_csrrw(env, csrno, &val, 0, 0); 706 return val; 707 } 708 709 typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, 710 int csrno); 711 typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, 712 target_ulong *ret_value); 713 typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, 714 target_ulong new_value); 715 typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, 716 target_ulong *ret_value, 717 target_ulong new_value, 718 target_ulong write_mask); 719 720 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, 721 Int128 *ret_value, 722 Int128 new_value, Int128 write_mask); 723 724 typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno, 725 Int128 *ret_value); 726 typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int csrno, 727 Int128 new_value); 728 729 typedef struct { 730 const char *name; 731 riscv_csr_predicate_fn predicate; 732 riscv_csr_read_fn read; 733 riscv_csr_write_fn write; 734 riscv_csr_op_fn op; 735 riscv_csr_read128_fn read128; 736 riscv_csr_write128_fn write128; 737 /* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0) */ 738 uint32_t min_priv_ver; 739 } riscv_csr_operations; 740 741 /* CSR function table constants */ 742 enum { 743 CSR_TABLE_SIZE = 0x1000 744 }; 745 746 /* CSR function table */ 747 extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; 748 749 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); 750 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); 751 752 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); 753 754 #endif /* RISCV_CPU_H */ 755