1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef RISCV_CPU_H 21 #define RISCV_CPU_H 22 23 #include "hw/core/cpu.h" 24 #include "hw/registerfields.h" 25 #include "exec/cpu-defs.h" 26 #include "fpu/softfloat-types.h" 27 #include "qom/object.h" 28 29 #define TCG_GUEST_DEFAULT_MO 0 30 31 #define TYPE_RISCV_CPU "riscv-cpu" 32 33 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU 34 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) 35 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU 36 37 #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") 38 #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") 39 #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") 40 #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") 41 #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") 42 #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") 43 #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") 44 #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") 45 #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") 46 47 #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2)) 48 #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2)) 49 50 #if defined(TARGET_RISCV32) 51 #define RVXLEN RV32 52 #elif defined(TARGET_RISCV64) 53 #define RVXLEN RV64 54 #endif 55 56 #define RV(x) ((target_ulong)1 << (x - 'A')) 57 58 #define RVI RV('I') 59 #define RVE RV('E') /* E and I are mutually exclusive */ 60 #define RVM RV('M') 61 #define RVA RV('A') 62 #define RVF RV('F') 63 #define RVD RV('D') 64 #define RVV RV('V') 65 #define RVC RV('C') 66 #define RVS RV('S') 67 #define RVU RV('U') 68 #define RVH RV('H') 69 70 /* S extension denotes that Supervisor mode exists, however it is possible 71 to have a core that support S mode but does not have an MMU and there 72 is currently no bit in misa to indicate whether an MMU exists or not 73 so a cpu features bitfield is required, likewise for optional PMP support */ 74 enum { 75 RISCV_FEATURE_MMU, 76 RISCV_FEATURE_PMP, 77 RISCV_FEATURE_MISA 78 }; 79 80 #define PRIV_VERSION_1_10_0 0x00011000 81 #define PRIV_VERSION_1_11_0 0x00011100 82 83 #define VEXT_VERSION_0_07_1 0x00000701 84 85 #define TRANSLATE_PMP_FAIL 2 86 #define TRANSLATE_FAIL 1 87 #define TRANSLATE_SUCCESS 0 88 #define MMU_USER_IDX 3 89 90 #define MAX_RISCV_PMPS (16) 91 92 typedef struct CPURISCVState CPURISCVState; 93 94 #include "pmp.h" 95 96 #define RV_VLEN_MAX 256 97 98 FIELD(VTYPE, VLMUL, 0, 2) 99 FIELD(VTYPE, VSEW, 2, 3) 100 FIELD(VTYPE, VEDIV, 5, 2) 101 FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 9) 102 FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1) 103 104 struct CPURISCVState { 105 target_ulong gpr[32]; 106 uint64_t fpr[32]; /* assume both F and D extensions */ 107 108 /* vector coprocessor state. */ 109 uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); 110 target_ulong vxrm; 111 target_ulong vxsat; 112 target_ulong vl; 113 target_ulong vstart; 114 target_ulong vtype; 115 116 target_ulong pc; 117 target_ulong load_res; 118 target_ulong load_val; 119 120 target_ulong frm; 121 122 target_ulong badaddr; 123 target_ulong guest_phys_fault_addr; 124 125 target_ulong priv_ver; 126 target_ulong vext_ver; 127 target_ulong misa; 128 target_ulong misa_mask; 129 130 uint32_t features; 131 132 #ifdef CONFIG_USER_ONLY 133 uint32_t elf_flags; 134 #endif 135 136 #ifndef CONFIG_USER_ONLY 137 target_ulong priv; 138 /* This contains QEMU specific information about the virt state. */ 139 target_ulong virt; 140 target_ulong resetvec; 141 142 target_ulong mhartid; 143 target_ulong mstatus; 144 145 target_ulong mip; 146 147 #ifdef TARGET_RISCV32 148 target_ulong mstatush; 149 #endif 150 151 uint32_t miclaim; 152 153 target_ulong mie; 154 target_ulong mideleg; 155 156 target_ulong sptbr; /* until: priv-1.9.1 */ 157 target_ulong satp; /* since: priv-1.10.0 */ 158 target_ulong sbadaddr; 159 target_ulong mbadaddr; 160 target_ulong medeleg; 161 162 target_ulong stvec; 163 target_ulong sepc; 164 target_ulong scause; 165 166 target_ulong mtvec; 167 target_ulong mepc; 168 target_ulong mcause; 169 target_ulong mtval; /* since: priv-1.10.0 */ 170 171 /* Hypervisor CSRs */ 172 target_ulong hstatus; 173 target_ulong hedeleg; 174 target_ulong hideleg; 175 target_ulong hcounteren; 176 target_ulong htval; 177 target_ulong htinst; 178 target_ulong hgatp; 179 uint64_t htimedelta; 180 181 /* Virtual CSRs */ 182 target_ulong vsstatus; 183 target_ulong vstvec; 184 target_ulong vsscratch; 185 target_ulong vsepc; 186 target_ulong vscause; 187 target_ulong vstval; 188 target_ulong vsatp; 189 #ifdef TARGET_RISCV32 190 target_ulong vsstatush; 191 #endif 192 193 target_ulong mtval2; 194 target_ulong mtinst; 195 196 /* HS Backup CSRs */ 197 target_ulong stvec_hs; 198 target_ulong sscratch_hs; 199 target_ulong sepc_hs; 200 target_ulong scause_hs; 201 target_ulong stval_hs; 202 target_ulong satp_hs; 203 target_ulong mstatus_hs; 204 #ifdef TARGET_RISCV32 205 target_ulong mstatush_hs; 206 #endif 207 208 target_ulong scounteren; 209 target_ulong mcounteren; 210 211 target_ulong sscratch; 212 target_ulong mscratch; 213 214 /* temporary htif regs */ 215 uint64_t mfromhost; 216 uint64_t mtohost; 217 uint64_t timecmp; 218 219 /* physical memory protection */ 220 pmp_table_t pmp_state; 221 222 /* machine specific rdtime callback */ 223 uint64_t (*rdtime_fn)(uint32_t); 224 uint32_t rdtime_fn_arg; 225 226 /* True if in debugger mode. */ 227 bool debugger; 228 #endif 229 230 float_status fp_status; 231 232 /* Fields from here on are preserved across CPU reset. */ 233 QEMUTimer *timer; /* Internal timer */ 234 }; 235 236 OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass, 237 RISCV_CPU) 238 239 /** 240 * RISCVCPUClass: 241 * @parent_realize: The parent class' realize handler. 242 * @parent_reset: The parent class' reset handler. 243 * 244 * A RISCV CPU model. 245 */ 246 struct RISCVCPUClass { 247 /*< private >*/ 248 CPUClass parent_class; 249 /*< public >*/ 250 DeviceRealize parent_realize; 251 DeviceReset parent_reset; 252 }; 253 254 /** 255 * RISCVCPU: 256 * @env: #CPURISCVState 257 * 258 * A RISCV CPU. 259 */ 260 struct RISCVCPU { 261 /*< private >*/ 262 CPUState parent_obj; 263 /*< public >*/ 264 CPUNegativeOffsetState neg; 265 CPURISCVState env; 266 267 /* Configuration Settings */ 268 struct { 269 bool ext_i; 270 bool ext_e; 271 bool ext_g; 272 bool ext_m; 273 bool ext_a; 274 bool ext_f; 275 bool ext_d; 276 bool ext_c; 277 bool ext_s; 278 bool ext_u; 279 bool ext_h; 280 bool ext_v; 281 bool ext_counters; 282 bool ext_ifencei; 283 bool ext_icsr; 284 285 char *priv_spec; 286 char *user_spec; 287 char *vext_spec; 288 uint16_t vlen; 289 uint16_t elen; 290 bool mmu; 291 bool pmp; 292 uint64_t resetvec; 293 } cfg; 294 }; 295 296 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) 297 { 298 return (env->misa & ext) != 0; 299 } 300 301 static inline bool riscv_feature(CPURISCVState *env, int feature) 302 { 303 return env->features & (1ULL << feature); 304 } 305 306 #include "cpu_user.h" 307 #include "cpu_bits.h" 308 309 extern const char * const riscv_int_regnames[]; 310 extern const char * const riscv_fpr_regnames[]; 311 extern const char * const riscv_excp_names[]; 312 extern const char * const riscv_intr_names[]; 313 314 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); 315 void riscv_cpu_do_interrupt(CPUState *cpu); 316 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 317 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 318 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); 319 bool riscv_cpu_fp_enabled(CPURISCVState *env); 320 bool riscv_cpu_virt_enabled(CPURISCVState *env); 321 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); 322 bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env); 323 void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable); 324 bool riscv_cpu_two_stage_lookup(CPURISCVState *env); 325 void riscv_cpu_set_two_stage_lookup(CPURISCVState *env, bool enable); 326 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); 327 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 328 void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 329 MMUAccessType access_type, int mmu_idx, 330 uintptr_t retaddr); 331 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 332 MMUAccessType access_type, int mmu_idx, 333 bool probe, uintptr_t retaddr); 334 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 335 vaddr addr, unsigned size, 336 MMUAccessType access_type, 337 int mmu_idx, MemTxAttrs attrs, 338 MemTxResult response, uintptr_t retaddr); 339 char *riscv_isa_string(RISCVCPU *cpu); 340 void riscv_cpu_list(void); 341 342 #define cpu_signal_handler riscv_cpu_signal_handler 343 #define cpu_list riscv_cpu_list 344 #define cpu_mmu_index riscv_cpu_mmu_index 345 346 #ifndef CONFIG_USER_ONLY 347 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); 348 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts); 349 uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value); 350 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ 351 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t), 352 uint32_t arg); 353 #endif 354 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); 355 356 void riscv_translate_init(void); 357 int riscv_cpu_signal_handler(int host_signum, void *pinfo, void *puc); 358 void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env, 359 uint32_t exception, uintptr_t pc); 360 361 target_ulong riscv_cpu_get_fflags(CPURISCVState *env); 362 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); 363 364 #define TB_FLAGS_MMU_MASK 3 365 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS 366 367 typedef CPURISCVState CPUArchState; 368 typedef RISCVCPU ArchCPU; 369 #include "exec/cpu-all.h" 370 371 FIELD(TB_FLAGS, VL_EQ_VLMAX, 2, 1) 372 FIELD(TB_FLAGS, LMUL, 3, 2) 373 FIELD(TB_FLAGS, SEW, 5, 3) 374 FIELD(TB_FLAGS, VILL, 8, 1) 375 376 /* 377 * A simplification for VLMAX 378 * = (1 << LMUL) * VLEN / (8 * (1 << SEW)) 379 * = (VLEN << LMUL) / (8 << SEW) 380 * = (VLEN << LMUL) >> (SEW + 3) 381 * = VLEN >> (SEW + 3 - LMUL) 382 */ 383 static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) 384 { 385 uint8_t sew, lmul; 386 387 sew = FIELD_EX64(vtype, VTYPE, VSEW); 388 lmul = FIELD_EX64(vtype, VTYPE, VLMUL); 389 return cpu->cfg.vlen >> (sew + 3 - lmul); 390 } 391 392 static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 393 target_ulong *cs_base, uint32_t *pflags) 394 { 395 uint32_t flags = 0; 396 397 *pc = env->pc; 398 *cs_base = 0; 399 400 if (riscv_has_ext(env, RVV)) { 401 uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype); 402 bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl); 403 flags = FIELD_DP32(flags, TB_FLAGS, VILL, 404 FIELD_EX64(env->vtype, VTYPE, VILL)); 405 flags = FIELD_DP32(flags, TB_FLAGS, SEW, 406 FIELD_EX64(env->vtype, VTYPE, VSEW)); 407 flags = FIELD_DP32(flags, TB_FLAGS, LMUL, 408 FIELD_EX64(env->vtype, VTYPE, VLMUL)); 409 flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); 410 } else { 411 flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1); 412 } 413 414 #ifdef CONFIG_USER_ONLY 415 flags |= TB_FLAGS_MSTATUS_FS; 416 #else 417 flags |= cpu_mmu_index(env, 0); 418 if (riscv_cpu_fp_enabled(env)) { 419 flags |= env->mstatus & MSTATUS_FS; 420 } 421 #endif 422 *pflags = flags; 423 } 424 425 int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, 426 target_ulong new_value, target_ulong write_mask); 427 int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value, 428 target_ulong new_value, target_ulong write_mask); 429 430 static inline void riscv_csr_write(CPURISCVState *env, int csrno, 431 target_ulong val) 432 { 433 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); 434 } 435 436 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) 437 { 438 target_ulong val = 0; 439 riscv_csrrw(env, csrno, &val, 0, 0); 440 return val; 441 } 442 443 typedef int (*riscv_csr_predicate_fn)(CPURISCVState *env, int csrno); 444 typedef int (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, 445 target_ulong *ret_value); 446 typedef int (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, 447 target_ulong new_value); 448 typedef int (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, 449 target_ulong *ret_value, target_ulong new_value, target_ulong write_mask); 450 451 typedef struct { 452 riscv_csr_predicate_fn predicate; 453 riscv_csr_read_fn read; 454 riscv_csr_write_fn write; 455 riscv_csr_op_fn op; 456 } riscv_csr_operations; 457 458 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); 459 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); 460 461 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); 462 463 #endif /* RISCV_CPU_H */ 464