1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef RISCV_CPU_H 21 #define RISCV_CPU_H 22 23 #include "hw/core/cpu.h" 24 #include "hw/registerfields.h" 25 #include "exec/cpu-defs.h" 26 #include "qemu/cpu-float.h" 27 #include "qom/object.h" 28 #include "qemu/int128.h" 29 #include "cpu_bits.h" 30 31 #define TCG_GUEST_DEFAULT_MO 0 32 33 /* 34 * RISC-V-specific extra insn start words: 35 * 1: Original instruction opcode 36 */ 37 #define TARGET_INSN_START_EXTRA_WORDS 1 38 39 #define TYPE_RISCV_CPU "riscv-cpu" 40 41 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU 42 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) 43 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU 44 45 #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") 46 #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") 47 #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") 48 #define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128") 49 #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") 50 #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") 51 #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") 52 #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") 53 #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") 54 #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") 55 #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") 56 #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") 57 58 #if defined(TARGET_RISCV32) 59 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 60 #elif defined(TARGET_RISCV64) 61 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 62 #endif 63 64 #define RV(x) ((target_ulong)1 << (x - 'A')) 65 66 #define RVI RV('I') 67 #define RVE RV('E') /* E and I are mutually exclusive */ 68 #define RVM RV('M') 69 #define RVA RV('A') 70 #define RVF RV('F') 71 #define RVD RV('D') 72 #define RVV RV('V') 73 #define RVC RV('C') 74 #define RVS RV('S') 75 #define RVU RV('U') 76 #define RVH RV('H') 77 #define RVJ RV('J') 78 79 /* S extension denotes that Supervisor mode exists, however it is possible 80 to have a core that support S mode but does not have an MMU and there 81 is currently no bit in misa to indicate whether an MMU exists or not 82 so a cpu features bitfield is required, likewise for optional PMP support */ 83 enum { 84 RISCV_FEATURE_MMU, 85 RISCV_FEATURE_PMP, 86 RISCV_FEATURE_EPMP, 87 RISCV_FEATURE_MISA, 88 RISCV_FEATURE_DEBUG 89 }; 90 91 /* Privileged specification version */ 92 enum { 93 PRIV_VERSION_1_10_0 = 0, 94 PRIV_VERSION_1_11_0, 95 PRIV_VERSION_1_12_0, 96 }; 97 98 #define VEXT_VERSION_1_00_0 0x00010000 99 100 enum { 101 TRANSLATE_SUCCESS, 102 TRANSLATE_FAIL, 103 TRANSLATE_PMP_FAIL, 104 TRANSLATE_G_STAGE_FAIL 105 }; 106 107 #define MMU_USER_IDX 3 108 109 #define MAX_RISCV_PMPS (16) 110 111 typedef struct CPUArchState CPURISCVState; 112 113 #if !defined(CONFIG_USER_ONLY) 114 #include "pmp.h" 115 #include "debug.h" 116 #endif 117 118 #define RV_VLEN_MAX 1024 119 #define RV_MAX_MHPMEVENTS 32 120 #define RV_MAX_MHPMCOUNTERS 32 121 122 FIELD(VTYPE, VLMUL, 0, 3) 123 FIELD(VTYPE, VSEW, 3, 3) 124 FIELD(VTYPE, VTA, 6, 1) 125 FIELD(VTYPE, VMA, 7, 1) 126 FIELD(VTYPE, VEDIV, 8, 2) 127 FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) 128 129 typedef struct PMUCTRState { 130 /* Current value of a counter */ 131 target_ulong mhpmcounter_val; 132 /* Current value of a counter in RV32*/ 133 target_ulong mhpmcounterh_val; 134 /* Snapshot values of counter */ 135 target_ulong mhpmcounter_prev; 136 /* Snapshort value of a counter in RV32 */ 137 target_ulong mhpmcounterh_prev; 138 bool started; 139 } PMUCTRState; 140 141 struct CPUArchState { 142 target_ulong gpr[32]; 143 target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ 144 uint64_t fpr[32]; /* assume both F and D extensions */ 145 146 /* vector coprocessor state. */ 147 uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); 148 target_ulong vxrm; 149 target_ulong vxsat; 150 target_ulong vl; 151 target_ulong vstart; 152 target_ulong vtype; 153 bool vill; 154 155 target_ulong pc; 156 target_ulong load_res; 157 target_ulong load_val; 158 159 target_ulong frm; 160 161 target_ulong badaddr; 162 target_ulong bins; 163 164 target_ulong guest_phys_fault_addr; 165 166 target_ulong priv_ver; 167 target_ulong bext_ver; 168 target_ulong vext_ver; 169 170 /* RISCVMXL, but uint32_t for vmstate migration */ 171 uint32_t misa_mxl; /* current mxl */ 172 uint32_t misa_mxl_max; /* max mxl for this cpu */ 173 uint32_t misa_ext; /* current extensions */ 174 uint32_t misa_ext_mask; /* max ext for this cpu */ 175 uint32_t xl; /* current xlen */ 176 177 /* 128-bit helpers upper part return value */ 178 target_ulong retxh; 179 180 uint32_t features; 181 182 #ifdef CONFIG_USER_ONLY 183 uint32_t elf_flags; 184 #endif 185 186 #ifndef CONFIG_USER_ONLY 187 target_ulong priv; 188 /* This contains QEMU specific information about the virt state. */ 189 target_ulong virt; 190 target_ulong geilen; 191 target_ulong resetvec; 192 193 target_ulong mhartid; 194 /* 195 * For RV32 this is 32-bit mstatus and 32-bit mstatush. 196 * For RV64 this is a 64-bit mstatus. 197 */ 198 uint64_t mstatus; 199 200 uint64_t mip; 201 /* 202 * MIP contains the software writable version of SEIP ORed with the 203 * external interrupt value. The MIP register is always up-to-date. 204 * To keep track of the current source, we also save booleans of the values 205 * here. 206 */ 207 bool external_seip; 208 bool software_seip; 209 210 uint64_t miclaim; 211 212 uint64_t mie; 213 uint64_t mideleg; 214 215 target_ulong satp; /* since: priv-1.10.0 */ 216 target_ulong stval; 217 target_ulong medeleg; 218 219 target_ulong stvec; 220 target_ulong sepc; 221 target_ulong scause; 222 223 target_ulong mtvec; 224 target_ulong mepc; 225 target_ulong mcause; 226 target_ulong mtval; /* since: priv-1.10.0 */ 227 228 /* Machine and Supervisor interrupt priorities */ 229 uint8_t miprio[64]; 230 uint8_t siprio[64]; 231 232 /* AIA CSRs */ 233 target_ulong miselect; 234 target_ulong siselect; 235 236 /* Hypervisor CSRs */ 237 target_ulong hstatus; 238 target_ulong hedeleg; 239 uint64_t hideleg; 240 target_ulong hcounteren; 241 target_ulong htval; 242 target_ulong htinst; 243 target_ulong hgatp; 244 target_ulong hgeie; 245 target_ulong hgeip; 246 uint64_t htimedelta; 247 248 /* Hypervisor controlled virtual interrupt priorities */ 249 target_ulong hvictl; 250 uint8_t hviprio[64]; 251 252 /* Upper 64-bits of 128-bit CSRs */ 253 uint64_t mscratchh; 254 uint64_t sscratchh; 255 256 /* Virtual CSRs */ 257 /* 258 * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. 259 * For RV64 this is a 64-bit vsstatus. 260 */ 261 uint64_t vsstatus; 262 target_ulong vstvec; 263 target_ulong vsscratch; 264 target_ulong vsepc; 265 target_ulong vscause; 266 target_ulong vstval; 267 target_ulong vsatp; 268 269 /* AIA VS-mode CSRs */ 270 target_ulong vsiselect; 271 272 target_ulong mtval2; 273 target_ulong mtinst; 274 275 /* HS Backup CSRs */ 276 target_ulong stvec_hs; 277 target_ulong sscratch_hs; 278 target_ulong sepc_hs; 279 target_ulong scause_hs; 280 target_ulong stval_hs; 281 target_ulong satp_hs; 282 uint64_t mstatus_hs; 283 284 /* Signals whether the current exception occurred with two-stage address 285 translation active. */ 286 bool two_stage_lookup; 287 /* 288 * Signals whether the current exception occurred while doing two-stage 289 * address translation for the VS-stage page table walk. 290 */ 291 bool two_stage_indirect_lookup; 292 293 target_ulong scounteren; 294 target_ulong mcounteren; 295 296 target_ulong mcountinhibit; 297 298 /* PMU counter state */ 299 PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS]; 300 301 /* PMU event selector configured values. First three are unused*/ 302 target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS]; 303 304 target_ulong sscratch; 305 target_ulong mscratch; 306 307 /* temporary htif regs */ 308 uint64_t mfromhost; 309 uint64_t mtohost; 310 311 /* physical memory protection */ 312 pmp_table_t pmp_state; 313 target_ulong mseccfg; 314 315 /* trigger module */ 316 target_ulong trigger_cur; 317 type2_trigger_t type2_trig[TRIGGER_TYPE2_NUM]; 318 319 /* machine specific rdtime callback */ 320 uint64_t (*rdtime_fn)(void *); 321 void *rdtime_fn_arg; 322 323 /* machine specific AIA ireg read-modify-write callback */ 324 #define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \ 325 ((((__xlen) & 0xff) << 24) | \ 326 (((__vgein) & 0x3f) << 20) | \ 327 (((__virt) & 0x1) << 18) | \ 328 (((__priv) & 0x3) << 16) | \ 329 (__isel & 0xffff)) 330 #define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff) 331 #define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3) 332 #define AIA_IREG_VIRT(__ireg) (((__ireg) >> 18) & 0x1) 333 #define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 20) & 0x3f) 334 #define AIA_IREG_XLEN(__ireg) (((__ireg) >> 24) & 0xff) 335 int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg, 336 target_ulong *val, target_ulong new_val, target_ulong write_mask); 337 void *aia_ireg_rmw_fn_arg[4]; 338 339 /* True if in debugger mode. */ 340 bool debugger; 341 342 /* 343 * CSRs for PointerMasking extension 344 */ 345 target_ulong mmte; 346 target_ulong mpmmask; 347 target_ulong mpmbase; 348 target_ulong spmmask; 349 target_ulong spmbase; 350 target_ulong upmmask; 351 target_ulong upmbase; 352 353 /* CSRs for execution enviornment configuration */ 354 uint64_t menvcfg; 355 target_ulong senvcfg; 356 uint64_t henvcfg; 357 #endif 358 target_ulong cur_pmmask; 359 target_ulong cur_pmbase; 360 361 float_status fp_status; 362 363 /* Fields from here on are preserved across CPU reset. */ 364 365 hwaddr kernel_addr; 366 hwaddr fdt_addr; 367 368 /* kvm timer */ 369 bool kvm_timer_dirty; 370 uint64_t kvm_timer_time; 371 uint64_t kvm_timer_compare; 372 uint64_t kvm_timer_state; 373 uint64_t kvm_timer_frequency; 374 }; 375 376 OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) 377 378 /** 379 * RISCVCPUClass: 380 * @parent_realize: The parent class' realize handler. 381 * @parent_reset: The parent class' reset handler. 382 * 383 * A RISCV CPU model. 384 */ 385 struct RISCVCPUClass { 386 /*< private >*/ 387 CPUClass parent_class; 388 /*< public >*/ 389 DeviceRealize parent_realize; 390 DeviceReset parent_reset; 391 }; 392 393 struct RISCVCPUConfig { 394 bool ext_i; 395 bool ext_e; 396 bool ext_g; 397 bool ext_m; 398 bool ext_a; 399 bool ext_f; 400 bool ext_d; 401 bool ext_c; 402 bool ext_s; 403 bool ext_u; 404 bool ext_h; 405 bool ext_j; 406 bool ext_v; 407 bool ext_zba; 408 bool ext_zbb; 409 bool ext_zbc; 410 bool ext_zbkb; 411 bool ext_zbkc; 412 bool ext_zbkx; 413 bool ext_zbs; 414 bool ext_zk; 415 bool ext_zkn; 416 bool ext_zknd; 417 bool ext_zkne; 418 bool ext_zknh; 419 bool ext_zkr; 420 bool ext_zks; 421 bool ext_zksed; 422 bool ext_zksh; 423 bool ext_zkt; 424 bool ext_ifencei; 425 bool ext_icsr; 426 bool ext_zihintpause; 427 bool ext_svinval; 428 bool ext_svnapot; 429 bool ext_svpbmt; 430 bool ext_zdinx; 431 bool ext_zfh; 432 bool ext_zfhmin; 433 bool ext_zfinx; 434 bool ext_zhinx; 435 bool ext_zhinxmin; 436 bool ext_zve32f; 437 bool ext_zve64f; 438 bool ext_zmmul; 439 bool ext_smaia; 440 bool ext_ssaia; 441 bool rvv_ta_all_1s; 442 bool rvv_ma_all_1s; 443 444 uint32_t mvendorid; 445 uint64_t marchid; 446 uint64_t mimpid; 447 448 /* Vendor-specific custom extensions */ 449 bool ext_XVentanaCondOps; 450 451 uint8_t pmu_num; 452 char *priv_spec; 453 char *user_spec; 454 char *bext_spec; 455 char *vext_spec; 456 uint16_t vlen; 457 uint16_t elen; 458 bool mmu; 459 bool pmp; 460 bool epmp; 461 bool debug; 462 uint64_t resetvec; 463 464 bool short_isa_string; 465 }; 466 467 typedef struct RISCVCPUConfig RISCVCPUConfig; 468 469 /** 470 * RISCVCPU: 471 * @env: #CPURISCVState 472 * 473 * A RISCV CPU. 474 */ 475 struct ArchCPU { 476 /*< private >*/ 477 CPUState parent_obj; 478 /*< public >*/ 479 CPUNegativeOffsetState neg; 480 CPURISCVState env; 481 482 char *dyn_csr_xml; 483 char *dyn_vreg_xml; 484 485 /* Configuration Settings */ 486 RISCVCPUConfig cfg; 487 }; 488 489 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) 490 { 491 return (env->misa_ext & ext) != 0; 492 } 493 494 static inline bool riscv_feature(CPURISCVState *env, int feature) 495 { 496 return env->features & (1ULL << feature); 497 } 498 499 static inline void riscv_set_feature(CPURISCVState *env, int feature) 500 { 501 env->features |= (1ULL << feature); 502 } 503 504 #include "cpu_user.h" 505 506 extern const char * const riscv_int_regnames[]; 507 extern const char * const riscv_int_regnamesh[]; 508 extern const char * const riscv_fpr_regnames[]; 509 510 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); 511 void riscv_cpu_do_interrupt(CPUState *cpu); 512 int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 513 int cpuid, void *opaque); 514 int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 515 int cpuid, void *opaque); 516 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 517 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 518 int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero); 519 uint8_t riscv_cpu_default_priority(int irq); 520 uint64_t riscv_cpu_all_pending(CPURISCVState *env); 521 int riscv_cpu_mirq_pending(CPURISCVState *env); 522 int riscv_cpu_sirq_pending(CPURISCVState *env); 523 int riscv_cpu_vsirq_pending(CPURISCVState *env); 524 bool riscv_cpu_fp_enabled(CPURISCVState *env); 525 target_ulong riscv_cpu_get_geilen(CPURISCVState *env); 526 void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); 527 bool riscv_cpu_vector_enabled(CPURISCVState *env); 528 bool riscv_cpu_virt_enabled(CPURISCVState *env); 529 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); 530 bool riscv_cpu_two_stage_lookup(int mmu_idx); 531 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); 532 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 533 G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 534 MMUAccessType access_type, int mmu_idx, 535 uintptr_t retaddr); 536 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 537 MMUAccessType access_type, int mmu_idx, 538 bool probe, uintptr_t retaddr); 539 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 540 vaddr addr, unsigned size, 541 MMUAccessType access_type, 542 int mmu_idx, MemTxAttrs attrs, 543 MemTxResult response, uintptr_t retaddr); 544 char *riscv_isa_string(RISCVCPU *cpu); 545 void riscv_cpu_list(void); 546 547 #define cpu_list riscv_cpu_list 548 #define cpu_mmu_index riscv_cpu_mmu_index 549 550 #ifndef CONFIG_USER_ONLY 551 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); 552 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); 553 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); 554 uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value); 555 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ 556 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), 557 void *arg); 558 void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, 559 int (*rmw_fn)(void *arg, 560 target_ulong reg, 561 target_ulong *val, 562 target_ulong new_val, 563 target_ulong write_mask), 564 void *rmw_fn_arg); 565 #endif 566 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); 567 568 void riscv_translate_init(void); 569 G_NORETURN void riscv_raise_exception(CPURISCVState *env, 570 uint32_t exception, uintptr_t pc); 571 572 target_ulong riscv_cpu_get_fflags(CPURISCVState *env); 573 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); 574 575 #define TB_FLAGS_PRIV_MMU_MASK 3 576 #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2) 577 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS 578 #define TB_FLAGS_MSTATUS_VS MSTATUS_VS 579 580 #include "exec/cpu-all.h" 581 582 FIELD(TB_FLAGS, MEM_IDX, 0, 3) 583 FIELD(TB_FLAGS, LMUL, 3, 3) 584 FIELD(TB_FLAGS, SEW, 6, 3) 585 /* Skip MSTATUS_VS (0x600) bits */ 586 FIELD(TB_FLAGS, VL_EQ_VLMAX, 11, 1) 587 FIELD(TB_FLAGS, VILL, 12, 1) 588 /* Skip MSTATUS_FS (0x6000) bits */ 589 /* Is a Hypervisor instruction load/store allowed? */ 590 FIELD(TB_FLAGS, HLSX, 15, 1) 591 FIELD(TB_FLAGS, MSTATUS_HS_FS, 16, 2) 592 FIELD(TB_FLAGS, MSTATUS_HS_VS, 18, 2) 593 /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ 594 FIELD(TB_FLAGS, XL, 20, 2) 595 /* If PointerMasking should be applied */ 596 FIELD(TB_FLAGS, PM_MASK_ENABLED, 22, 1) 597 FIELD(TB_FLAGS, PM_BASE_ENABLED, 23, 1) 598 FIELD(TB_FLAGS, VTA, 24, 1) 599 FIELD(TB_FLAGS, VMA, 25, 1) 600 601 #ifdef TARGET_RISCV32 602 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) 603 #else 604 static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) 605 { 606 return env->misa_mxl; 607 } 608 #endif 609 #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env))) 610 611 #if defined(TARGET_RISCV32) 612 #define cpu_recompute_xl(env) ((void)(env), MXL_RV32) 613 #else 614 static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) 615 { 616 RISCVMXL xl = env->misa_mxl; 617 #if !defined(CONFIG_USER_ONLY) 618 /* 619 * When emulating a 32-bit-only cpu, use RV32. 620 * When emulating a 64-bit cpu, and MXL has been reduced to RV32, 621 * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened 622 * back to RV64 for lower privs. 623 */ 624 if (xl != MXL_RV32) { 625 switch (env->priv) { 626 case PRV_M: 627 break; 628 case PRV_U: 629 xl = get_field(env->mstatus, MSTATUS64_UXL); 630 break; 631 default: /* PRV_S | PRV_H */ 632 xl = get_field(env->mstatus, MSTATUS64_SXL); 633 break; 634 } 635 } 636 #endif 637 return xl; 638 } 639 #endif 640 641 static inline int riscv_cpu_xlen(CPURISCVState *env) 642 { 643 return 16 << env->xl; 644 } 645 646 #ifdef TARGET_RISCV32 647 #define riscv_cpu_sxl(env) ((void)(env), MXL_RV32) 648 #else 649 static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env) 650 { 651 #ifdef CONFIG_USER_ONLY 652 return env->misa_mxl; 653 #else 654 return get_field(env->mstatus, MSTATUS64_SXL); 655 #endif 656 } 657 #endif 658 659 /* 660 * Encode LMUL to lmul as follows: 661 * LMUL vlmul lmul 662 * 1 000 0 663 * 2 001 1 664 * 4 010 2 665 * 8 011 3 666 * - 100 - 667 * 1/8 101 -3 668 * 1/4 110 -2 669 * 1/2 111 -1 670 * 671 * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul) 672 * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8 673 * => VLMAX = vlen >> (1 + 3 - (-3)) 674 * = 256 >> 7 675 * = 2 676 */ 677 static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) 678 { 679 uint8_t sew = FIELD_EX64(vtype, VTYPE, VSEW); 680 int8_t lmul = sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3); 681 return cpu->cfg.vlen >> (sew + 3 - lmul); 682 } 683 684 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 685 target_ulong *cs_base, uint32_t *pflags); 686 687 void riscv_cpu_update_mask(CPURISCVState *env); 688 689 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, 690 target_ulong *ret_value, 691 target_ulong new_value, target_ulong write_mask); 692 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, 693 target_ulong *ret_value, 694 target_ulong new_value, 695 target_ulong write_mask); 696 697 static inline void riscv_csr_write(CPURISCVState *env, int csrno, 698 target_ulong val) 699 { 700 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); 701 } 702 703 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) 704 { 705 target_ulong val = 0; 706 riscv_csrrw(env, csrno, &val, 0, 0); 707 return val; 708 } 709 710 typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, 711 int csrno); 712 typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, 713 target_ulong *ret_value); 714 typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, 715 target_ulong new_value); 716 typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, 717 target_ulong *ret_value, 718 target_ulong new_value, 719 target_ulong write_mask); 720 721 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, 722 Int128 *ret_value, 723 Int128 new_value, Int128 write_mask); 724 725 typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno, 726 Int128 *ret_value); 727 typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int csrno, 728 Int128 new_value); 729 730 typedef struct { 731 const char *name; 732 riscv_csr_predicate_fn predicate; 733 riscv_csr_read_fn read; 734 riscv_csr_write_fn write; 735 riscv_csr_op_fn op; 736 riscv_csr_read128_fn read128; 737 riscv_csr_write128_fn write128; 738 /* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0) */ 739 uint32_t min_priv_ver; 740 } riscv_csr_operations; 741 742 /* CSR function table constants */ 743 enum { 744 CSR_TABLE_SIZE = 0x1000 745 }; 746 747 /* CSR function table */ 748 extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; 749 750 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); 751 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); 752 753 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); 754 755 #endif /* RISCV_CPU_H */ 756