1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef RISCV_CPU_H 21 #define RISCV_CPU_H 22 23 #include "qemu-common.h" 24 #include "qom/cpu.h" 25 #include "exec/cpu-defs.h" 26 #include "fpu/softfloat.h" 27 28 #define TCG_GUEST_DEFAULT_MO 0 29 30 #define CPUArchState struct CPURISCVState 31 32 #define TYPE_RISCV_CPU "riscv-cpu" 33 34 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU 35 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) 36 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU 37 38 #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") 39 #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") 40 #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") 41 #define TYPE_RISCV_CPU_RV32GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9.1") 42 #define TYPE_RISCV_CPU_RV32GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.10.0") 43 #define TYPE_RISCV_CPU_RV32IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv32imacu-nommu") 44 #define TYPE_RISCV_CPU_RV64GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.9.1") 45 #define TYPE_RISCV_CPU_RV64GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.10.0") 46 #define TYPE_RISCV_CPU_RV64IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv64imacu-nommu") 47 #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") 48 #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") 49 #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") 50 #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") 51 52 #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2)) 53 #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2)) 54 55 #if defined(TARGET_RISCV32) 56 #define RVXLEN RV32 57 #elif defined(TARGET_RISCV64) 58 #define RVXLEN RV64 59 #endif 60 61 #define RV(x) ((target_ulong)1 << (x - 'A')) 62 63 #define RVI RV('I') 64 #define RVE RV('E') /* E and I are mutually exclusive */ 65 #define RVM RV('M') 66 #define RVA RV('A') 67 #define RVF RV('F') 68 #define RVD RV('D') 69 #define RVC RV('C') 70 #define RVS RV('S') 71 #define RVU RV('U') 72 73 /* S extension denotes that Supervisor mode exists, however it is possible 74 to have a core that support S mode but does not have an MMU and there 75 is currently no bit in misa to indicate whether an MMU exists or not 76 so a cpu features bitfield is required, likewise for optional PMP support */ 77 enum { 78 RISCV_FEATURE_MMU, 79 RISCV_FEATURE_PMP, 80 RISCV_FEATURE_MISA 81 }; 82 83 #define USER_VERSION_2_02_0 0x00020200 84 #define PRIV_VERSION_1_09_1 0x00010901 85 #define PRIV_VERSION_1_10_0 0x00011000 86 87 #define TRANSLATE_FAIL 1 88 #define TRANSLATE_SUCCESS 0 89 #define MMU_USER_IDX 3 90 91 #define MAX_RISCV_PMPS (16) 92 93 typedef struct CPURISCVState CPURISCVState; 94 95 #include "pmp.h" 96 97 struct CPURISCVState { 98 target_ulong gpr[32]; 99 uint64_t fpr[32]; /* assume both F and D extensions */ 100 target_ulong pc; 101 target_ulong load_res; 102 target_ulong load_val; 103 104 target_ulong frm; 105 106 target_ulong badaddr; 107 108 target_ulong user_ver; 109 target_ulong priv_ver; 110 target_ulong misa; 111 target_ulong misa_mask; 112 113 uint32_t features; 114 115 #ifdef CONFIG_USER_ONLY 116 uint32_t elf_flags; 117 #endif 118 119 #ifndef CONFIG_USER_ONLY 120 target_ulong priv; 121 target_ulong resetvec; 122 123 target_ulong mhartid; 124 target_ulong mstatus; 125 126 /* 127 * CAUTION! Unlike the rest of this struct, mip is accessed asynchonously 128 * by I/O threads. It should be read with atomic_read. It should be updated 129 * using riscv_cpu_update_mip with the iothread mutex held. The iothread 130 * mutex must be held because mip must be consistent with the CPU inturrept 131 * state. riscv_cpu_update_mip calls cpu_interrupt or cpu_reset_interrupt 132 * wuth the invariant that CPU_INTERRUPT_HARD is set iff mip is non-zero. 133 * mip is 32-bits to allow atomic_read on 32-bit hosts. 134 */ 135 uint32_t mip; 136 uint32_t miclaim; 137 138 target_ulong mie; 139 target_ulong mideleg; 140 141 target_ulong sptbr; /* until: priv-1.9.1 */ 142 target_ulong satp; /* since: priv-1.10.0 */ 143 target_ulong sbadaddr; 144 target_ulong mbadaddr; 145 target_ulong medeleg; 146 147 target_ulong stvec; 148 target_ulong sepc; 149 target_ulong scause; 150 151 target_ulong mtvec; 152 target_ulong mepc; 153 target_ulong mcause; 154 target_ulong mtval; /* since: priv-1.10.0 */ 155 156 target_ulong scounteren; 157 target_ulong mcounteren; 158 159 target_ulong sscratch; 160 target_ulong mscratch; 161 162 /* temporary htif regs */ 163 uint64_t mfromhost; 164 uint64_t mtohost; 165 uint64_t timecmp; 166 167 /* physical memory protection */ 168 pmp_table_t pmp_state; 169 170 /* True if in debugger mode. */ 171 bool debugger; 172 #endif 173 174 float_status fp_status; 175 176 /* QEMU */ 177 CPU_COMMON 178 179 /* Fields from here on are preserved across CPU reset. */ 180 QEMUTimer *timer; /* Internal timer */ 181 }; 182 183 #define RISCV_CPU_CLASS(klass) \ 184 OBJECT_CLASS_CHECK(RISCVCPUClass, (klass), TYPE_RISCV_CPU) 185 #define RISCV_CPU(obj) \ 186 OBJECT_CHECK(RISCVCPU, (obj), TYPE_RISCV_CPU) 187 #define RISCV_CPU_GET_CLASS(obj) \ 188 OBJECT_GET_CLASS(RISCVCPUClass, (obj), TYPE_RISCV_CPU) 189 190 /** 191 * RISCVCPUClass: 192 * @parent_realize: The parent class' realize handler. 193 * @parent_reset: The parent class' reset handler. 194 * 195 * A RISCV CPU model. 196 */ 197 typedef struct RISCVCPUClass { 198 /*< private >*/ 199 CPUClass parent_class; 200 /*< public >*/ 201 DeviceRealize parent_realize; 202 void (*parent_reset)(CPUState *cpu); 203 } RISCVCPUClass; 204 205 /** 206 * RISCVCPU: 207 * @env: #CPURISCVState 208 * 209 * A RISCV CPU. 210 */ 211 typedef struct RISCVCPU { 212 /*< private >*/ 213 CPUState parent_obj; 214 /*< public >*/ 215 CPURISCVState env; 216 217 /* Configuration Settings */ 218 struct { 219 char *priv_spec; 220 char *user_spec; 221 bool mmu; 222 bool pmp; 223 } cfg; 224 } RISCVCPU; 225 226 static inline RISCVCPU *riscv_env_get_cpu(CPURISCVState *env) 227 { 228 return container_of(env, RISCVCPU, env); 229 } 230 231 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) 232 { 233 return (env->misa & ext) != 0; 234 } 235 236 static inline bool riscv_feature(CPURISCVState *env, int feature) 237 { 238 return env->features & (1ULL << feature); 239 } 240 241 #include "cpu_user.h" 242 #include "cpu_bits.h" 243 244 extern const char * const riscv_int_regnames[]; 245 extern const char * const riscv_fpr_regnames[]; 246 extern const char * const riscv_excp_names[]; 247 extern const char * const riscv_intr_names[]; 248 249 #define ENV_GET_CPU(e) CPU(riscv_env_get_cpu(e)) 250 #define ENV_OFFSET offsetof(RISCVCPU, env) 251 252 void riscv_cpu_do_interrupt(CPUState *cpu); 253 int riscv_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 254 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 255 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); 256 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); 257 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 258 void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 259 MMUAccessType access_type, int mmu_idx, 260 uintptr_t retaddr); 261 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 262 MMUAccessType access_type, int mmu_idx, 263 bool probe, uintptr_t retaddr); 264 char *riscv_isa_string(RISCVCPU *cpu); 265 void riscv_cpu_list(void); 266 267 #define cpu_signal_handler riscv_cpu_signal_handler 268 #define cpu_list riscv_cpu_list 269 #define cpu_mmu_index riscv_cpu_mmu_index 270 271 #ifndef CONFIG_USER_ONLY 272 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts); 273 uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value); 274 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ 275 #endif 276 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); 277 278 void riscv_translate_init(void); 279 int riscv_cpu_signal_handler(int host_signum, void *pinfo, void *puc); 280 void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env, 281 uint32_t exception, uintptr_t pc); 282 283 target_ulong riscv_cpu_get_fflags(CPURISCVState *env); 284 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); 285 286 #define TB_FLAGS_MMU_MASK 3 287 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS 288 289 static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 290 target_ulong *cs_base, uint32_t *flags) 291 { 292 *pc = env->pc; 293 *cs_base = 0; 294 #ifdef CONFIG_USER_ONLY 295 *flags = TB_FLAGS_MSTATUS_FS; 296 #else 297 *flags = cpu_mmu_index(env, 0) | (env->mstatus & MSTATUS_FS); 298 #endif 299 } 300 301 int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, 302 target_ulong new_value, target_ulong write_mask); 303 int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value, 304 target_ulong new_value, target_ulong write_mask); 305 306 static inline void riscv_csr_write(CPURISCVState *env, int csrno, 307 target_ulong val) 308 { 309 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); 310 } 311 312 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) 313 { 314 target_ulong val = 0; 315 riscv_csrrw(env, csrno, &val, 0, 0); 316 return val; 317 } 318 319 typedef int (*riscv_csr_predicate_fn)(CPURISCVState *env, int csrno); 320 typedef int (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, 321 target_ulong *ret_value); 322 typedef int (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, 323 target_ulong new_value); 324 typedef int (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, 325 target_ulong *ret_value, target_ulong new_value, target_ulong write_mask); 326 327 typedef struct { 328 riscv_csr_predicate_fn predicate; 329 riscv_csr_read_fn read; 330 riscv_csr_write_fn write; 331 riscv_csr_op_fn op; 332 } riscv_csr_operations; 333 334 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); 335 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); 336 337 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); 338 339 #include "exec/cpu-all.h" 340 341 #endif /* RISCV_CPU_H */ 342