1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef RISCV_CPU_H 21 #define RISCV_CPU_H 22 23 #include "hw/core/cpu.h" 24 #include "hw/registerfields.h" 25 #include "exec/cpu-defs.h" 26 #include "fpu/softfloat-types.h" 27 #include "qom/object.h" 28 29 #define TCG_GUEST_DEFAULT_MO 0 30 31 #define TYPE_RISCV_CPU "riscv-cpu" 32 33 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU 34 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) 35 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU 36 37 #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") 38 #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") 39 #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") 40 #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") 41 #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") 42 #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") 43 #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") 44 #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") 45 #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") 46 47 #if defined(TARGET_RISCV32) 48 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 49 #elif defined(TARGET_RISCV64) 50 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 51 #endif 52 53 #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2)) 54 #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2)) 55 56 #if defined(TARGET_RISCV32) 57 #define RVXLEN RV32 58 #elif defined(TARGET_RISCV64) 59 #define RVXLEN RV64 60 #endif 61 62 #define RV(x) ((target_ulong)1 << (x - 'A')) 63 64 #define RVI RV('I') 65 #define RVE RV('E') /* E and I are mutually exclusive */ 66 #define RVM RV('M') 67 #define RVA RV('A') 68 #define RVF RV('F') 69 #define RVD RV('D') 70 #define RVV RV('V') 71 #define RVC RV('C') 72 #define RVS RV('S') 73 #define RVU RV('U') 74 #define RVH RV('H') 75 76 /* S extension denotes that Supervisor mode exists, however it is possible 77 to have a core that support S mode but does not have an MMU and there 78 is currently no bit in misa to indicate whether an MMU exists or not 79 so a cpu features bitfield is required, likewise for optional PMP support */ 80 enum { 81 RISCV_FEATURE_MMU, 82 RISCV_FEATURE_PMP, 83 RISCV_FEATURE_MISA 84 }; 85 86 #define PRIV_VERSION_1_10_0 0x00011000 87 #define PRIV_VERSION_1_11_0 0x00011100 88 89 #define VEXT_VERSION_0_07_1 0x00000701 90 91 enum { 92 TRANSLATE_SUCCESS, 93 TRANSLATE_FAIL, 94 TRANSLATE_PMP_FAIL, 95 TRANSLATE_G_STAGE_FAIL 96 }; 97 98 #define MMU_USER_IDX 3 99 100 #define MAX_RISCV_PMPS (16) 101 102 typedef struct CPURISCVState CPURISCVState; 103 104 #include "pmp.h" 105 106 #define RV_VLEN_MAX 256 107 108 FIELD(VTYPE, VLMUL, 0, 2) 109 FIELD(VTYPE, VSEW, 2, 3) 110 FIELD(VTYPE, VEDIV, 5, 2) 111 FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 9) 112 FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1) 113 114 struct CPURISCVState { 115 target_ulong gpr[32]; 116 uint64_t fpr[32]; /* assume both F and D extensions */ 117 118 /* vector coprocessor state. */ 119 uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); 120 target_ulong vxrm; 121 target_ulong vxsat; 122 target_ulong vl; 123 target_ulong vstart; 124 target_ulong vtype; 125 126 target_ulong pc; 127 target_ulong load_res; 128 target_ulong load_val; 129 130 target_ulong frm; 131 132 target_ulong badaddr; 133 target_ulong guest_phys_fault_addr; 134 135 target_ulong priv_ver; 136 target_ulong vext_ver; 137 target_ulong misa; 138 target_ulong misa_mask; 139 140 uint32_t features; 141 142 #ifdef CONFIG_USER_ONLY 143 uint32_t elf_flags; 144 #endif 145 146 #ifndef CONFIG_USER_ONLY 147 target_ulong priv; 148 /* This contains QEMU specific information about the virt state. */ 149 target_ulong virt; 150 target_ulong resetvec; 151 152 target_ulong mhartid; 153 /* 154 * For RV32 this is 32-bit mstatus and 32-bit mstatush. 155 * For RV64 this is a 64-bit mstatus. 156 */ 157 uint64_t mstatus; 158 159 target_ulong mip; 160 161 uint32_t miclaim; 162 163 target_ulong mie; 164 target_ulong mideleg; 165 166 target_ulong sptbr; /* until: priv-1.9.1 */ 167 target_ulong satp; /* since: priv-1.10.0 */ 168 target_ulong sbadaddr; 169 target_ulong mbadaddr; 170 target_ulong medeleg; 171 172 target_ulong stvec; 173 target_ulong sepc; 174 target_ulong scause; 175 176 target_ulong mtvec; 177 target_ulong mepc; 178 target_ulong mcause; 179 target_ulong mtval; /* since: priv-1.10.0 */ 180 181 /* Hypervisor CSRs */ 182 target_ulong hstatus; 183 target_ulong hedeleg; 184 target_ulong hideleg; 185 target_ulong hcounteren; 186 target_ulong htval; 187 target_ulong htinst; 188 target_ulong hgatp; 189 uint64_t htimedelta; 190 191 /* Virtual CSRs */ 192 /* 193 * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. 194 * For RV64 this is a 64-bit vsstatus. 195 */ 196 uint64_t vsstatus; 197 target_ulong vstvec; 198 target_ulong vsscratch; 199 target_ulong vsepc; 200 target_ulong vscause; 201 target_ulong vstval; 202 target_ulong vsatp; 203 204 target_ulong mtval2; 205 target_ulong mtinst; 206 207 /* HS Backup CSRs */ 208 target_ulong stvec_hs; 209 target_ulong sscratch_hs; 210 target_ulong sepc_hs; 211 target_ulong scause_hs; 212 target_ulong stval_hs; 213 target_ulong satp_hs; 214 uint64_t mstatus_hs; 215 216 target_ulong scounteren; 217 target_ulong mcounteren; 218 219 target_ulong sscratch; 220 target_ulong mscratch; 221 222 /* temporary htif regs */ 223 uint64_t mfromhost; 224 uint64_t mtohost; 225 uint64_t timecmp; 226 227 /* physical memory protection */ 228 pmp_table_t pmp_state; 229 230 /* machine specific rdtime callback */ 231 uint64_t (*rdtime_fn)(uint32_t); 232 uint32_t rdtime_fn_arg; 233 234 /* True if in debugger mode. */ 235 bool debugger; 236 #endif 237 238 float_status fp_status; 239 240 /* Fields from here on are preserved across CPU reset. */ 241 QEMUTimer *timer; /* Internal timer */ 242 }; 243 244 OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass, 245 RISCV_CPU) 246 247 /** 248 * RISCVCPUClass: 249 * @parent_realize: The parent class' realize handler. 250 * @parent_reset: The parent class' reset handler. 251 * 252 * A RISCV CPU model. 253 */ 254 struct RISCVCPUClass { 255 /*< private >*/ 256 CPUClass parent_class; 257 /*< public >*/ 258 DeviceRealize parent_realize; 259 DeviceReset parent_reset; 260 }; 261 262 /** 263 * RISCVCPU: 264 * @env: #CPURISCVState 265 * 266 * A RISCV CPU. 267 */ 268 struct RISCVCPU { 269 /*< private >*/ 270 CPUState parent_obj; 271 /*< public >*/ 272 CPUNegativeOffsetState neg; 273 CPURISCVState env; 274 275 char *dyn_csr_xml; 276 277 /* Configuration Settings */ 278 struct { 279 bool ext_i; 280 bool ext_e; 281 bool ext_g; 282 bool ext_m; 283 bool ext_a; 284 bool ext_f; 285 bool ext_d; 286 bool ext_c; 287 bool ext_s; 288 bool ext_u; 289 bool ext_h; 290 bool ext_v; 291 bool ext_counters; 292 bool ext_ifencei; 293 bool ext_icsr; 294 295 char *priv_spec; 296 char *user_spec; 297 char *vext_spec; 298 uint16_t vlen; 299 uint16_t elen; 300 bool mmu; 301 bool pmp; 302 uint64_t resetvec; 303 } cfg; 304 }; 305 306 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) 307 { 308 return (env->misa & ext) != 0; 309 } 310 311 static inline bool riscv_feature(CPURISCVState *env, int feature) 312 { 313 return env->features & (1ULL << feature); 314 } 315 316 #include "cpu_user.h" 317 #include "cpu_bits.h" 318 319 extern const char * const riscv_int_regnames[]; 320 extern const char * const riscv_fpr_regnames[]; 321 extern const char * const riscv_excp_names[]; 322 extern const char * const riscv_intr_names[]; 323 324 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); 325 void riscv_cpu_do_interrupt(CPUState *cpu); 326 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 327 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 328 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); 329 bool riscv_cpu_fp_enabled(CPURISCVState *env); 330 bool riscv_cpu_virt_enabled(CPURISCVState *env); 331 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); 332 bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env); 333 void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable); 334 bool riscv_cpu_two_stage_lookup(int mmu_idx); 335 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); 336 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 337 void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 338 MMUAccessType access_type, int mmu_idx, 339 uintptr_t retaddr); 340 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 341 MMUAccessType access_type, int mmu_idx, 342 bool probe, uintptr_t retaddr); 343 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 344 vaddr addr, unsigned size, 345 MMUAccessType access_type, 346 int mmu_idx, MemTxAttrs attrs, 347 MemTxResult response, uintptr_t retaddr); 348 char *riscv_isa_string(RISCVCPU *cpu); 349 void riscv_cpu_list(void); 350 351 #define cpu_signal_handler riscv_cpu_signal_handler 352 #define cpu_list riscv_cpu_list 353 #define cpu_mmu_index riscv_cpu_mmu_index 354 355 #ifndef CONFIG_USER_ONLY 356 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); 357 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts); 358 uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value); 359 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ 360 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t), 361 uint32_t arg); 362 #endif 363 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); 364 365 void riscv_translate_init(void); 366 int riscv_cpu_signal_handler(int host_signum, void *pinfo, void *puc); 367 void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env, 368 uint32_t exception, uintptr_t pc); 369 370 target_ulong riscv_cpu_get_fflags(CPURISCVState *env); 371 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); 372 373 #define TB_FLAGS_MMU_MASK 7 374 #define TB_FLAGS_PRIV_MMU_MASK 3 375 #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2) 376 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS 377 378 typedef CPURISCVState CPUArchState; 379 typedef RISCVCPU ArchCPU; 380 #include "exec/cpu-all.h" 381 382 FIELD(TB_FLAGS, VL_EQ_VLMAX, 2, 1) 383 FIELD(TB_FLAGS, LMUL, 3, 2) 384 FIELD(TB_FLAGS, SEW, 5, 3) 385 FIELD(TB_FLAGS, VILL, 8, 1) 386 /* Is a Hypervisor instruction load/store allowed? */ 387 FIELD(TB_FLAGS, HLSX, 9, 1) 388 389 bool riscv_cpu_is_32bit(CPURISCVState *env); 390 391 /* 392 * A simplification for VLMAX 393 * = (1 << LMUL) * VLEN / (8 * (1 << SEW)) 394 * = (VLEN << LMUL) / (8 << SEW) 395 * = (VLEN << LMUL) >> (SEW + 3) 396 * = VLEN >> (SEW + 3 - LMUL) 397 */ 398 static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) 399 { 400 uint8_t sew, lmul; 401 402 sew = FIELD_EX64(vtype, VTYPE, VSEW); 403 lmul = FIELD_EX64(vtype, VTYPE, VLMUL); 404 return cpu->cfg.vlen >> (sew + 3 - lmul); 405 } 406 407 static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 408 target_ulong *cs_base, uint32_t *pflags) 409 { 410 uint32_t flags = 0; 411 412 *pc = env->pc; 413 *cs_base = 0; 414 415 if (riscv_has_ext(env, RVV)) { 416 uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype); 417 bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl); 418 flags = FIELD_DP32(flags, TB_FLAGS, VILL, 419 FIELD_EX64(env->vtype, VTYPE, VILL)); 420 flags = FIELD_DP32(flags, TB_FLAGS, SEW, 421 FIELD_EX64(env->vtype, VTYPE, VSEW)); 422 flags = FIELD_DP32(flags, TB_FLAGS, LMUL, 423 FIELD_EX64(env->vtype, VTYPE, VLMUL)); 424 flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); 425 } else { 426 flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1); 427 } 428 429 #ifdef CONFIG_USER_ONLY 430 flags |= TB_FLAGS_MSTATUS_FS; 431 #else 432 flags |= cpu_mmu_index(env, 0); 433 if (riscv_cpu_fp_enabled(env)) { 434 flags |= env->mstatus & MSTATUS_FS; 435 } 436 437 if (riscv_has_ext(env, RVH)) { 438 if (env->priv == PRV_M || 439 (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || 440 (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) && 441 get_field(env->hstatus, HSTATUS_HU))) { 442 flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1); 443 } 444 } 445 #endif 446 447 *pflags = flags; 448 } 449 450 int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, 451 target_ulong new_value, target_ulong write_mask); 452 int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value, 453 target_ulong new_value, target_ulong write_mask); 454 455 static inline void riscv_csr_write(CPURISCVState *env, int csrno, 456 target_ulong val) 457 { 458 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); 459 } 460 461 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) 462 { 463 target_ulong val = 0; 464 riscv_csrrw(env, csrno, &val, 0, 0); 465 return val; 466 } 467 468 typedef int (*riscv_csr_predicate_fn)(CPURISCVState *env, int csrno); 469 typedef int (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, 470 target_ulong *ret_value); 471 typedef int (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, 472 target_ulong new_value); 473 typedef int (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, 474 target_ulong *ret_value, target_ulong new_value, target_ulong write_mask); 475 476 typedef struct { 477 const char *name; 478 riscv_csr_predicate_fn predicate; 479 riscv_csr_read_fn read; 480 riscv_csr_write_fn write; 481 riscv_csr_op_fn op; 482 } riscv_csr_operations; 483 484 /* CSR function table constants */ 485 enum { 486 CSR_TABLE_SIZE = 0x1000 487 }; 488 489 /* CSR function table */ 490 extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; 491 492 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); 493 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); 494 495 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); 496 497 #endif /* RISCV_CPU_H */ 498