1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef RISCV_CPU_H 21 #define RISCV_CPU_H 22 23 #include "hw/core/cpu.h" 24 #include "hw/registerfields.h" 25 #include "exec/cpu-defs.h" 26 #include "qemu/cpu-float.h" 27 #include "qom/object.h" 28 #include "qemu/int128.h" 29 #include "cpu_bits.h" 30 31 #define TCG_GUEST_DEFAULT_MO 0 32 33 /* 34 * RISC-V-specific extra insn start words: 35 * 1: Original instruction opcode 36 */ 37 #define TARGET_INSN_START_EXTRA_WORDS 1 38 39 #define TYPE_RISCV_CPU "riscv-cpu" 40 41 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU 42 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) 43 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU 44 45 #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") 46 #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") 47 #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") 48 #define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128") 49 #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") 50 #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") 51 #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") 52 #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") 53 #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") 54 #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") 55 #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") 56 #define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906") 57 #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") 58 59 #if defined(TARGET_RISCV32) 60 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 61 #elif defined(TARGET_RISCV64) 62 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 63 #endif 64 65 #define RV(x) ((target_ulong)1 << (x - 'A')) 66 67 /* 68 * Consider updating register_cpu_props() when adding 69 * new MISA bits here. 70 */ 71 #define RVI RV('I') 72 #define RVE RV('E') /* E and I are mutually exclusive */ 73 #define RVM RV('M') 74 #define RVA RV('A') 75 #define RVF RV('F') 76 #define RVD RV('D') 77 #define RVV RV('V') 78 #define RVC RV('C') 79 #define RVS RV('S') 80 #define RVU RV('U') 81 #define RVH RV('H') 82 #define RVJ RV('J') 83 84 /* S extension denotes that Supervisor mode exists, however it is possible 85 to have a core that support S mode but does not have an MMU and there 86 is currently no bit in misa to indicate whether an MMU exists or not 87 so a cpu features bitfield is required, likewise for optional PMP support */ 88 enum { 89 RISCV_FEATURE_MMU, 90 RISCV_FEATURE_PMP, 91 }; 92 93 /* Privileged specification version */ 94 enum { 95 PRIV_VERSION_1_10_0 = 0, 96 PRIV_VERSION_1_11_0, 97 PRIV_VERSION_1_12_0, 98 }; 99 100 #define VEXT_VERSION_1_00_0 0x00010000 101 102 enum { 103 TRANSLATE_SUCCESS, 104 TRANSLATE_FAIL, 105 TRANSLATE_PMP_FAIL, 106 TRANSLATE_G_STAGE_FAIL 107 }; 108 109 #define MMU_USER_IDX 3 110 111 #define MAX_RISCV_PMPS (16) 112 113 typedef struct CPUArchState CPURISCVState; 114 115 #if !defined(CONFIG_USER_ONLY) 116 #include "pmp.h" 117 #include "debug.h" 118 #endif 119 120 #define RV_VLEN_MAX 1024 121 #define RV_MAX_MHPMEVENTS 32 122 #define RV_MAX_MHPMCOUNTERS 32 123 124 FIELD(VTYPE, VLMUL, 0, 3) 125 FIELD(VTYPE, VSEW, 3, 3) 126 FIELD(VTYPE, VTA, 6, 1) 127 FIELD(VTYPE, VMA, 7, 1) 128 FIELD(VTYPE, VEDIV, 8, 2) 129 FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) 130 131 typedef struct PMUCTRState { 132 /* Current value of a counter */ 133 target_ulong mhpmcounter_val; 134 /* Current value of a counter in RV32*/ 135 target_ulong mhpmcounterh_val; 136 /* Snapshot values of counter */ 137 target_ulong mhpmcounter_prev; 138 /* Snapshort value of a counter in RV32 */ 139 target_ulong mhpmcounterh_prev; 140 bool started; 141 /* Value beyond UINT32_MAX/UINT64_MAX before overflow interrupt trigger */ 142 target_ulong irq_overflow_left; 143 } PMUCTRState; 144 145 struct CPUArchState { 146 target_ulong gpr[32]; 147 target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ 148 149 /* vector coprocessor state. */ 150 uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); 151 target_ulong vxrm; 152 target_ulong vxsat; 153 target_ulong vl; 154 target_ulong vstart; 155 target_ulong vtype; 156 bool vill; 157 158 target_ulong pc; 159 target_ulong load_res; 160 target_ulong load_val; 161 162 /* Floating-Point state */ 163 uint64_t fpr[32]; /* assume both F and D extensions */ 164 target_ulong frm; 165 float_status fp_status; 166 167 target_ulong badaddr; 168 target_ulong bins; 169 170 target_ulong guest_phys_fault_addr; 171 172 target_ulong priv_ver; 173 target_ulong bext_ver; 174 target_ulong vext_ver; 175 176 /* RISCVMXL, but uint32_t for vmstate migration */ 177 uint32_t misa_mxl; /* current mxl */ 178 uint32_t misa_mxl_max; /* max mxl for this cpu */ 179 uint32_t misa_ext; /* current extensions */ 180 uint32_t misa_ext_mask; /* max ext for this cpu */ 181 uint32_t xl; /* current xlen */ 182 183 /* 128-bit helpers upper part return value */ 184 target_ulong retxh; 185 186 uint32_t features; 187 188 #ifdef CONFIG_USER_ONLY 189 uint32_t elf_flags; 190 #endif 191 192 #ifndef CONFIG_USER_ONLY 193 target_ulong priv; 194 /* This contains QEMU specific information about the virt state. */ 195 target_ulong virt; 196 target_ulong geilen; 197 uint64_t resetvec; 198 199 target_ulong mhartid; 200 /* 201 * For RV32 this is 32-bit mstatus and 32-bit mstatush. 202 * For RV64 this is a 64-bit mstatus. 203 */ 204 uint64_t mstatus; 205 206 uint64_t mip; 207 /* 208 * MIP contains the software writable version of SEIP ORed with the 209 * external interrupt value. The MIP register is always up-to-date. 210 * To keep track of the current source, we also save booleans of the values 211 * here. 212 */ 213 bool external_seip; 214 bool software_seip; 215 216 uint64_t miclaim; 217 218 uint64_t mie; 219 uint64_t mideleg; 220 221 target_ulong satp; /* since: priv-1.10.0 */ 222 target_ulong stval; 223 target_ulong medeleg; 224 225 target_ulong stvec; 226 target_ulong sepc; 227 target_ulong scause; 228 229 target_ulong mtvec; 230 target_ulong mepc; 231 target_ulong mcause; 232 target_ulong mtval; /* since: priv-1.10.0 */ 233 234 /* Machine and Supervisor interrupt priorities */ 235 uint8_t miprio[64]; 236 uint8_t siprio[64]; 237 238 /* AIA CSRs */ 239 target_ulong miselect; 240 target_ulong siselect; 241 242 /* Hypervisor CSRs */ 243 target_ulong hstatus; 244 target_ulong hedeleg; 245 uint64_t hideleg; 246 target_ulong hcounteren; 247 target_ulong htval; 248 target_ulong htinst; 249 target_ulong hgatp; 250 target_ulong hgeie; 251 target_ulong hgeip; 252 uint64_t htimedelta; 253 254 /* Hypervisor controlled virtual interrupt priorities */ 255 target_ulong hvictl; 256 uint8_t hviprio[64]; 257 258 /* Upper 64-bits of 128-bit CSRs */ 259 uint64_t mscratchh; 260 uint64_t sscratchh; 261 262 /* Virtual CSRs */ 263 /* 264 * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. 265 * For RV64 this is a 64-bit vsstatus. 266 */ 267 uint64_t vsstatus; 268 target_ulong vstvec; 269 target_ulong vsscratch; 270 target_ulong vsepc; 271 target_ulong vscause; 272 target_ulong vstval; 273 target_ulong vsatp; 274 275 /* AIA VS-mode CSRs */ 276 target_ulong vsiselect; 277 278 target_ulong mtval2; 279 target_ulong mtinst; 280 281 /* HS Backup CSRs */ 282 target_ulong stvec_hs; 283 target_ulong sscratch_hs; 284 target_ulong sepc_hs; 285 target_ulong scause_hs; 286 target_ulong stval_hs; 287 target_ulong satp_hs; 288 uint64_t mstatus_hs; 289 290 /* Signals whether the current exception occurred with two-stage address 291 translation active. */ 292 bool two_stage_lookup; 293 /* 294 * Signals whether the current exception occurred while doing two-stage 295 * address translation for the VS-stage page table walk. 296 */ 297 bool two_stage_indirect_lookup; 298 299 target_ulong scounteren; 300 target_ulong mcounteren; 301 302 target_ulong mcountinhibit; 303 304 /* PMU counter state */ 305 PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS]; 306 307 /* PMU event selector configured values. First three are unused*/ 308 target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS]; 309 310 /* PMU event selector configured values for RV32*/ 311 target_ulong mhpmeventh_val[RV_MAX_MHPMEVENTS]; 312 313 target_ulong sscratch; 314 target_ulong mscratch; 315 316 /* Sstc CSRs */ 317 uint64_t stimecmp; 318 319 uint64_t vstimecmp; 320 321 /* physical memory protection */ 322 pmp_table_t pmp_state; 323 target_ulong mseccfg; 324 325 /* trigger module */ 326 target_ulong trigger_cur; 327 target_ulong tdata1[RV_MAX_TRIGGERS]; 328 target_ulong tdata2[RV_MAX_TRIGGERS]; 329 target_ulong tdata3[RV_MAX_TRIGGERS]; 330 struct CPUBreakpoint *cpu_breakpoint[RV_MAX_TRIGGERS]; 331 struct CPUWatchpoint *cpu_watchpoint[RV_MAX_TRIGGERS]; 332 QEMUTimer *itrigger_timer[RV_MAX_TRIGGERS]; 333 int64_t last_icount; 334 bool itrigger_enabled; 335 336 /* machine specific rdtime callback */ 337 uint64_t (*rdtime_fn)(void *); 338 void *rdtime_fn_arg; 339 340 /* machine specific AIA ireg read-modify-write callback */ 341 #define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \ 342 ((((__xlen) & 0xff) << 24) | \ 343 (((__vgein) & 0x3f) << 20) | \ 344 (((__virt) & 0x1) << 18) | \ 345 (((__priv) & 0x3) << 16) | \ 346 (__isel & 0xffff)) 347 #define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff) 348 #define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3) 349 #define AIA_IREG_VIRT(__ireg) (((__ireg) >> 18) & 0x1) 350 #define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 20) & 0x3f) 351 #define AIA_IREG_XLEN(__ireg) (((__ireg) >> 24) & 0xff) 352 int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg, 353 target_ulong *val, target_ulong new_val, target_ulong write_mask); 354 void *aia_ireg_rmw_fn_arg[4]; 355 356 /* True if in debugger mode. */ 357 bool debugger; 358 359 /* 360 * CSRs for PointerMasking extension 361 */ 362 target_ulong mmte; 363 target_ulong mpmmask; 364 target_ulong mpmbase; 365 target_ulong spmmask; 366 target_ulong spmbase; 367 target_ulong upmmask; 368 target_ulong upmbase; 369 370 /* CSRs for execution enviornment configuration */ 371 uint64_t menvcfg; 372 uint64_t mstateen[SMSTATEEN_MAX_COUNT]; 373 uint64_t hstateen[SMSTATEEN_MAX_COUNT]; 374 uint64_t sstateen[SMSTATEEN_MAX_COUNT]; 375 target_ulong senvcfg; 376 uint64_t henvcfg; 377 #endif 378 target_ulong cur_pmmask; 379 target_ulong cur_pmbase; 380 381 /* Fields from here on are preserved across CPU reset. */ 382 QEMUTimer *stimer; /* Internal timer for S-mode interrupt */ 383 QEMUTimer *vstimer; /* Internal timer for VS-mode interrupt */ 384 bool vstime_irq; 385 386 hwaddr kernel_addr; 387 hwaddr fdt_addr; 388 389 /* kvm timer */ 390 bool kvm_timer_dirty; 391 uint64_t kvm_timer_time; 392 uint64_t kvm_timer_compare; 393 uint64_t kvm_timer_state; 394 uint64_t kvm_timer_frequency; 395 }; 396 397 OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) 398 399 /** 400 * RISCVCPUClass: 401 * @parent_realize: The parent class' realize handler. 402 * @parent_phases: The parent class' reset phase handlers. 403 * 404 * A RISCV CPU model. 405 */ 406 struct RISCVCPUClass { 407 /*< private >*/ 408 CPUClass parent_class; 409 /*< public >*/ 410 DeviceRealize parent_realize; 411 ResettablePhases parent_phases; 412 }; 413 414 struct RISCVCPUConfig { 415 bool ext_i; 416 bool ext_e; 417 bool ext_g; 418 bool ext_m; 419 bool ext_a; 420 bool ext_f; 421 bool ext_d; 422 bool ext_c; 423 bool ext_s; 424 bool ext_u; 425 bool ext_h; 426 bool ext_j; 427 bool ext_v; 428 bool ext_zba; 429 bool ext_zbb; 430 bool ext_zbc; 431 bool ext_zbkb; 432 bool ext_zbkc; 433 bool ext_zbkx; 434 bool ext_zbs; 435 bool ext_zk; 436 bool ext_zkn; 437 bool ext_zknd; 438 bool ext_zkne; 439 bool ext_zknh; 440 bool ext_zkr; 441 bool ext_zks; 442 bool ext_zksed; 443 bool ext_zksh; 444 bool ext_zkt; 445 bool ext_ifencei; 446 bool ext_icsr; 447 bool ext_zihintpause; 448 bool ext_smstateen; 449 bool ext_sstc; 450 bool ext_svinval; 451 bool ext_svnapot; 452 bool ext_svpbmt; 453 bool ext_zdinx; 454 bool ext_zawrs; 455 bool ext_zfh; 456 bool ext_zfhmin; 457 bool ext_zfinx; 458 bool ext_zhinx; 459 bool ext_zhinxmin; 460 bool ext_zve32f; 461 bool ext_zve64f; 462 bool ext_zmmul; 463 bool ext_smaia; 464 bool ext_ssaia; 465 bool ext_sscofpmf; 466 bool rvv_ta_all_1s; 467 bool rvv_ma_all_1s; 468 469 uint32_t mvendorid; 470 uint64_t marchid; 471 uint64_t mimpid; 472 473 /* Vendor-specific custom extensions */ 474 bool ext_xtheadba; 475 bool ext_xtheadbb; 476 bool ext_xtheadbs; 477 bool ext_xtheadcmo; 478 bool ext_xtheadcondmov; 479 bool ext_xtheadfmemidx; 480 bool ext_xtheadfmv; 481 bool ext_xtheadmac; 482 bool ext_xtheadmemidx; 483 bool ext_xtheadmempair; 484 bool ext_xtheadsync; 485 bool ext_XVentanaCondOps; 486 487 uint8_t pmu_num; 488 char *priv_spec; 489 char *user_spec; 490 char *bext_spec; 491 char *vext_spec; 492 uint16_t vlen; 493 uint16_t elen; 494 bool mmu; 495 bool pmp; 496 bool epmp; 497 bool debug; 498 bool misa_w; 499 500 bool short_isa_string; 501 }; 502 503 typedef struct RISCVCPUConfig RISCVCPUConfig; 504 505 /** 506 * RISCVCPU: 507 * @env: #CPURISCVState 508 * 509 * A RISCV CPU. 510 */ 511 struct ArchCPU { 512 /*< private >*/ 513 CPUState parent_obj; 514 /*< public >*/ 515 CPUNegativeOffsetState neg; 516 CPURISCVState env; 517 518 char *dyn_csr_xml; 519 char *dyn_vreg_xml; 520 521 /* Configuration Settings */ 522 RISCVCPUConfig cfg; 523 524 QEMUTimer *pmu_timer; 525 /* A bitmask of Available programmable counters */ 526 uint32_t pmu_avail_ctrs; 527 /* Mapping of events to counters */ 528 GHashTable *pmu_event_ctr_map; 529 }; 530 531 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) 532 { 533 return (env->misa_ext & ext) != 0; 534 } 535 536 static inline bool riscv_feature(CPURISCVState *env, int feature) 537 { 538 return env->features & (1ULL << feature); 539 } 540 541 static inline void riscv_set_feature(CPURISCVState *env, int feature) 542 { 543 env->features |= (1ULL << feature); 544 } 545 546 #include "cpu_user.h" 547 548 extern const char * const riscv_int_regnames[]; 549 extern const char * const riscv_int_regnamesh[]; 550 extern const char * const riscv_fpr_regnames[]; 551 552 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); 553 void riscv_cpu_do_interrupt(CPUState *cpu); 554 int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 555 int cpuid, DumpState *s); 556 int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 557 int cpuid, DumpState *s); 558 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 559 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 560 int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero); 561 uint8_t riscv_cpu_default_priority(int irq); 562 uint64_t riscv_cpu_all_pending(CPURISCVState *env); 563 int riscv_cpu_mirq_pending(CPURISCVState *env); 564 int riscv_cpu_sirq_pending(CPURISCVState *env); 565 int riscv_cpu_vsirq_pending(CPURISCVState *env); 566 bool riscv_cpu_fp_enabled(CPURISCVState *env); 567 target_ulong riscv_cpu_get_geilen(CPURISCVState *env); 568 void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); 569 bool riscv_cpu_vector_enabled(CPURISCVState *env); 570 bool riscv_cpu_virt_enabled(CPURISCVState *env); 571 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); 572 bool riscv_cpu_two_stage_lookup(int mmu_idx); 573 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); 574 G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 575 MMUAccessType access_type, int mmu_idx, 576 uintptr_t retaddr); 577 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 578 MMUAccessType access_type, int mmu_idx, 579 bool probe, uintptr_t retaddr); 580 char *riscv_isa_string(RISCVCPU *cpu); 581 void riscv_cpu_list(void); 582 583 #define cpu_list riscv_cpu_list 584 #define cpu_mmu_index riscv_cpu_mmu_index 585 586 #ifndef CONFIG_USER_ONLY 587 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 588 vaddr addr, unsigned size, 589 MMUAccessType access_type, 590 int mmu_idx, MemTxAttrs attrs, 591 MemTxResult response, uintptr_t retaddr); 592 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 593 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); 594 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); 595 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); 596 uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value); 597 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ 598 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), 599 void *arg); 600 void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, 601 int (*rmw_fn)(void *arg, 602 target_ulong reg, 603 target_ulong *val, 604 target_ulong new_val, 605 target_ulong write_mask), 606 void *rmw_fn_arg); 607 #endif 608 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); 609 610 void riscv_translate_init(void); 611 G_NORETURN void riscv_raise_exception(CPURISCVState *env, 612 uint32_t exception, uintptr_t pc); 613 614 target_ulong riscv_cpu_get_fflags(CPURISCVState *env); 615 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); 616 617 #define TB_FLAGS_PRIV_MMU_MASK 3 618 #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2) 619 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS 620 #define TB_FLAGS_MSTATUS_VS MSTATUS_VS 621 622 #include "exec/cpu-all.h" 623 624 FIELD(TB_FLAGS, MEM_IDX, 0, 3) 625 FIELD(TB_FLAGS, LMUL, 3, 3) 626 FIELD(TB_FLAGS, SEW, 6, 3) 627 /* Skip MSTATUS_VS (0x600) bits */ 628 FIELD(TB_FLAGS, VL_EQ_VLMAX, 11, 1) 629 FIELD(TB_FLAGS, VILL, 12, 1) 630 /* Skip MSTATUS_FS (0x6000) bits */ 631 /* Is a Hypervisor instruction load/store allowed? */ 632 FIELD(TB_FLAGS, HLSX, 15, 1) 633 FIELD(TB_FLAGS, MSTATUS_HS_FS, 16, 2) 634 FIELD(TB_FLAGS, MSTATUS_HS_VS, 18, 2) 635 /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ 636 FIELD(TB_FLAGS, XL, 20, 2) 637 /* If PointerMasking should be applied */ 638 FIELD(TB_FLAGS, PM_MASK_ENABLED, 22, 1) 639 FIELD(TB_FLAGS, PM_BASE_ENABLED, 23, 1) 640 FIELD(TB_FLAGS, VTA, 24, 1) 641 FIELD(TB_FLAGS, VMA, 25, 1) 642 /* Native debug itrigger */ 643 FIELD(TB_FLAGS, ITRIGGER, 26, 1) 644 645 #ifdef TARGET_RISCV32 646 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) 647 #else 648 static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) 649 { 650 return env->misa_mxl; 651 } 652 #endif 653 #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env))) 654 655 static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURISCVState *env) 656 { 657 return &env_archcpu(env)->cfg; 658 } 659 660 #if defined(TARGET_RISCV32) 661 #define cpu_recompute_xl(env) ((void)(env), MXL_RV32) 662 #else 663 static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) 664 { 665 RISCVMXL xl = env->misa_mxl; 666 #if !defined(CONFIG_USER_ONLY) 667 /* 668 * When emulating a 32-bit-only cpu, use RV32. 669 * When emulating a 64-bit cpu, and MXL has been reduced to RV32, 670 * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened 671 * back to RV64 for lower privs. 672 */ 673 if (xl != MXL_RV32) { 674 switch (env->priv) { 675 case PRV_M: 676 break; 677 case PRV_U: 678 xl = get_field(env->mstatus, MSTATUS64_UXL); 679 break; 680 default: /* PRV_S | PRV_H */ 681 xl = get_field(env->mstatus, MSTATUS64_SXL); 682 break; 683 } 684 } 685 #endif 686 return xl; 687 } 688 #endif 689 690 static inline int riscv_cpu_xlen(CPURISCVState *env) 691 { 692 return 16 << env->xl; 693 } 694 695 #ifdef TARGET_RISCV32 696 #define riscv_cpu_sxl(env) ((void)(env), MXL_RV32) 697 #else 698 static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env) 699 { 700 #ifdef CONFIG_USER_ONLY 701 return env->misa_mxl; 702 #else 703 return get_field(env->mstatus, MSTATUS64_SXL); 704 #endif 705 } 706 #endif 707 708 /* 709 * Encode LMUL to lmul as follows: 710 * LMUL vlmul lmul 711 * 1 000 0 712 * 2 001 1 713 * 4 010 2 714 * 8 011 3 715 * - 100 - 716 * 1/8 101 -3 717 * 1/4 110 -2 718 * 1/2 111 -1 719 * 720 * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul) 721 * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8 722 * => VLMAX = vlen >> (1 + 3 - (-3)) 723 * = 256 >> 7 724 * = 2 725 */ 726 static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) 727 { 728 uint8_t sew = FIELD_EX64(vtype, VTYPE, VSEW); 729 int8_t lmul = sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3); 730 return cpu->cfg.vlen >> (sew + 3 - lmul); 731 } 732 733 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 734 target_ulong *cs_base, uint32_t *pflags); 735 736 void riscv_cpu_update_mask(CPURISCVState *env); 737 738 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, 739 target_ulong *ret_value, 740 target_ulong new_value, target_ulong write_mask); 741 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, 742 target_ulong *ret_value, 743 target_ulong new_value, 744 target_ulong write_mask); 745 746 static inline void riscv_csr_write(CPURISCVState *env, int csrno, 747 target_ulong val) 748 { 749 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); 750 } 751 752 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) 753 { 754 target_ulong val = 0; 755 riscv_csrrw(env, csrno, &val, 0, 0); 756 return val; 757 } 758 759 typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, 760 int csrno); 761 typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, 762 target_ulong *ret_value); 763 typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, 764 target_ulong new_value); 765 typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, 766 target_ulong *ret_value, 767 target_ulong new_value, 768 target_ulong write_mask); 769 770 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, 771 Int128 *ret_value, 772 Int128 new_value, Int128 write_mask); 773 774 typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno, 775 Int128 *ret_value); 776 typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int csrno, 777 Int128 new_value); 778 779 typedef struct { 780 const char *name; 781 riscv_csr_predicate_fn predicate; 782 riscv_csr_read_fn read; 783 riscv_csr_write_fn write; 784 riscv_csr_op_fn op; 785 riscv_csr_read128_fn read128; 786 riscv_csr_write128_fn write128; 787 /* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0) */ 788 uint32_t min_priv_ver; 789 } riscv_csr_operations; 790 791 /* CSR function table constants */ 792 enum { 793 CSR_TABLE_SIZE = 0x1000 794 }; 795 796 /** 797 * The event id are encoded based on the encoding specified in the 798 * SBI specification v0.3 799 */ 800 801 enum riscv_pmu_event_idx { 802 RISCV_PMU_EVENT_HW_CPU_CYCLES = 0x01, 803 RISCV_PMU_EVENT_HW_INSTRUCTIONS = 0x02, 804 RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS = 0x10019, 805 RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS = 0x1001B, 806 RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS = 0x10021, 807 }; 808 809 /* CSR function table */ 810 extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; 811 812 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); 813 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); 814 815 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); 816 817 #endif /* RISCV_CPU_H */ 818