1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef RISCV_CPU_H 21 #define RISCV_CPU_H 22 23 #include "hw/core/cpu.h" 24 #include "hw/registerfields.h" 25 #include "exec/cpu-defs.h" 26 #include "qemu/cpu-float.h" 27 #include "qom/object.h" 28 #include "qemu/int128.h" 29 #include "cpu_bits.h" 30 31 #define TCG_GUEST_DEFAULT_MO 0 32 33 /* 34 * RISC-V-specific extra insn start words: 35 * 1: Original instruction opcode 36 */ 37 #define TARGET_INSN_START_EXTRA_WORDS 1 38 39 #define TYPE_RISCV_CPU "riscv-cpu" 40 41 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU 42 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) 43 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU 44 45 #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") 46 #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") 47 #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") 48 #define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128") 49 #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") 50 #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") 51 #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") 52 #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") 53 #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") 54 #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") 55 #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") 56 #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") 57 58 #if defined(TARGET_RISCV32) 59 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 60 #elif defined(TARGET_RISCV64) 61 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 62 #endif 63 64 #define RV(x) ((target_ulong)1 << (x - 'A')) 65 66 #define RVI RV('I') 67 #define RVE RV('E') /* E and I are mutually exclusive */ 68 #define RVM RV('M') 69 #define RVA RV('A') 70 #define RVF RV('F') 71 #define RVD RV('D') 72 #define RVV RV('V') 73 #define RVC RV('C') 74 #define RVS RV('S') 75 #define RVU RV('U') 76 #define RVH RV('H') 77 #define RVJ RV('J') 78 79 /* S extension denotes that Supervisor mode exists, however it is possible 80 to have a core that support S mode but does not have an MMU and there 81 is currently no bit in misa to indicate whether an MMU exists or not 82 so a cpu features bitfield is required, likewise for optional PMP support */ 83 enum { 84 RISCV_FEATURE_MMU, 85 RISCV_FEATURE_PMP, 86 RISCV_FEATURE_EPMP, 87 RISCV_FEATURE_MISA, 88 RISCV_FEATURE_AIA, 89 RISCV_FEATURE_DEBUG 90 }; 91 92 /* Privileged specification version */ 93 enum { 94 PRIV_VERSION_1_10_0 = 0, 95 PRIV_VERSION_1_11_0, 96 PRIV_VERSION_1_12_0, 97 }; 98 99 #define VEXT_VERSION_1_00_0 0x00010000 100 101 enum { 102 TRANSLATE_SUCCESS, 103 TRANSLATE_FAIL, 104 TRANSLATE_PMP_FAIL, 105 TRANSLATE_G_STAGE_FAIL 106 }; 107 108 #define MMU_USER_IDX 3 109 110 #define MAX_RISCV_PMPS (16) 111 112 typedef struct CPUArchState CPURISCVState; 113 114 #if !defined(CONFIG_USER_ONLY) 115 #include "pmp.h" 116 #include "debug.h" 117 #endif 118 119 #define RV_VLEN_MAX 1024 120 #define RV_MAX_MHPMEVENTS 29 121 #define RV_MAX_MHPMCOUNTERS 32 122 123 FIELD(VTYPE, VLMUL, 0, 3) 124 FIELD(VTYPE, VSEW, 3, 3) 125 FIELD(VTYPE, VTA, 6, 1) 126 FIELD(VTYPE, VMA, 7, 1) 127 FIELD(VTYPE, VEDIV, 8, 2) 128 FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) 129 130 struct CPUArchState { 131 target_ulong gpr[32]; 132 target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ 133 uint64_t fpr[32]; /* assume both F and D extensions */ 134 135 /* vector coprocessor state. */ 136 uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); 137 target_ulong vxrm; 138 target_ulong vxsat; 139 target_ulong vl; 140 target_ulong vstart; 141 target_ulong vtype; 142 bool vill; 143 144 target_ulong pc; 145 target_ulong load_res; 146 target_ulong load_val; 147 148 target_ulong frm; 149 150 target_ulong badaddr; 151 target_ulong bins; 152 153 target_ulong guest_phys_fault_addr; 154 155 target_ulong priv_ver; 156 target_ulong bext_ver; 157 target_ulong vext_ver; 158 159 /* RISCVMXL, but uint32_t for vmstate migration */ 160 uint32_t misa_mxl; /* current mxl */ 161 uint32_t misa_mxl_max; /* max mxl for this cpu */ 162 uint32_t misa_ext; /* current extensions */ 163 uint32_t misa_ext_mask; /* max ext for this cpu */ 164 uint32_t xl; /* current xlen */ 165 166 /* 128-bit helpers upper part return value */ 167 target_ulong retxh; 168 169 uint32_t features; 170 171 #ifdef CONFIG_USER_ONLY 172 uint32_t elf_flags; 173 #endif 174 175 #ifndef CONFIG_USER_ONLY 176 target_ulong priv; 177 /* This contains QEMU specific information about the virt state. */ 178 target_ulong virt; 179 target_ulong geilen; 180 target_ulong resetvec; 181 182 target_ulong mhartid; 183 /* 184 * For RV32 this is 32-bit mstatus and 32-bit mstatush. 185 * For RV64 this is a 64-bit mstatus. 186 */ 187 uint64_t mstatus; 188 189 uint64_t mip; 190 /* 191 * MIP contains the software writable version of SEIP ORed with the 192 * external interrupt value. The MIP register is always up-to-date. 193 * To keep track of the current source, we also save booleans of the values 194 * here. 195 */ 196 bool external_seip; 197 bool software_seip; 198 199 uint64_t miclaim; 200 201 uint64_t mie; 202 uint64_t mideleg; 203 204 target_ulong satp; /* since: priv-1.10.0 */ 205 target_ulong stval; 206 target_ulong medeleg; 207 208 target_ulong stvec; 209 target_ulong sepc; 210 target_ulong scause; 211 212 target_ulong mtvec; 213 target_ulong mepc; 214 target_ulong mcause; 215 target_ulong mtval; /* since: priv-1.10.0 */ 216 217 /* Machine and Supervisor interrupt priorities */ 218 uint8_t miprio[64]; 219 uint8_t siprio[64]; 220 221 /* AIA CSRs */ 222 target_ulong miselect; 223 target_ulong siselect; 224 225 /* Hypervisor CSRs */ 226 target_ulong hstatus; 227 target_ulong hedeleg; 228 uint64_t hideleg; 229 target_ulong hcounteren; 230 target_ulong htval; 231 target_ulong htinst; 232 target_ulong hgatp; 233 target_ulong hgeie; 234 target_ulong hgeip; 235 uint64_t htimedelta; 236 237 /* Hypervisor controlled virtual interrupt priorities */ 238 target_ulong hvictl; 239 uint8_t hviprio[64]; 240 241 /* Upper 64-bits of 128-bit CSRs */ 242 uint64_t mscratchh; 243 uint64_t sscratchh; 244 245 /* Virtual CSRs */ 246 /* 247 * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. 248 * For RV64 this is a 64-bit vsstatus. 249 */ 250 uint64_t vsstatus; 251 target_ulong vstvec; 252 target_ulong vsscratch; 253 target_ulong vsepc; 254 target_ulong vscause; 255 target_ulong vstval; 256 target_ulong vsatp; 257 258 /* AIA VS-mode CSRs */ 259 target_ulong vsiselect; 260 261 target_ulong mtval2; 262 target_ulong mtinst; 263 264 /* HS Backup CSRs */ 265 target_ulong stvec_hs; 266 target_ulong sscratch_hs; 267 target_ulong sepc_hs; 268 target_ulong scause_hs; 269 target_ulong stval_hs; 270 target_ulong satp_hs; 271 uint64_t mstatus_hs; 272 273 /* Signals whether the current exception occurred with two-stage address 274 translation active. */ 275 bool two_stage_lookup; 276 277 target_ulong scounteren; 278 target_ulong mcounteren; 279 280 target_ulong mcountinhibit; 281 282 /* PMU counter configured values */ 283 target_ulong mhpmcounter_val[RV_MAX_MHPMCOUNTERS]; 284 285 /* for RV32 */ 286 target_ulong mhpmcounterh_val[RV_MAX_MHPMCOUNTERS]; 287 288 /* PMU event selector configured values */ 289 target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS]; 290 291 target_ulong sscratch; 292 target_ulong mscratch; 293 294 /* temporary htif regs */ 295 uint64_t mfromhost; 296 uint64_t mtohost; 297 uint64_t timecmp; 298 299 /* physical memory protection */ 300 pmp_table_t pmp_state; 301 target_ulong mseccfg; 302 303 /* trigger module */ 304 target_ulong trigger_cur; 305 type2_trigger_t type2_trig[TRIGGER_TYPE2_NUM]; 306 307 /* machine specific rdtime callback */ 308 uint64_t (*rdtime_fn)(void *); 309 void *rdtime_fn_arg; 310 311 /* machine specific AIA ireg read-modify-write callback */ 312 #define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \ 313 ((((__xlen) & 0xff) << 24) | \ 314 (((__vgein) & 0x3f) << 20) | \ 315 (((__virt) & 0x1) << 18) | \ 316 (((__priv) & 0x3) << 16) | \ 317 (__isel & 0xffff)) 318 #define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff) 319 #define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3) 320 #define AIA_IREG_VIRT(__ireg) (((__ireg) >> 18) & 0x1) 321 #define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 20) & 0x3f) 322 #define AIA_IREG_XLEN(__ireg) (((__ireg) >> 24) & 0xff) 323 int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg, 324 target_ulong *val, target_ulong new_val, target_ulong write_mask); 325 void *aia_ireg_rmw_fn_arg[4]; 326 327 /* True if in debugger mode. */ 328 bool debugger; 329 330 /* 331 * CSRs for PointerMasking extension 332 */ 333 target_ulong mmte; 334 target_ulong mpmmask; 335 target_ulong mpmbase; 336 target_ulong spmmask; 337 target_ulong spmbase; 338 target_ulong upmmask; 339 target_ulong upmbase; 340 341 /* CSRs for execution enviornment configuration */ 342 uint64_t menvcfg; 343 target_ulong senvcfg; 344 uint64_t henvcfg; 345 #endif 346 target_ulong cur_pmmask; 347 target_ulong cur_pmbase; 348 349 float_status fp_status; 350 351 /* Fields from here on are preserved across CPU reset. */ 352 QEMUTimer *timer; /* Internal timer */ 353 354 hwaddr kernel_addr; 355 hwaddr fdt_addr; 356 357 /* kvm timer */ 358 bool kvm_timer_dirty; 359 uint64_t kvm_timer_time; 360 uint64_t kvm_timer_compare; 361 uint64_t kvm_timer_state; 362 uint64_t kvm_timer_frequency; 363 }; 364 365 OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) 366 367 /** 368 * RISCVCPUClass: 369 * @parent_realize: The parent class' realize handler. 370 * @parent_reset: The parent class' reset handler. 371 * 372 * A RISCV CPU model. 373 */ 374 struct RISCVCPUClass { 375 /*< private >*/ 376 CPUClass parent_class; 377 /*< public >*/ 378 DeviceRealize parent_realize; 379 DeviceReset parent_reset; 380 }; 381 382 struct RISCVCPUConfig { 383 bool ext_i; 384 bool ext_e; 385 bool ext_g; 386 bool ext_m; 387 bool ext_a; 388 bool ext_f; 389 bool ext_d; 390 bool ext_c; 391 bool ext_s; 392 bool ext_u; 393 bool ext_h; 394 bool ext_j; 395 bool ext_v; 396 bool ext_zba; 397 bool ext_zbb; 398 bool ext_zbc; 399 bool ext_zbkb; 400 bool ext_zbkc; 401 bool ext_zbkx; 402 bool ext_zbs; 403 bool ext_zk; 404 bool ext_zkn; 405 bool ext_zknd; 406 bool ext_zkne; 407 bool ext_zknh; 408 bool ext_zkr; 409 bool ext_zks; 410 bool ext_zksed; 411 bool ext_zksh; 412 bool ext_zkt; 413 bool ext_ifencei; 414 bool ext_icsr; 415 bool ext_svinval; 416 bool ext_svnapot; 417 bool ext_svpbmt; 418 bool ext_zdinx; 419 bool ext_zfh; 420 bool ext_zfhmin; 421 bool ext_zfinx; 422 bool ext_zhinx; 423 bool ext_zhinxmin; 424 bool ext_zve32f; 425 bool ext_zve64f; 426 bool ext_zmmul; 427 bool rvv_ta_all_1s; 428 429 uint32_t mvendorid; 430 uint64_t marchid; 431 uint64_t mimpid; 432 433 /* Vendor-specific custom extensions */ 434 bool ext_XVentanaCondOps; 435 436 uint8_t pmu_num; 437 char *priv_spec; 438 char *user_spec; 439 char *bext_spec; 440 char *vext_spec; 441 uint16_t vlen; 442 uint16_t elen; 443 bool mmu; 444 bool pmp; 445 bool epmp; 446 bool aia; 447 bool debug; 448 uint64_t resetvec; 449 450 bool short_isa_string; 451 }; 452 453 typedef struct RISCVCPUConfig RISCVCPUConfig; 454 455 /** 456 * RISCVCPU: 457 * @env: #CPURISCVState 458 * 459 * A RISCV CPU. 460 */ 461 struct ArchCPU { 462 /*< private >*/ 463 CPUState parent_obj; 464 /*< public >*/ 465 CPUNegativeOffsetState neg; 466 CPURISCVState env; 467 468 char *dyn_csr_xml; 469 char *dyn_vreg_xml; 470 471 /* Configuration Settings */ 472 RISCVCPUConfig cfg; 473 }; 474 475 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) 476 { 477 return (env->misa_ext & ext) != 0; 478 } 479 480 static inline bool riscv_feature(CPURISCVState *env, int feature) 481 { 482 return env->features & (1ULL << feature); 483 } 484 485 static inline void riscv_set_feature(CPURISCVState *env, int feature) 486 { 487 env->features |= (1ULL << feature); 488 } 489 490 #include "cpu_user.h" 491 492 extern const char * const riscv_int_regnames[]; 493 extern const char * const riscv_int_regnamesh[]; 494 extern const char * const riscv_fpr_regnames[]; 495 496 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); 497 void riscv_cpu_do_interrupt(CPUState *cpu); 498 int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 499 int cpuid, void *opaque); 500 int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 501 int cpuid, void *opaque); 502 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 503 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 504 int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero); 505 uint8_t riscv_cpu_default_priority(int irq); 506 uint64_t riscv_cpu_all_pending(CPURISCVState *env); 507 int riscv_cpu_mirq_pending(CPURISCVState *env); 508 int riscv_cpu_sirq_pending(CPURISCVState *env); 509 int riscv_cpu_vsirq_pending(CPURISCVState *env); 510 bool riscv_cpu_fp_enabled(CPURISCVState *env); 511 target_ulong riscv_cpu_get_geilen(CPURISCVState *env); 512 void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); 513 bool riscv_cpu_vector_enabled(CPURISCVState *env); 514 bool riscv_cpu_virt_enabled(CPURISCVState *env); 515 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); 516 bool riscv_cpu_two_stage_lookup(int mmu_idx); 517 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); 518 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 519 G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 520 MMUAccessType access_type, int mmu_idx, 521 uintptr_t retaddr); 522 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 523 MMUAccessType access_type, int mmu_idx, 524 bool probe, uintptr_t retaddr); 525 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 526 vaddr addr, unsigned size, 527 MMUAccessType access_type, 528 int mmu_idx, MemTxAttrs attrs, 529 MemTxResult response, uintptr_t retaddr); 530 char *riscv_isa_string(RISCVCPU *cpu); 531 void riscv_cpu_list(void); 532 533 #define cpu_list riscv_cpu_list 534 #define cpu_mmu_index riscv_cpu_mmu_index 535 536 #ifndef CONFIG_USER_ONLY 537 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); 538 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); 539 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); 540 uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value); 541 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ 542 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), 543 void *arg); 544 void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, 545 int (*rmw_fn)(void *arg, 546 target_ulong reg, 547 target_ulong *val, 548 target_ulong new_val, 549 target_ulong write_mask), 550 void *rmw_fn_arg); 551 #endif 552 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); 553 554 void riscv_translate_init(void); 555 G_NORETURN void riscv_raise_exception(CPURISCVState *env, 556 uint32_t exception, uintptr_t pc); 557 558 target_ulong riscv_cpu_get_fflags(CPURISCVState *env); 559 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); 560 561 #define TB_FLAGS_PRIV_MMU_MASK 3 562 #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2) 563 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS 564 #define TB_FLAGS_MSTATUS_VS MSTATUS_VS 565 566 #include "exec/cpu-all.h" 567 568 FIELD(TB_FLAGS, MEM_IDX, 0, 3) 569 FIELD(TB_FLAGS, LMUL, 3, 3) 570 FIELD(TB_FLAGS, SEW, 6, 3) 571 /* Skip MSTATUS_VS (0x600) bits */ 572 FIELD(TB_FLAGS, VL_EQ_VLMAX, 11, 1) 573 FIELD(TB_FLAGS, VILL, 12, 1) 574 /* Skip MSTATUS_FS (0x6000) bits */ 575 /* Is a Hypervisor instruction load/store allowed? */ 576 FIELD(TB_FLAGS, HLSX, 15, 1) 577 FIELD(TB_FLAGS, MSTATUS_HS_FS, 16, 2) 578 FIELD(TB_FLAGS, MSTATUS_HS_VS, 18, 2) 579 /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ 580 FIELD(TB_FLAGS, XL, 20, 2) 581 /* If PointerMasking should be applied */ 582 FIELD(TB_FLAGS, PM_MASK_ENABLED, 22, 1) 583 FIELD(TB_FLAGS, PM_BASE_ENABLED, 23, 1) 584 FIELD(TB_FLAGS, VTA, 24, 1) 585 586 #ifdef TARGET_RISCV32 587 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) 588 #else 589 static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) 590 { 591 return env->misa_mxl; 592 } 593 #endif 594 #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env))) 595 596 #if defined(TARGET_RISCV32) 597 #define cpu_recompute_xl(env) ((void)(env), MXL_RV32) 598 #else 599 static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) 600 { 601 RISCVMXL xl = env->misa_mxl; 602 #if !defined(CONFIG_USER_ONLY) 603 /* 604 * When emulating a 32-bit-only cpu, use RV32. 605 * When emulating a 64-bit cpu, and MXL has been reduced to RV32, 606 * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened 607 * back to RV64 for lower privs. 608 */ 609 if (xl != MXL_RV32) { 610 switch (env->priv) { 611 case PRV_M: 612 break; 613 case PRV_U: 614 xl = get_field(env->mstatus, MSTATUS64_UXL); 615 break; 616 default: /* PRV_S | PRV_H */ 617 xl = get_field(env->mstatus, MSTATUS64_SXL); 618 break; 619 } 620 } 621 #endif 622 return xl; 623 } 624 #endif 625 626 static inline int riscv_cpu_xlen(CPURISCVState *env) 627 { 628 return 16 << env->xl; 629 } 630 631 #ifdef TARGET_RISCV32 632 #define riscv_cpu_sxl(env) ((void)(env), MXL_RV32) 633 #else 634 static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env) 635 { 636 #ifdef CONFIG_USER_ONLY 637 return env->misa_mxl; 638 #else 639 return get_field(env->mstatus, MSTATUS64_SXL); 640 #endif 641 } 642 #endif 643 644 /* 645 * Encode LMUL to lmul as follows: 646 * LMUL vlmul lmul 647 * 1 000 0 648 * 2 001 1 649 * 4 010 2 650 * 8 011 3 651 * - 100 - 652 * 1/8 101 -3 653 * 1/4 110 -2 654 * 1/2 111 -1 655 * 656 * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul) 657 * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8 658 * => VLMAX = vlen >> (1 + 3 - (-3)) 659 * = 256 >> 7 660 * = 2 661 */ 662 static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) 663 { 664 uint8_t sew = FIELD_EX64(vtype, VTYPE, VSEW); 665 int8_t lmul = sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3); 666 return cpu->cfg.vlen >> (sew + 3 - lmul); 667 } 668 669 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 670 target_ulong *cs_base, uint32_t *pflags); 671 672 void riscv_cpu_update_mask(CPURISCVState *env); 673 674 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, 675 target_ulong *ret_value, 676 target_ulong new_value, target_ulong write_mask); 677 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, 678 target_ulong *ret_value, 679 target_ulong new_value, 680 target_ulong write_mask); 681 682 static inline void riscv_csr_write(CPURISCVState *env, int csrno, 683 target_ulong val) 684 { 685 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); 686 } 687 688 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) 689 { 690 target_ulong val = 0; 691 riscv_csrrw(env, csrno, &val, 0, 0); 692 return val; 693 } 694 695 typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, 696 int csrno); 697 typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, 698 target_ulong *ret_value); 699 typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, 700 target_ulong new_value); 701 typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, 702 target_ulong *ret_value, 703 target_ulong new_value, 704 target_ulong write_mask); 705 706 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, 707 Int128 *ret_value, 708 Int128 new_value, Int128 write_mask); 709 710 typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno, 711 Int128 *ret_value); 712 typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int csrno, 713 Int128 new_value); 714 715 typedef struct { 716 const char *name; 717 riscv_csr_predicate_fn predicate; 718 riscv_csr_read_fn read; 719 riscv_csr_write_fn write; 720 riscv_csr_op_fn op; 721 riscv_csr_read128_fn read128; 722 riscv_csr_write128_fn write128; 723 /* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0) */ 724 uint32_t min_priv_ver; 725 } riscv_csr_operations; 726 727 /* CSR function table constants */ 728 enum { 729 CSR_TABLE_SIZE = 0x1000 730 }; 731 732 /* CSR function table */ 733 extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; 734 735 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); 736 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); 737 738 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); 739 740 #endif /* RISCV_CPU_H */ 741