1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef RISCV_CPU_H 21 #define RISCV_CPU_H 22 23 #include "qemu-common.h" 24 #include "qom/cpu.h" 25 #include "exec/cpu-defs.h" 26 #include "fpu/softfloat.h" 27 28 #define TCG_GUEST_DEFAULT_MO 0 29 30 #define TYPE_RISCV_CPU "riscv-cpu" 31 32 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU 33 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) 34 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU 35 36 #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") 37 #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") 38 #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") 39 #define TYPE_RISCV_CPU_RV32GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9.1") 40 #define TYPE_RISCV_CPU_RV32GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.10.0") 41 #define TYPE_RISCV_CPU_RV32IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv32imacu-nommu") 42 #define TYPE_RISCV_CPU_RV64GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.9.1") 43 #define TYPE_RISCV_CPU_RV64GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.10.0") 44 #define TYPE_RISCV_CPU_RV64IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv64imacu-nommu") 45 #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") 46 #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") 47 #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") 48 #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") 49 50 #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2)) 51 #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2)) 52 53 #if defined(TARGET_RISCV32) 54 #define RVXLEN RV32 55 #elif defined(TARGET_RISCV64) 56 #define RVXLEN RV64 57 #endif 58 59 #define RV(x) ((target_ulong)1 << (x - 'A')) 60 61 #define RVI RV('I') 62 #define RVE RV('E') /* E and I are mutually exclusive */ 63 #define RVM RV('M') 64 #define RVA RV('A') 65 #define RVF RV('F') 66 #define RVD RV('D') 67 #define RVC RV('C') 68 #define RVS RV('S') 69 #define RVU RV('U') 70 71 /* S extension denotes that Supervisor mode exists, however it is possible 72 to have a core that support S mode but does not have an MMU and there 73 is currently no bit in misa to indicate whether an MMU exists or not 74 so a cpu features bitfield is required, likewise for optional PMP support */ 75 enum { 76 RISCV_FEATURE_MMU, 77 RISCV_FEATURE_PMP, 78 RISCV_FEATURE_MISA 79 }; 80 81 #define USER_VERSION_2_02_0 0x00020200 82 #define PRIV_VERSION_1_09_1 0x00010901 83 #define PRIV_VERSION_1_10_0 0x00011000 84 85 #define TRANSLATE_FAIL 1 86 #define TRANSLATE_SUCCESS 0 87 #define MMU_USER_IDX 3 88 89 #define MAX_RISCV_PMPS (16) 90 91 typedef struct CPURISCVState CPURISCVState; 92 93 #include "pmp.h" 94 95 struct CPURISCVState { 96 target_ulong gpr[32]; 97 uint64_t fpr[32]; /* assume both F and D extensions */ 98 target_ulong pc; 99 target_ulong load_res; 100 target_ulong load_val; 101 102 target_ulong frm; 103 104 target_ulong badaddr; 105 106 target_ulong user_ver; 107 target_ulong priv_ver; 108 target_ulong misa; 109 target_ulong misa_mask; 110 111 uint32_t features; 112 113 #ifdef CONFIG_USER_ONLY 114 uint32_t elf_flags; 115 #endif 116 117 #ifndef CONFIG_USER_ONLY 118 target_ulong priv; 119 target_ulong resetvec; 120 121 target_ulong mhartid; 122 target_ulong mstatus; 123 124 /* 125 * CAUTION! Unlike the rest of this struct, mip is accessed asynchonously 126 * by I/O threads. It should be read with atomic_read. It should be updated 127 * using riscv_cpu_update_mip with the iothread mutex held. The iothread 128 * mutex must be held because mip must be consistent with the CPU inturrept 129 * state. riscv_cpu_update_mip calls cpu_interrupt or cpu_reset_interrupt 130 * wuth the invariant that CPU_INTERRUPT_HARD is set iff mip is non-zero. 131 * mip is 32-bits to allow atomic_read on 32-bit hosts. 132 */ 133 uint32_t mip; 134 uint32_t miclaim; 135 136 target_ulong mie; 137 target_ulong mideleg; 138 139 target_ulong sptbr; /* until: priv-1.9.1 */ 140 target_ulong satp; /* since: priv-1.10.0 */ 141 target_ulong sbadaddr; 142 target_ulong mbadaddr; 143 target_ulong medeleg; 144 145 target_ulong stvec; 146 target_ulong sepc; 147 target_ulong scause; 148 149 target_ulong mtvec; 150 target_ulong mepc; 151 target_ulong mcause; 152 target_ulong mtval; /* since: priv-1.10.0 */ 153 154 target_ulong scounteren; 155 target_ulong mcounteren; 156 157 target_ulong sscratch; 158 target_ulong mscratch; 159 160 /* temporary htif regs */ 161 uint64_t mfromhost; 162 uint64_t mtohost; 163 uint64_t timecmp; 164 165 /* physical memory protection */ 166 pmp_table_t pmp_state; 167 168 /* True if in debugger mode. */ 169 bool debugger; 170 #endif 171 172 float_status fp_status; 173 174 /* QEMU */ 175 CPU_COMMON 176 177 /* Fields from here on are preserved across CPU reset. */ 178 QEMUTimer *timer; /* Internal timer */ 179 }; 180 181 #define RISCV_CPU_CLASS(klass) \ 182 OBJECT_CLASS_CHECK(RISCVCPUClass, (klass), TYPE_RISCV_CPU) 183 #define RISCV_CPU(obj) \ 184 OBJECT_CHECK(RISCVCPU, (obj), TYPE_RISCV_CPU) 185 #define RISCV_CPU_GET_CLASS(obj) \ 186 OBJECT_GET_CLASS(RISCVCPUClass, (obj), TYPE_RISCV_CPU) 187 188 /** 189 * RISCVCPUClass: 190 * @parent_realize: The parent class' realize handler. 191 * @parent_reset: The parent class' reset handler. 192 * 193 * A RISCV CPU model. 194 */ 195 typedef struct RISCVCPUClass { 196 /*< private >*/ 197 CPUClass parent_class; 198 /*< public >*/ 199 DeviceRealize parent_realize; 200 void (*parent_reset)(CPUState *cpu); 201 } RISCVCPUClass; 202 203 /** 204 * RISCVCPU: 205 * @env: #CPURISCVState 206 * 207 * A RISCV CPU. 208 */ 209 typedef struct RISCVCPU { 210 /*< private >*/ 211 CPUState parent_obj; 212 /*< public >*/ 213 CPUNegativeOffsetState neg; 214 CPURISCVState env; 215 216 /* Configuration Settings */ 217 struct { 218 char *priv_spec; 219 char *user_spec; 220 bool mmu; 221 bool pmp; 222 } cfg; 223 } RISCVCPU; 224 225 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) 226 { 227 return (env->misa & ext) != 0; 228 } 229 230 static inline bool riscv_feature(CPURISCVState *env, int feature) 231 { 232 return env->features & (1ULL << feature); 233 } 234 235 #include "cpu_user.h" 236 #include "cpu_bits.h" 237 238 extern const char * const riscv_int_regnames[]; 239 extern const char * const riscv_fpr_regnames[]; 240 extern const char * const riscv_excp_names[]; 241 extern const char * const riscv_intr_names[]; 242 243 void riscv_cpu_do_interrupt(CPUState *cpu); 244 int riscv_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 245 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 246 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); 247 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); 248 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 249 void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 250 MMUAccessType access_type, int mmu_idx, 251 uintptr_t retaddr); 252 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 253 MMUAccessType access_type, int mmu_idx, 254 bool probe, uintptr_t retaddr); 255 char *riscv_isa_string(RISCVCPU *cpu); 256 void riscv_cpu_list(void); 257 258 #define cpu_signal_handler riscv_cpu_signal_handler 259 #define cpu_list riscv_cpu_list 260 #define cpu_mmu_index riscv_cpu_mmu_index 261 262 #ifndef CONFIG_USER_ONLY 263 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts); 264 uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value); 265 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ 266 #endif 267 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); 268 269 void riscv_translate_init(void); 270 int riscv_cpu_signal_handler(int host_signum, void *pinfo, void *puc); 271 void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env, 272 uint32_t exception, uintptr_t pc); 273 274 target_ulong riscv_cpu_get_fflags(CPURISCVState *env); 275 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); 276 277 #define TB_FLAGS_MMU_MASK 3 278 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS 279 280 static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 281 target_ulong *cs_base, uint32_t *flags) 282 { 283 *pc = env->pc; 284 *cs_base = 0; 285 #ifdef CONFIG_USER_ONLY 286 *flags = TB_FLAGS_MSTATUS_FS; 287 #else 288 *flags = cpu_mmu_index(env, 0) | (env->mstatus & MSTATUS_FS); 289 #endif 290 } 291 292 int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, 293 target_ulong new_value, target_ulong write_mask); 294 int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value, 295 target_ulong new_value, target_ulong write_mask); 296 297 static inline void riscv_csr_write(CPURISCVState *env, int csrno, 298 target_ulong val) 299 { 300 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); 301 } 302 303 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) 304 { 305 target_ulong val = 0; 306 riscv_csrrw(env, csrno, &val, 0, 0); 307 return val; 308 } 309 310 typedef int (*riscv_csr_predicate_fn)(CPURISCVState *env, int csrno); 311 typedef int (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, 312 target_ulong *ret_value); 313 typedef int (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, 314 target_ulong new_value); 315 typedef int (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, 316 target_ulong *ret_value, target_ulong new_value, target_ulong write_mask); 317 318 typedef struct { 319 riscv_csr_predicate_fn predicate; 320 riscv_csr_read_fn read; 321 riscv_csr_write_fn write; 322 riscv_csr_op_fn op; 323 } riscv_csr_operations; 324 325 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); 326 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); 327 328 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); 329 330 typedef CPURISCVState CPUArchState; 331 typedef RISCVCPU ArchCPU; 332 333 #include "exec/cpu-all.h" 334 335 #endif /* RISCV_CPU_H */ 336