1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef RISCV_CPU_H 21 #define RISCV_CPU_H 22 23 #include "hw/core/cpu.h" 24 #include "hw/registerfields.h" 25 #include "exec/cpu-defs.h" 26 #include "fpu/softfloat-types.h" 27 #include "qom/object.h" 28 29 #define TCG_GUEST_DEFAULT_MO 0 30 31 #define TYPE_RISCV_CPU "riscv-cpu" 32 33 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU 34 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) 35 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU 36 37 #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") 38 #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") 39 #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") 40 #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") 41 #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") 42 #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") 43 #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") 44 #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") 45 #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") 46 #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") 47 48 #if defined(TARGET_RISCV32) 49 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 50 #elif defined(TARGET_RISCV64) 51 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 52 #endif 53 54 #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2)) 55 #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2)) 56 57 #if defined(TARGET_RISCV32) 58 #define RVXLEN RV32 59 #elif defined(TARGET_RISCV64) 60 #define RVXLEN RV64 61 #endif 62 63 #define RV(x) ((target_ulong)1 << (x - 'A')) 64 65 #define RVI RV('I') 66 #define RVE RV('E') /* E and I are mutually exclusive */ 67 #define RVM RV('M') 68 #define RVA RV('A') 69 #define RVF RV('F') 70 #define RVD RV('D') 71 #define RVV RV('V') 72 #define RVC RV('C') 73 #define RVS RV('S') 74 #define RVU RV('U') 75 #define RVH RV('H') 76 77 /* S extension denotes that Supervisor mode exists, however it is possible 78 to have a core that support S mode but does not have an MMU and there 79 is currently no bit in misa to indicate whether an MMU exists or not 80 so a cpu features bitfield is required, likewise for optional PMP support */ 81 enum { 82 RISCV_FEATURE_MMU, 83 RISCV_FEATURE_PMP, 84 RISCV_FEATURE_EPMP, 85 RISCV_FEATURE_MISA 86 }; 87 88 #define PRIV_VERSION_1_10_0 0x00011000 89 #define PRIV_VERSION_1_11_0 0x00011100 90 91 #define VEXT_VERSION_0_07_1 0x00000701 92 93 enum { 94 TRANSLATE_SUCCESS, 95 TRANSLATE_FAIL, 96 TRANSLATE_PMP_FAIL, 97 TRANSLATE_G_STAGE_FAIL 98 }; 99 100 #define MMU_USER_IDX 3 101 102 #define MAX_RISCV_PMPS (16) 103 104 typedef struct CPURISCVState CPURISCVState; 105 106 #include "pmp.h" 107 108 #define RV_VLEN_MAX 256 109 110 FIELD(VTYPE, VLMUL, 0, 2) 111 FIELD(VTYPE, VSEW, 2, 3) 112 FIELD(VTYPE, VEDIV, 5, 2) 113 FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 9) 114 FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1) 115 116 struct CPURISCVState { 117 target_ulong gpr[32]; 118 uint64_t fpr[32]; /* assume both F and D extensions */ 119 120 /* vector coprocessor state. */ 121 uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); 122 target_ulong vxrm; 123 target_ulong vxsat; 124 target_ulong vl; 125 target_ulong vstart; 126 target_ulong vtype; 127 128 target_ulong pc; 129 target_ulong load_res; 130 target_ulong load_val; 131 132 target_ulong frm; 133 134 target_ulong badaddr; 135 target_ulong guest_phys_fault_addr; 136 137 target_ulong priv_ver; 138 target_ulong vext_ver; 139 target_ulong misa; 140 target_ulong misa_mask; 141 142 uint32_t features; 143 144 #ifdef CONFIG_USER_ONLY 145 uint32_t elf_flags; 146 #endif 147 148 #ifndef CONFIG_USER_ONLY 149 target_ulong priv; 150 /* This contains QEMU specific information about the virt state. */ 151 target_ulong virt; 152 target_ulong resetvec; 153 154 target_ulong mhartid; 155 /* 156 * For RV32 this is 32-bit mstatus and 32-bit mstatush. 157 * For RV64 this is a 64-bit mstatus. 158 */ 159 uint64_t mstatus; 160 161 target_ulong mip; 162 163 uint32_t miclaim; 164 165 target_ulong mie; 166 target_ulong mideleg; 167 168 target_ulong satp; /* since: priv-1.10.0 */ 169 target_ulong stval; 170 target_ulong medeleg; 171 172 target_ulong stvec; 173 target_ulong sepc; 174 target_ulong scause; 175 176 target_ulong mtvec; 177 target_ulong mepc; 178 target_ulong mcause; 179 target_ulong mtval; /* since: priv-1.10.0 */ 180 181 /* Hypervisor CSRs */ 182 target_ulong hstatus; 183 target_ulong hedeleg; 184 target_ulong hideleg; 185 target_ulong hcounteren; 186 target_ulong htval; 187 target_ulong htinst; 188 target_ulong hgatp; 189 uint64_t htimedelta; 190 191 /* Virtual CSRs */ 192 /* 193 * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. 194 * For RV64 this is a 64-bit vsstatus. 195 */ 196 uint64_t vsstatus; 197 target_ulong vstvec; 198 target_ulong vsscratch; 199 target_ulong vsepc; 200 target_ulong vscause; 201 target_ulong vstval; 202 target_ulong vsatp; 203 204 target_ulong mtval2; 205 target_ulong mtinst; 206 207 /* HS Backup CSRs */ 208 target_ulong stvec_hs; 209 target_ulong sscratch_hs; 210 target_ulong sepc_hs; 211 target_ulong scause_hs; 212 target_ulong stval_hs; 213 target_ulong satp_hs; 214 uint64_t mstatus_hs; 215 216 /* Signals whether the current exception occurred with two-stage address 217 translation active. */ 218 bool two_stage_lookup; 219 220 target_ulong scounteren; 221 target_ulong mcounteren; 222 223 target_ulong sscratch; 224 target_ulong mscratch; 225 226 /* temporary htif regs */ 227 uint64_t mfromhost; 228 uint64_t mtohost; 229 uint64_t timecmp; 230 231 /* physical memory protection */ 232 pmp_table_t pmp_state; 233 target_ulong mseccfg; 234 235 /* machine specific rdtime callback */ 236 uint64_t (*rdtime_fn)(uint32_t); 237 uint32_t rdtime_fn_arg; 238 239 /* True if in debugger mode. */ 240 bool debugger; 241 #endif 242 243 float_status fp_status; 244 245 /* Fields from here on are preserved across CPU reset. */ 246 QEMUTimer *timer; /* Internal timer */ 247 }; 248 249 OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass, 250 RISCV_CPU) 251 252 /** 253 * RISCVCPUClass: 254 * @parent_realize: The parent class' realize handler. 255 * @parent_reset: The parent class' reset handler. 256 * 257 * A RISCV CPU model. 258 */ 259 struct RISCVCPUClass { 260 /*< private >*/ 261 CPUClass parent_class; 262 /*< public >*/ 263 DeviceRealize parent_realize; 264 DeviceReset parent_reset; 265 }; 266 267 /** 268 * RISCVCPU: 269 * @env: #CPURISCVState 270 * 271 * A RISCV CPU. 272 */ 273 struct RISCVCPU { 274 /*< private >*/ 275 CPUState parent_obj; 276 /*< public >*/ 277 CPUNegativeOffsetState neg; 278 CPURISCVState env; 279 280 char *dyn_csr_xml; 281 282 /* Configuration Settings */ 283 struct { 284 bool ext_i; 285 bool ext_e; 286 bool ext_g; 287 bool ext_m; 288 bool ext_a; 289 bool ext_f; 290 bool ext_d; 291 bool ext_c; 292 bool ext_s; 293 bool ext_u; 294 bool ext_h; 295 bool ext_v; 296 bool ext_counters; 297 bool ext_ifencei; 298 bool ext_icsr; 299 300 char *priv_spec; 301 char *user_spec; 302 char *vext_spec; 303 uint16_t vlen; 304 uint16_t elen; 305 bool mmu; 306 bool pmp; 307 bool epmp; 308 uint64_t resetvec; 309 } cfg; 310 }; 311 312 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) 313 { 314 return (env->misa & ext) != 0; 315 } 316 317 static inline bool riscv_feature(CPURISCVState *env, int feature) 318 { 319 return env->features & (1ULL << feature); 320 } 321 322 #include "cpu_user.h" 323 #include "cpu_bits.h" 324 325 extern const char * const riscv_int_regnames[]; 326 extern const char * const riscv_fpr_regnames[]; 327 extern const char * const riscv_excp_names[]; 328 extern const char * const riscv_intr_names[]; 329 330 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); 331 void riscv_cpu_do_interrupt(CPUState *cpu); 332 int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 333 int cpuid, void *opaque); 334 int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 335 int cpuid, void *opaque); 336 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 337 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 338 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); 339 bool riscv_cpu_fp_enabled(CPURISCVState *env); 340 bool riscv_cpu_virt_enabled(CPURISCVState *env); 341 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); 342 bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env); 343 void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable); 344 bool riscv_cpu_two_stage_lookup(int mmu_idx); 345 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); 346 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 347 void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 348 MMUAccessType access_type, int mmu_idx, 349 uintptr_t retaddr); 350 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 351 MMUAccessType access_type, int mmu_idx, 352 bool probe, uintptr_t retaddr); 353 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 354 vaddr addr, unsigned size, 355 MMUAccessType access_type, 356 int mmu_idx, MemTxAttrs attrs, 357 MemTxResult response, uintptr_t retaddr); 358 char *riscv_isa_string(RISCVCPU *cpu); 359 void riscv_cpu_list(void); 360 361 #define cpu_signal_handler riscv_cpu_signal_handler 362 #define cpu_list riscv_cpu_list 363 #define cpu_mmu_index riscv_cpu_mmu_index 364 365 #ifndef CONFIG_USER_ONLY 366 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); 367 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts); 368 uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value); 369 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ 370 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t), 371 uint32_t arg); 372 #endif 373 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); 374 375 void riscv_translate_init(void); 376 int riscv_cpu_signal_handler(int host_signum, void *pinfo, void *puc); 377 void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env, 378 uint32_t exception, uintptr_t pc); 379 380 target_ulong riscv_cpu_get_fflags(CPURISCVState *env); 381 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); 382 383 #define TB_FLAGS_MMU_MASK 7 384 #define TB_FLAGS_PRIV_MMU_MASK 3 385 #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2) 386 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS 387 388 typedef CPURISCVState CPUArchState; 389 typedef RISCVCPU ArchCPU; 390 #include "exec/cpu-all.h" 391 392 FIELD(TB_FLAGS, VL_EQ_VLMAX, 2, 1) 393 FIELD(TB_FLAGS, LMUL, 3, 2) 394 FIELD(TB_FLAGS, SEW, 5, 3) 395 FIELD(TB_FLAGS, VILL, 8, 1) 396 /* Is a Hypervisor instruction load/store allowed? */ 397 FIELD(TB_FLAGS, HLSX, 9, 1) 398 399 bool riscv_cpu_is_32bit(CPURISCVState *env); 400 401 /* 402 * A simplification for VLMAX 403 * = (1 << LMUL) * VLEN / (8 * (1 << SEW)) 404 * = (VLEN << LMUL) / (8 << SEW) 405 * = (VLEN << LMUL) >> (SEW + 3) 406 * = VLEN >> (SEW + 3 - LMUL) 407 */ 408 static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) 409 { 410 uint8_t sew, lmul; 411 412 sew = FIELD_EX64(vtype, VTYPE, VSEW); 413 lmul = FIELD_EX64(vtype, VTYPE, VLMUL); 414 return cpu->cfg.vlen >> (sew + 3 - lmul); 415 } 416 417 static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 418 target_ulong *cs_base, uint32_t *pflags) 419 { 420 uint32_t flags = 0; 421 422 *pc = env->pc; 423 *cs_base = 0; 424 425 if (riscv_has_ext(env, RVV)) { 426 uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype); 427 bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl); 428 flags = FIELD_DP32(flags, TB_FLAGS, VILL, 429 FIELD_EX64(env->vtype, VTYPE, VILL)); 430 flags = FIELD_DP32(flags, TB_FLAGS, SEW, 431 FIELD_EX64(env->vtype, VTYPE, VSEW)); 432 flags = FIELD_DP32(flags, TB_FLAGS, LMUL, 433 FIELD_EX64(env->vtype, VTYPE, VLMUL)); 434 flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); 435 } else { 436 flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1); 437 } 438 439 #ifdef CONFIG_USER_ONLY 440 flags |= TB_FLAGS_MSTATUS_FS; 441 #else 442 flags |= cpu_mmu_index(env, 0); 443 if (riscv_cpu_fp_enabled(env)) { 444 flags |= env->mstatus & MSTATUS_FS; 445 } 446 447 if (riscv_has_ext(env, RVH)) { 448 if (env->priv == PRV_M || 449 (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || 450 (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) && 451 get_field(env->hstatus, HSTATUS_HU))) { 452 flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1); 453 } 454 } 455 #endif 456 457 *pflags = flags; 458 } 459 460 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, 461 target_ulong *ret_value, 462 target_ulong new_value, target_ulong write_mask); 463 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, 464 target_ulong *ret_value, 465 target_ulong new_value, 466 target_ulong write_mask); 467 468 static inline void riscv_csr_write(CPURISCVState *env, int csrno, 469 target_ulong val) 470 { 471 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); 472 } 473 474 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) 475 { 476 target_ulong val = 0; 477 riscv_csrrw(env, csrno, &val, 0, 0); 478 return val; 479 } 480 481 typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, 482 int csrno); 483 typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, 484 target_ulong *ret_value); 485 typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, 486 target_ulong new_value); 487 typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, 488 target_ulong *ret_value, 489 target_ulong new_value, 490 target_ulong write_mask); 491 492 typedef struct { 493 const char *name; 494 riscv_csr_predicate_fn predicate; 495 riscv_csr_read_fn read; 496 riscv_csr_write_fn write; 497 riscv_csr_op_fn op; 498 } riscv_csr_operations; 499 500 /* CSR function table constants */ 501 enum { 502 CSR_TABLE_SIZE = 0x1000 503 }; 504 505 /* CSR function table */ 506 extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; 507 508 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); 509 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); 510 511 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); 512 513 #endif /* RISCV_CPU_H */ 514