1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef RISCV_CPU_H 21 #define RISCV_CPU_H 22 23 #include "hw/core/cpu.h" 24 #include "hw/registerfields.h" 25 #include "exec/cpu-defs.h" 26 #include "qemu/cpu-float.h" 27 #include "qom/object.h" 28 #include "qemu/int128.h" 29 #include "cpu_bits.h" 30 31 #define TCG_GUEST_DEFAULT_MO 0 32 33 /* 34 * RISC-V-specific extra insn start words: 35 * 1: Original instruction opcode 36 */ 37 #define TARGET_INSN_START_EXTRA_WORDS 1 38 39 #define TYPE_RISCV_CPU "riscv-cpu" 40 41 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU 42 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) 43 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU 44 45 #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") 46 #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") 47 #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") 48 #define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128") 49 #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") 50 #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") 51 #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") 52 #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") 53 #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") 54 #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") 55 #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") 56 #define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906") 57 #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") 58 59 #if defined(TARGET_RISCV32) 60 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 61 #elif defined(TARGET_RISCV64) 62 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 63 #endif 64 65 #define RV(x) ((target_ulong)1 << (x - 'A')) 66 67 /* 68 * Consider updating register_cpu_props() when adding 69 * new MISA bits here. 70 */ 71 #define RVI RV('I') 72 #define RVE RV('E') /* E and I are mutually exclusive */ 73 #define RVM RV('M') 74 #define RVA RV('A') 75 #define RVF RV('F') 76 #define RVD RV('D') 77 #define RVV RV('V') 78 #define RVC RV('C') 79 #define RVS RV('S') 80 #define RVU RV('U') 81 #define RVH RV('H') 82 #define RVJ RV('J') 83 84 /* S extension denotes that Supervisor mode exists, however it is possible 85 to have a core that support S mode but does not have an MMU and there 86 is currently no bit in misa to indicate whether an MMU exists or not 87 so a cpu features bitfield is required, likewise for optional PMP support */ 88 enum { 89 RISCV_FEATURE_MMU, 90 RISCV_FEATURE_PMP, 91 RISCV_FEATURE_EPMP, 92 RISCV_FEATURE_DEBUG 93 }; 94 95 /* Privileged specification version */ 96 enum { 97 PRIV_VERSION_1_10_0 = 0, 98 PRIV_VERSION_1_11_0, 99 PRIV_VERSION_1_12_0, 100 }; 101 102 #define VEXT_VERSION_1_00_0 0x00010000 103 104 enum { 105 TRANSLATE_SUCCESS, 106 TRANSLATE_FAIL, 107 TRANSLATE_PMP_FAIL, 108 TRANSLATE_G_STAGE_FAIL 109 }; 110 111 #define MMU_USER_IDX 3 112 113 #define MAX_RISCV_PMPS (16) 114 115 typedef struct CPUArchState CPURISCVState; 116 117 #if !defined(CONFIG_USER_ONLY) 118 #include "pmp.h" 119 #include "debug.h" 120 #endif 121 122 #define RV_VLEN_MAX 1024 123 #define RV_MAX_MHPMEVENTS 32 124 #define RV_MAX_MHPMCOUNTERS 32 125 126 FIELD(VTYPE, VLMUL, 0, 3) 127 FIELD(VTYPE, VSEW, 3, 3) 128 FIELD(VTYPE, VTA, 6, 1) 129 FIELD(VTYPE, VMA, 7, 1) 130 FIELD(VTYPE, VEDIV, 8, 2) 131 FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) 132 133 typedef struct PMUCTRState { 134 /* Current value of a counter */ 135 target_ulong mhpmcounter_val; 136 /* Current value of a counter in RV32*/ 137 target_ulong mhpmcounterh_val; 138 /* Snapshot values of counter */ 139 target_ulong mhpmcounter_prev; 140 /* Snapshort value of a counter in RV32 */ 141 target_ulong mhpmcounterh_prev; 142 bool started; 143 /* Value beyond UINT32_MAX/UINT64_MAX before overflow interrupt trigger */ 144 target_ulong irq_overflow_left; 145 } PMUCTRState; 146 147 struct CPUArchState { 148 target_ulong gpr[32]; 149 target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ 150 151 /* vector coprocessor state. */ 152 uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); 153 target_ulong vxrm; 154 target_ulong vxsat; 155 target_ulong vl; 156 target_ulong vstart; 157 target_ulong vtype; 158 bool vill; 159 160 target_ulong pc; 161 target_ulong load_res; 162 target_ulong load_val; 163 164 /* Floating-Point state */ 165 uint64_t fpr[32]; /* assume both F and D extensions */ 166 target_ulong frm; 167 float_status fp_status; 168 169 target_ulong badaddr; 170 target_ulong bins; 171 172 target_ulong guest_phys_fault_addr; 173 174 target_ulong priv_ver; 175 target_ulong bext_ver; 176 target_ulong vext_ver; 177 178 /* RISCVMXL, but uint32_t for vmstate migration */ 179 uint32_t misa_mxl; /* current mxl */ 180 uint32_t misa_mxl_max; /* max mxl for this cpu */ 181 uint32_t misa_ext; /* current extensions */ 182 uint32_t misa_ext_mask; /* max ext for this cpu */ 183 uint32_t xl; /* current xlen */ 184 185 /* 128-bit helpers upper part return value */ 186 target_ulong retxh; 187 188 uint32_t features; 189 190 #ifdef CONFIG_USER_ONLY 191 uint32_t elf_flags; 192 #endif 193 194 #ifndef CONFIG_USER_ONLY 195 target_ulong priv; 196 /* This contains QEMU specific information about the virt state. */ 197 target_ulong virt; 198 target_ulong geilen; 199 uint64_t resetvec; 200 201 target_ulong mhartid; 202 /* 203 * For RV32 this is 32-bit mstatus and 32-bit mstatush. 204 * For RV64 this is a 64-bit mstatus. 205 */ 206 uint64_t mstatus; 207 208 uint64_t mip; 209 /* 210 * MIP contains the software writable version of SEIP ORed with the 211 * external interrupt value. The MIP register is always up-to-date. 212 * To keep track of the current source, we also save booleans of the values 213 * here. 214 */ 215 bool external_seip; 216 bool software_seip; 217 218 uint64_t miclaim; 219 220 uint64_t mie; 221 uint64_t mideleg; 222 223 target_ulong satp; /* since: priv-1.10.0 */ 224 target_ulong stval; 225 target_ulong medeleg; 226 227 target_ulong stvec; 228 target_ulong sepc; 229 target_ulong scause; 230 231 target_ulong mtvec; 232 target_ulong mepc; 233 target_ulong mcause; 234 target_ulong mtval; /* since: priv-1.10.0 */ 235 236 /* Machine and Supervisor interrupt priorities */ 237 uint8_t miprio[64]; 238 uint8_t siprio[64]; 239 240 /* AIA CSRs */ 241 target_ulong miselect; 242 target_ulong siselect; 243 244 /* Hypervisor CSRs */ 245 target_ulong hstatus; 246 target_ulong hedeleg; 247 uint64_t hideleg; 248 target_ulong hcounteren; 249 target_ulong htval; 250 target_ulong htinst; 251 target_ulong hgatp; 252 target_ulong hgeie; 253 target_ulong hgeip; 254 uint64_t htimedelta; 255 256 /* Hypervisor controlled virtual interrupt priorities */ 257 target_ulong hvictl; 258 uint8_t hviprio[64]; 259 260 /* Upper 64-bits of 128-bit CSRs */ 261 uint64_t mscratchh; 262 uint64_t sscratchh; 263 264 /* Virtual CSRs */ 265 /* 266 * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. 267 * For RV64 this is a 64-bit vsstatus. 268 */ 269 uint64_t vsstatus; 270 target_ulong vstvec; 271 target_ulong vsscratch; 272 target_ulong vsepc; 273 target_ulong vscause; 274 target_ulong vstval; 275 target_ulong vsatp; 276 277 /* AIA VS-mode CSRs */ 278 target_ulong vsiselect; 279 280 target_ulong mtval2; 281 target_ulong mtinst; 282 283 /* HS Backup CSRs */ 284 target_ulong stvec_hs; 285 target_ulong sscratch_hs; 286 target_ulong sepc_hs; 287 target_ulong scause_hs; 288 target_ulong stval_hs; 289 target_ulong satp_hs; 290 uint64_t mstatus_hs; 291 292 /* Signals whether the current exception occurred with two-stage address 293 translation active. */ 294 bool two_stage_lookup; 295 /* 296 * Signals whether the current exception occurred while doing two-stage 297 * address translation for the VS-stage page table walk. 298 */ 299 bool two_stage_indirect_lookup; 300 301 target_ulong scounteren; 302 target_ulong mcounteren; 303 304 target_ulong mcountinhibit; 305 306 /* PMU counter state */ 307 PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS]; 308 309 /* PMU event selector configured values. First three are unused*/ 310 target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS]; 311 312 /* PMU event selector configured values for RV32*/ 313 target_ulong mhpmeventh_val[RV_MAX_MHPMEVENTS]; 314 315 target_ulong sscratch; 316 target_ulong mscratch; 317 318 /* Sstc CSRs */ 319 uint64_t stimecmp; 320 321 uint64_t vstimecmp; 322 323 /* physical memory protection */ 324 pmp_table_t pmp_state; 325 target_ulong mseccfg; 326 327 /* trigger module */ 328 target_ulong trigger_cur; 329 target_ulong tdata1[RV_MAX_TRIGGERS]; 330 target_ulong tdata2[RV_MAX_TRIGGERS]; 331 target_ulong tdata3[RV_MAX_TRIGGERS]; 332 struct CPUBreakpoint *cpu_breakpoint[RV_MAX_TRIGGERS]; 333 struct CPUWatchpoint *cpu_watchpoint[RV_MAX_TRIGGERS]; 334 QEMUTimer *itrigger_timer[RV_MAX_TRIGGERS]; 335 int64_t last_icount; 336 bool itrigger_enabled; 337 338 /* machine specific rdtime callback */ 339 uint64_t (*rdtime_fn)(void *); 340 void *rdtime_fn_arg; 341 342 /* machine specific AIA ireg read-modify-write callback */ 343 #define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \ 344 ((((__xlen) & 0xff) << 24) | \ 345 (((__vgein) & 0x3f) << 20) | \ 346 (((__virt) & 0x1) << 18) | \ 347 (((__priv) & 0x3) << 16) | \ 348 (__isel & 0xffff)) 349 #define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff) 350 #define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3) 351 #define AIA_IREG_VIRT(__ireg) (((__ireg) >> 18) & 0x1) 352 #define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 20) & 0x3f) 353 #define AIA_IREG_XLEN(__ireg) (((__ireg) >> 24) & 0xff) 354 int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg, 355 target_ulong *val, target_ulong new_val, target_ulong write_mask); 356 void *aia_ireg_rmw_fn_arg[4]; 357 358 /* True if in debugger mode. */ 359 bool debugger; 360 361 /* 362 * CSRs for PointerMasking extension 363 */ 364 target_ulong mmte; 365 target_ulong mpmmask; 366 target_ulong mpmbase; 367 target_ulong spmmask; 368 target_ulong spmbase; 369 target_ulong upmmask; 370 target_ulong upmbase; 371 372 /* CSRs for execution enviornment configuration */ 373 uint64_t menvcfg; 374 uint64_t mstateen[SMSTATEEN_MAX_COUNT]; 375 uint64_t hstateen[SMSTATEEN_MAX_COUNT]; 376 uint64_t sstateen[SMSTATEEN_MAX_COUNT]; 377 target_ulong senvcfg; 378 uint64_t henvcfg; 379 #endif 380 target_ulong cur_pmmask; 381 target_ulong cur_pmbase; 382 383 /* Fields from here on are preserved across CPU reset. */ 384 QEMUTimer *stimer; /* Internal timer for S-mode interrupt */ 385 QEMUTimer *vstimer; /* Internal timer for VS-mode interrupt */ 386 bool vstime_irq; 387 388 hwaddr kernel_addr; 389 hwaddr fdt_addr; 390 391 /* kvm timer */ 392 bool kvm_timer_dirty; 393 uint64_t kvm_timer_time; 394 uint64_t kvm_timer_compare; 395 uint64_t kvm_timer_state; 396 uint64_t kvm_timer_frequency; 397 }; 398 399 OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) 400 401 /** 402 * RISCVCPUClass: 403 * @parent_realize: The parent class' realize handler. 404 * @parent_phases: The parent class' reset phase handlers. 405 * 406 * A RISCV CPU model. 407 */ 408 struct RISCVCPUClass { 409 /*< private >*/ 410 CPUClass parent_class; 411 /*< public >*/ 412 DeviceRealize parent_realize; 413 ResettablePhases parent_phases; 414 }; 415 416 struct RISCVCPUConfig { 417 bool ext_i; 418 bool ext_e; 419 bool ext_g; 420 bool ext_m; 421 bool ext_a; 422 bool ext_f; 423 bool ext_d; 424 bool ext_c; 425 bool ext_s; 426 bool ext_u; 427 bool ext_h; 428 bool ext_j; 429 bool ext_v; 430 bool ext_zba; 431 bool ext_zbb; 432 bool ext_zbc; 433 bool ext_zbkb; 434 bool ext_zbkc; 435 bool ext_zbkx; 436 bool ext_zbs; 437 bool ext_zk; 438 bool ext_zkn; 439 bool ext_zknd; 440 bool ext_zkne; 441 bool ext_zknh; 442 bool ext_zkr; 443 bool ext_zks; 444 bool ext_zksed; 445 bool ext_zksh; 446 bool ext_zkt; 447 bool ext_ifencei; 448 bool ext_icsr; 449 bool ext_zihintpause; 450 bool ext_smstateen; 451 bool ext_sstc; 452 bool ext_svinval; 453 bool ext_svnapot; 454 bool ext_svpbmt; 455 bool ext_zdinx; 456 bool ext_zawrs; 457 bool ext_zfh; 458 bool ext_zfhmin; 459 bool ext_zfinx; 460 bool ext_zhinx; 461 bool ext_zhinxmin; 462 bool ext_zve32f; 463 bool ext_zve64f; 464 bool ext_zmmul; 465 bool ext_smaia; 466 bool ext_ssaia; 467 bool ext_sscofpmf; 468 bool rvv_ta_all_1s; 469 bool rvv_ma_all_1s; 470 471 uint32_t mvendorid; 472 uint64_t marchid; 473 uint64_t mimpid; 474 475 /* Vendor-specific custom extensions */ 476 bool ext_xtheadba; 477 bool ext_xtheadbb; 478 bool ext_xtheadbs; 479 bool ext_xtheadcmo; 480 bool ext_xtheadcondmov; 481 bool ext_xtheadfmemidx; 482 bool ext_xtheadfmv; 483 bool ext_xtheadmac; 484 bool ext_xtheadmemidx; 485 bool ext_xtheadmempair; 486 bool ext_xtheadsync; 487 bool ext_XVentanaCondOps; 488 489 uint8_t pmu_num; 490 char *priv_spec; 491 char *user_spec; 492 char *bext_spec; 493 char *vext_spec; 494 uint16_t vlen; 495 uint16_t elen; 496 bool mmu; 497 bool pmp; 498 bool epmp; 499 bool debug; 500 bool misa_w; 501 502 bool short_isa_string; 503 }; 504 505 typedef struct RISCVCPUConfig RISCVCPUConfig; 506 507 /** 508 * RISCVCPU: 509 * @env: #CPURISCVState 510 * 511 * A RISCV CPU. 512 */ 513 struct ArchCPU { 514 /*< private >*/ 515 CPUState parent_obj; 516 /*< public >*/ 517 CPUNegativeOffsetState neg; 518 CPURISCVState env; 519 520 char *dyn_csr_xml; 521 char *dyn_vreg_xml; 522 523 /* Configuration Settings */ 524 RISCVCPUConfig cfg; 525 526 QEMUTimer *pmu_timer; 527 /* A bitmask of Available programmable counters */ 528 uint32_t pmu_avail_ctrs; 529 /* Mapping of events to counters */ 530 GHashTable *pmu_event_ctr_map; 531 }; 532 533 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) 534 { 535 return (env->misa_ext & ext) != 0; 536 } 537 538 static inline bool riscv_feature(CPURISCVState *env, int feature) 539 { 540 return env->features & (1ULL << feature); 541 } 542 543 static inline void riscv_set_feature(CPURISCVState *env, int feature) 544 { 545 env->features |= (1ULL << feature); 546 } 547 548 #include "cpu_user.h" 549 550 extern const char * const riscv_int_regnames[]; 551 extern const char * const riscv_int_regnamesh[]; 552 extern const char * const riscv_fpr_regnames[]; 553 554 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); 555 void riscv_cpu_do_interrupt(CPUState *cpu); 556 int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 557 int cpuid, DumpState *s); 558 int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 559 int cpuid, DumpState *s); 560 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 561 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 562 int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero); 563 uint8_t riscv_cpu_default_priority(int irq); 564 uint64_t riscv_cpu_all_pending(CPURISCVState *env); 565 int riscv_cpu_mirq_pending(CPURISCVState *env); 566 int riscv_cpu_sirq_pending(CPURISCVState *env); 567 int riscv_cpu_vsirq_pending(CPURISCVState *env); 568 bool riscv_cpu_fp_enabled(CPURISCVState *env); 569 target_ulong riscv_cpu_get_geilen(CPURISCVState *env); 570 void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); 571 bool riscv_cpu_vector_enabled(CPURISCVState *env); 572 bool riscv_cpu_virt_enabled(CPURISCVState *env); 573 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); 574 bool riscv_cpu_two_stage_lookup(int mmu_idx); 575 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); 576 G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 577 MMUAccessType access_type, int mmu_idx, 578 uintptr_t retaddr); 579 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 580 MMUAccessType access_type, int mmu_idx, 581 bool probe, uintptr_t retaddr); 582 char *riscv_isa_string(RISCVCPU *cpu); 583 void riscv_cpu_list(void); 584 585 #define cpu_list riscv_cpu_list 586 #define cpu_mmu_index riscv_cpu_mmu_index 587 588 #ifndef CONFIG_USER_ONLY 589 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 590 vaddr addr, unsigned size, 591 MMUAccessType access_type, 592 int mmu_idx, MemTxAttrs attrs, 593 MemTxResult response, uintptr_t retaddr); 594 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 595 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); 596 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); 597 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); 598 uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value); 599 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ 600 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), 601 void *arg); 602 void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, 603 int (*rmw_fn)(void *arg, 604 target_ulong reg, 605 target_ulong *val, 606 target_ulong new_val, 607 target_ulong write_mask), 608 void *rmw_fn_arg); 609 #endif 610 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); 611 612 void riscv_translate_init(void); 613 G_NORETURN void riscv_raise_exception(CPURISCVState *env, 614 uint32_t exception, uintptr_t pc); 615 616 target_ulong riscv_cpu_get_fflags(CPURISCVState *env); 617 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); 618 619 #define TB_FLAGS_PRIV_MMU_MASK 3 620 #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2) 621 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS 622 #define TB_FLAGS_MSTATUS_VS MSTATUS_VS 623 624 #include "exec/cpu-all.h" 625 626 FIELD(TB_FLAGS, MEM_IDX, 0, 3) 627 FIELD(TB_FLAGS, LMUL, 3, 3) 628 FIELD(TB_FLAGS, SEW, 6, 3) 629 /* Skip MSTATUS_VS (0x600) bits */ 630 FIELD(TB_FLAGS, VL_EQ_VLMAX, 11, 1) 631 FIELD(TB_FLAGS, VILL, 12, 1) 632 /* Skip MSTATUS_FS (0x6000) bits */ 633 /* Is a Hypervisor instruction load/store allowed? */ 634 FIELD(TB_FLAGS, HLSX, 15, 1) 635 FIELD(TB_FLAGS, MSTATUS_HS_FS, 16, 2) 636 FIELD(TB_FLAGS, MSTATUS_HS_VS, 18, 2) 637 /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ 638 FIELD(TB_FLAGS, XL, 20, 2) 639 /* If PointerMasking should be applied */ 640 FIELD(TB_FLAGS, PM_MASK_ENABLED, 22, 1) 641 FIELD(TB_FLAGS, PM_BASE_ENABLED, 23, 1) 642 FIELD(TB_FLAGS, VTA, 24, 1) 643 FIELD(TB_FLAGS, VMA, 25, 1) 644 /* Native debug itrigger */ 645 FIELD(TB_FLAGS, ITRIGGER, 26, 1) 646 647 #ifdef TARGET_RISCV32 648 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) 649 #else 650 static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) 651 { 652 return env->misa_mxl; 653 } 654 #endif 655 #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env))) 656 657 static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURISCVState *env) 658 { 659 return &env_archcpu(env)->cfg; 660 } 661 662 #if defined(TARGET_RISCV32) 663 #define cpu_recompute_xl(env) ((void)(env), MXL_RV32) 664 #else 665 static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) 666 { 667 RISCVMXL xl = env->misa_mxl; 668 #if !defined(CONFIG_USER_ONLY) 669 /* 670 * When emulating a 32-bit-only cpu, use RV32. 671 * When emulating a 64-bit cpu, and MXL has been reduced to RV32, 672 * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened 673 * back to RV64 for lower privs. 674 */ 675 if (xl != MXL_RV32) { 676 switch (env->priv) { 677 case PRV_M: 678 break; 679 case PRV_U: 680 xl = get_field(env->mstatus, MSTATUS64_UXL); 681 break; 682 default: /* PRV_S | PRV_H */ 683 xl = get_field(env->mstatus, MSTATUS64_SXL); 684 break; 685 } 686 } 687 #endif 688 return xl; 689 } 690 #endif 691 692 static inline int riscv_cpu_xlen(CPURISCVState *env) 693 { 694 return 16 << env->xl; 695 } 696 697 #ifdef TARGET_RISCV32 698 #define riscv_cpu_sxl(env) ((void)(env), MXL_RV32) 699 #else 700 static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env) 701 { 702 #ifdef CONFIG_USER_ONLY 703 return env->misa_mxl; 704 #else 705 return get_field(env->mstatus, MSTATUS64_SXL); 706 #endif 707 } 708 #endif 709 710 /* 711 * Encode LMUL to lmul as follows: 712 * LMUL vlmul lmul 713 * 1 000 0 714 * 2 001 1 715 * 4 010 2 716 * 8 011 3 717 * - 100 - 718 * 1/8 101 -3 719 * 1/4 110 -2 720 * 1/2 111 -1 721 * 722 * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul) 723 * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8 724 * => VLMAX = vlen >> (1 + 3 - (-3)) 725 * = 256 >> 7 726 * = 2 727 */ 728 static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) 729 { 730 uint8_t sew = FIELD_EX64(vtype, VTYPE, VSEW); 731 int8_t lmul = sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3); 732 return cpu->cfg.vlen >> (sew + 3 - lmul); 733 } 734 735 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 736 target_ulong *cs_base, uint32_t *pflags); 737 738 void riscv_cpu_update_mask(CPURISCVState *env); 739 740 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, 741 target_ulong *ret_value, 742 target_ulong new_value, target_ulong write_mask); 743 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, 744 target_ulong *ret_value, 745 target_ulong new_value, 746 target_ulong write_mask); 747 748 static inline void riscv_csr_write(CPURISCVState *env, int csrno, 749 target_ulong val) 750 { 751 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); 752 } 753 754 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) 755 { 756 target_ulong val = 0; 757 riscv_csrrw(env, csrno, &val, 0, 0); 758 return val; 759 } 760 761 typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, 762 int csrno); 763 typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, 764 target_ulong *ret_value); 765 typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, 766 target_ulong new_value); 767 typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, 768 target_ulong *ret_value, 769 target_ulong new_value, 770 target_ulong write_mask); 771 772 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, 773 Int128 *ret_value, 774 Int128 new_value, Int128 write_mask); 775 776 typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno, 777 Int128 *ret_value); 778 typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int csrno, 779 Int128 new_value); 780 781 typedef struct { 782 const char *name; 783 riscv_csr_predicate_fn predicate; 784 riscv_csr_read_fn read; 785 riscv_csr_write_fn write; 786 riscv_csr_op_fn op; 787 riscv_csr_read128_fn read128; 788 riscv_csr_write128_fn write128; 789 /* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0) */ 790 uint32_t min_priv_ver; 791 } riscv_csr_operations; 792 793 /* CSR function table constants */ 794 enum { 795 CSR_TABLE_SIZE = 0x1000 796 }; 797 798 /** 799 * The event id are encoded based on the encoding specified in the 800 * SBI specification v0.3 801 */ 802 803 enum riscv_pmu_event_idx { 804 RISCV_PMU_EVENT_HW_CPU_CYCLES = 0x01, 805 RISCV_PMU_EVENT_HW_INSTRUCTIONS = 0x02, 806 RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS = 0x10019, 807 RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS = 0x1001B, 808 RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS = 0x10021, 809 }; 810 811 /* CSR function table */ 812 extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; 813 814 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); 815 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); 816 817 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); 818 819 #endif /* RISCV_CPU_H */ 820