1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef RISCV_CPU_H 21 #define RISCV_CPU_H 22 23 #include "hw/core/cpu.h" 24 #include "hw/registerfields.h" 25 #include "exec/cpu-defs.h" 26 #include "qemu/cpu-float.h" 27 #include "qom/object.h" 28 #include "qemu/int128.h" 29 #include "cpu_bits.h" 30 #include "qapi/qapi-types-common.h" 31 32 #define TCG_GUEST_DEFAULT_MO 0 33 34 /* 35 * RISC-V-specific extra insn start words: 36 * 1: Original instruction opcode 37 */ 38 #define TARGET_INSN_START_EXTRA_WORDS 1 39 40 #define TYPE_RISCV_CPU "riscv-cpu" 41 42 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU 43 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) 44 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU 45 46 #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") 47 #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") 48 #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") 49 #define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128") 50 #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") 51 #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") 52 #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") 53 #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") 54 #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") 55 #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") 56 #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") 57 #define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906") 58 #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") 59 60 #if defined(TARGET_RISCV32) 61 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 62 #elif defined(TARGET_RISCV64) 63 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 64 #endif 65 66 #define RV(x) ((target_ulong)1 << (x - 'A')) 67 68 /* 69 * Consider updating register_cpu_props() when adding 70 * new MISA bits here. 71 */ 72 #define RVI RV('I') 73 #define RVE RV('E') /* E and I are mutually exclusive */ 74 #define RVM RV('M') 75 #define RVA RV('A') 76 #define RVF RV('F') 77 #define RVD RV('D') 78 #define RVV RV('V') 79 #define RVC RV('C') 80 #define RVS RV('S') 81 #define RVU RV('U') 82 #define RVH RV('H') 83 #define RVJ RV('J') 84 #define RVG RV('G') 85 86 87 /* Privileged specification version */ 88 enum { 89 PRIV_VERSION_1_10_0 = 0, 90 PRIV_VERSION_1_11_0, 91 PRIV_VERSION_1_12_0, 92 }; 93 94 #define VEXT_VERSION_1_00_0 0x00010000 95 96 enum { 97 TRANSLATE_SUCCESS, 98 TRANSLATE_FAIL, 99 TRANSLATE_PMP_FAIL, 100 TRANSLATE_G_STAGE_FAIL 101 }; 102 103 #define MMU_USER_IDX 3 104 105 #define MAX_RISCV_PMPS (16) 106 107 typedef struct CPUArchState CPURISCVState; 108 109 #if !defined(CONFIG_USER_ONLY) 110 #include "pmp.h" 111 #include "debug.h" 112 #endif 113 114 #define RV_VLEN_MAX 1024 115 #define RV_MAX_MHPMEVENTS 32 116 #define RV_MAX_MHPMCOUNTERS 32 117 118 FIELD(VTYPE, VLMUL, 0, 3) 119 FIELD(VTYPE, VSEW, 3, 3) 120 FIELD(VTYPE, VTA, 6, 1) 121 FIELD(VTYPE, VMA, 7, 1) 122 FIELD(VTYPE, VEDIV, 8, 2) 123 FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) 124 125 typedef struct PMUCTRState { 126 /* Current value of a counter */ 127 target_ulong mhpmcounter_val; 128 /* Current value of a counter in RV32 */ 129 target_ulong mhpmcounterh_val; 130 /* Snapshot values of counter */ 131 target_ulong mhpmcounter_prev; 132 /* Snapshort value of a counter in RV32 */ 133 target_ulong mhpmcounterh_prev; 134 bool started; 135 /* Value beyond UINT32_MAX/UINT64_MAX before overflow interrupt trigger */ 136 target_ulong irq_overflow_left; 137 } PMUCTRState; 138 139 struct CPUArchState { 140 target_ulong gpr[32]; 141 target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ 142 143 /* vector coprocessor state. */ 144 uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); 145 target_ulong vxrm; 146 target_ulong vxsat; 147 target_ulong vl; 148 target_ulong vstart; 149 target_ulong vtype; 150 bool vill; 151 152 target_ulong pc; 153 target_ulong load_res; 154 target_ulong load_val; 155 156 /* Floating-Point state */ 157 uint64_t fpr[32]; /* assume both F and D extensions */ 158 target_ulong frm; 159 float_status fp_status; 160 161 target_ulong badaddr; 162 target_ulong bins; 163 164 target_ulong guest_phys_fault_addr; 165 166 target_ulong priv_ver; 167 target_ulong bext_ver; 168 target_ulong vext_ver; 169 170 /* RISCVMXL, but uint32_t for vmstate migration */ 171 uint32_t misa_mxl; /* current mxl */ 172 uint32_t misa_mxl_max; /* max mxl for this cpu */ 173 uint32_t misa_ext; /* current extensions */ 174 uint32_t misa_ext_mask; /* max ext for this cpu */ 175 uint32_t xl; /* current xlen */ 176 177 /* 128-bit helpers upper part return value */ 178 target_ulong retxh; 179 180 target_ulong jvt; 181 182 #ifdef CONFIG_USER_ONLY 183 uint32_t elf_flags; 184 #endif 185 186 #ifndef CONFIG_USER_ONLY 187 target_ulong priv; 188 /* This contains QEMU specific information about the virt state. */ 189 bool virt_enabled; 190 target_ulong geilen; 191 uint64_t resetvec; 192 193 target_ulong mhartid; 194 /* 195 * For RV32 this is 32-bit mstatus and 32-bit mstatush. 196 * For RV64 this is a 64-bit mstatus. 197 */ 198 uint64_t mstatus; 199 200 uint64_t mip; 201 /* 202 * MIP contains the software writable version of SEIP ORed with the 203 * external interrupt value. The MIP register is always up-to-date. 204 * To keep track of the current source, we also save booleans of the values 205 * here. 206 */ 207 bool external_seip; 208 bool software_seip; 209 210 uint64_t miclaim; 211 212 uint64_t mie; 213 uint64_t mideleg; 214 215 target_ulong satp; /* since: priv-1.10.0 */ 216 target_ulong stval; 217 target_ulong medeleg; 218 219 target_ulong stvec; 220 target_ulong sepc; 221 target_ulong scause; 222 223 target_ulong mtvec; 224 target_ulong mepc; 225 target_ulong mcause; 226 target_ulong mtval; /* since: priv-1.10.0 */ 227 228 /* Machine and Supervisor interrupt priorities */ 229 uint8_t miprio[64]; 230 uint8_t siprio[64]; 231 232 /* AIA CSRs */ 233 target_ulong miselect; 234 target_ulong siselect; 235 236 /* Hypervisor CSRs */ 237 target_ulong hstatus; 238 target_ulong hedeleg; 239 uint64_t hideleg; 240 target_ulong hcounteren; 241 target_ulong htval; 242 target_ulong htinst; 243 target_ulong hgatp; 244 target_ulong hgeie; 245 target_ulong hgeip; 246 uint64_t htimedelta; 247 248 /* Hypervisor controlled virtual interrupt priorities */ 249 target_ulong hvictl; 250 uint8_t hviprio[64]; 251 252 /* Upper 64-bits of 128-bit CSRs */ 253 uint64_t mscratchh; 254 uint64_t sscratchh; 255 256 /* Virtual CSRs */ 257 /* 258 * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. 259 * For RV64 this is a 64-bit vsstatus. 260 */ 261 uint64_t vsstatus; 262 target_ulong vstvec; 263 target_ulong vsscratch; 264 target_ulong vsepc; 265 target_ulong vscause; 266 target_ulong vstval; 267 target_ulong vsatp; 268 269 /* AIA VS-mode CSRs */ 270 target_ulong vsiselect; 271 272 target_ulong mtval2; 273 target_ulong mtinst; 274 275 /* HS Backup CSRs */ 276 target_ulong stvec_hs; 277 target_ulong sscratch_hs; 278 target_ulong sepc_hs; 279 target_ulong scause_hs; 280 target_ulong stval_hs; 281 target_ulong satp_hs; 282 uint64_t mstatus_hs; 283 284 /* 285 * Signals whether the current exception occurred with two-stage address 286 * translation active. 287 */ 288 bool two_stage_lookup; 289 /* 290 * Signals whether the current exception occurred while doing two-stage 291 * address translation for the VS-stage page table walk. 292 */ 293 bool two_stage_indirect_lookup; 294 295 target_ulong scounteren; 296 target_ulong mcounteren; 297 298 target_ulong mcountinhibit; 299 300 /* PMU counter state */ 301 PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS]; 302 303 /* PMU event selector configured values. First three are unused */ 304 target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS]; 305 306 /* PMU event selector configured values for RV32 */ 307 target_ulong mhpmeventh_val[RV_MAX_MHPMEVENTS]; 308 309 target_ulong sscratch; 310 target_ulong mscratch; 311 312 /* Sstc CSRs */ 313 uint64_t stimecmp; 314 315 uint64_t vstimecmp; 316 317 /* physical memory protection */ 318 pmp_table_t pmp_state; 319 target_ulong mseccfg; 320 321 /* trigger module */ 322 target_ulong trigger_cur; 323 target_ulong tdata1[RV_MAX_TRIGGERS]; 324 target_ulong tdata2[RV_MAX_TRIGGERS]; 325 target_ulong tdata3[RV_MAX_TRIGGERS]; 326 struct CPUBreakpoint *cpu_breakpoint[RV_MAX_TRIGGERS]; 327 struct CPUWatchpoint *cpu_watchpoint[RV_MAX_TRIGGERS]; 328 QEMUTimer *itrigger_timer[RV_MAX_TRIGGERS]; 329 int64_t last_icount; 330 bool itrigger_enabled; 331 332 /* machine specific rdtime callback */ 333 uint64_t (*rdtime_fn)(void *); 334 void *rdtime_fn_arg; 335 336 /* machine specific AIA ireg read-modify-write callback */ 337 #define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \ 338 ((((__xlen) & 0xff) << 24) | \ 339 (((__vgein) & 0x3f) << 20) | \ 340 (((__virt) & 0x1) << 18) | \ 341 (((__priv) & 0x3) << 16) | \ 342 (__isel & 0xffff)) 343 #define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff) 344 #define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3) 345 #define AIA_IREG_VIRT(__ireg) (((__ireg) >> 18) & 0x1) 346 #define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 20) & 0x3f) 347 #define AIA_IREG_XLEN(__ireg) (((__ireg) >> 24) & 0xff) 348 int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg, 349 target_ulong *val, target_ulong new_val, target_ulong write_mask); 350 void *aia_ireg_rmw_fn_arg[4]; 351 352 /* True if in debugger mode. */ 353 bool debugger; 354 355 /* 356 * CSRs for PointerMasking extension 357 */ 358 target_ulong mmte; 359 target_ulong mpmmask; 360 target_ulong mpmbase; 361 target_ulong spmmask; 362 target_ulong spmbase; 363 target_ulong upmmask; 364 target_ulong upmbase; 365 366 /* CSRs for execution enviornment configuration */ 367 uint64_t menvcfg; 368 uint64_t mstateen[SMSTATEEN_MAX_COUNT]; 369 uint64_t hstateen[SMSTATEEN_MAX_COUNT]; 370 uint64_t sstateen[SMSTATEEN_MAX_COUNT]; 371 target_ulong senvcfg; 372 uint64_t henvcfg; 373 #endif 374 target_ulong cur_pmmask; 375 target_ulong cur_pmbase; 376 377 /* Fields from here on are preserved across CPU reset. */ 378 QEMUTimer *stimer; /* Internal timer for S-mode interrupt */ 379 QEMUTimer *vstimer; /* Internal timer for VS-mode interrupt */ 380 bool vstime_irq; 381 382 hwaddr kernel_addr; 383 hwaddr fdt_addr; 384 385 /* kvm timer */ 386 bool kvm_timer_dirty; 387 uint64_t kvm_timer_time; 388 uint64_t kvm_timer_compare; 389 uint64_t kvm_timer_state; 390 uint64_t kvm_timer_frequency; 391 }; 392 393 OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) 394 395 /* 396 * RISCVCPUClass: 397 * @parent_realize: The parent class' realize handler. 398 * @parent_phases: The parent class' reset phase handlers. 399 * 400 * A RISCV CPU model. 401 */ 402 struct RISCVCPUClass { 403 /* < private > */ 404 CPUClass parent_class; 405 /* < public > */ 406 DeviceRealize parent_realize; 407 ResettablePhases parent_phases; 408 }; 409 410 /* 411 * map is a 16-bit bitmap: the most significant set bit in map is the maximum 412 * satp mode that is supported. It may be chosen by the user and must respect 413 * what qemu implements (valid_1_10_32/64) and what the hw is capable of 414 * (supported bitmap below). 415 * 416 * init is a 16-bit bitmap used to make sure the user selected a correct 417 * configuration as per the specification. 418 * 419 * supported is a 16-bit bitmap used to reflect the hw capabilities. 420 */ 421 typedef struct { 422 uint16_t map, init, supported; 423 } RISCVSATPMap; 424 425 struct RISCVCPUConfig { 426 bool ext_zba; 427 bool ext_zbb; 428 bool ext_zbc; 429 bool ext_zbkb; 430 bool ext_zbkc; 431 bool ext_zbkx; 432 bool ext_zbs; 433 bool ext_zca; 434 bool ext_zcb; 435 bool ext_zcd; 436 bool ext_zce; 437 bool ext_zcf; 438 bool ext_zcmp; 439 bool ext_zcmt; 440 bool ext_zk; 441 bool ext_zkn; 442 bool ext_zknd; 443 bool ext_zkne; 444 bool ext_zknh; 445 bool ext_zkr; 446 bool ext_zks; 447 bool ext_zksed; 448 bool ext_zksh; 449 bool ext_zkt; 450 bool ext_ifencei; 451 bool ext_icsr; 452 bool ext_icbom; 453 bool ext_icboz; 454 bool ext_zicond; 455 bool ext_zihintpause; 456 bool ext_smstateen; 457 bool ext_sstc; 458 bool ext_svadu; 459 bool ext_svinval; 460 bool ext_svnapot; 461 bool ext_svpbmt; 462 bool ext_zdinx; 463 bool ext_zawrs; 464 bool ext_zfh; 465 bool ext_zfhmin; 466 bool ext_zfinx; 467 bool ext_zhinx; 468 bool ext_zhinxmin; 469 bool ext_zve32f; 470 bool ext_zve64f; 471 bool ext_zve64d; 472 bool ext_zmmul; 473 bool ext_zvfh; 474 bool ext_zvfhmin; 475 bool ext_smaia; 476 bool ext_ssaia; 477 bool ext_sscofpmf; 478 bool rvv_ta_all_1s; 479 bool rvv_ma_all_1s; 480 481 uint32_t mvendorid; 482 uint64_t marchid; 483 uint64_t mimpid; 484 485 /* Vendor-specific custom extensions */ 486 bool ext_xtheadba; 487 bool ext_xtheadbb; 488 bool ext_xtheadbs; 489 bool ext_xtheadcmo; 490 bool ext_xtheadcondmov; 491 bool ext_xtheadfmemidx; 492 bool ext_xtheadfmv; 493 bool ext_xtheadmac; 494 bool ext_xtheadmemidx; 495 bool ext_xtheadmempair; 496 bool ext_xtheadsync; 497 bool ext_XVentanaCondOps; 498 499 uint8_t pmu_num; 500 char *priv_spec; 501 char *user_spec; 502 char *bext_spec; 503 char *vext_spec; 504 uint16_t vlen; 505 uint16_t elen; 506 uint16_t cbom_blocksize; 507 uint16_t cboz_blocksize; 508 bool mmu; 509 bool pmp; 510 bool epmp; 511 bool debug; 512 bool misa_w; 513 514 bool short_isa_string; 515 516 #ifndef CONFIG_USER_ONLY 517 RISCVSATPMap satp_mode; 518 #endif 519 }; 520 521 typedef struct RISCVCPUConfig RISCVCPUConfig; 522 523 /* 524 * RISCVCPU: 525 * @env: #CPURISCVState 526 * 527 * A RISCV CPU. 528 */ 529 struct ArchCPU { 530 /* < private > */ 531 CPUState parent_obj; 532 /* < public > */ 533 CPUNegativeOffsetState neg; 534 CPURISCVState env; 535 536 char *dyn_csr_xml; 537 char *dyn_vreg_xml; 538 539 /* Configuration Settings */ 540 RISCVCPUConfig cfg; 541 542 QEMUTimer *pmu_timer; 543 /* A bitmask of Available programmable counters */ 544 uint32_t pmu_avail_ctrs; 545 /* Mapping of events to counters */ 546 GHashTable *pmu_event_ctr_map; 547 }; 548 549 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) 550 { 551 return (env->misa_ext & ext) != 0; 552 } 553 554 #include "cpu_user.h" 555 556 extern const char * const riscv_int_regnames[]; 557 extern const char * const riscv_int_regnamesh[]; 558 extern const char * const riscv_fpr_regnames[]; 559 560 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); 561 void riscv_cpu_do_interrupt(CPUState *cpu); 562 int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 563 int cpuid, DumpState *s); 564 int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 565 int cpuid, DumpState *s); 566 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 567 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 568 int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero); 569 uint8_t riscv_cpu_default_priority(int irq); 570 uint64_t riscv_cpu_all_pending(CPURISCVState *env); 571 int riscv_cpu_mirq_pending(CPURISCVState *env); 572 int riscv_cpu_sirq_pending(CPURISCVState *env); 573 int riscv_cpu_vsirq_pending(CPURISCVState *env); 574 bool riscv_cpu_fp_enabled(CPURISCVState *env); 575 target_ulong riscv_cpu_get_geilen(CPURISCVState *env); 576 void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); 577 bool riscv_cpu_vector_enabled(CPURISCVState *env); 578 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); 579 bool riscv_cpu_two_stage_lookup(int mmu_idx); 580 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); 581 G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 582 MMUAccessType access_type, 583 int mmu_idx, uintptr_t retaddr); 584 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 585 MMUAccessType access_type, int mmu_idx, 586 bool probe, uintptr_t retaddr); 587 char *riscv_isa_string(RISCVCPU *cpu); 588 void riscv_cpu_list(void); 589 590 #define cpu_list riscv_cpu_list 591 #define cpu_mmu_index riscv_cpu_mmu_index 592 593 #ifndef CONFIG_USER_ONLY 594 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 595 vaddr addr, unsigned size, 596 MMUAccessType access_type, 597 int mmu_idx, MemTxAttrs attrs, 598 MemTxResult response, uintptr_t retaddr); 599 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 600 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); 601 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); 602 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); 603 uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask, 604 uint64_t value); 605 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ 606 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), 607 void *arg); 608 void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, 609 int (*rmw_fn)(void *arg, 610 target_ulong reg, 611 target_ulong *val, 612 target_ulong new_val, 613 target_ulong write_mask), 614 void *rmw_fn_arg); 615 616 RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit); 617 #endif 618 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); 619 620 void riscv_translate_init(void); 621 G_NORETURN void riscv_raise_exception(CPURISCVState *env, 622 uint32_t exception, uintptr_t pc); 623 624 target_ulong riscv_cpu_get_fflags(CPURISCVState *env); 625 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); 626 627 #define TB_FLAGS_PRIV_MMU_MASK 3 628 #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2) 629 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS 630 #define TB_FLAGS_MSTATUS_VS MSTATUS_VS 631 632 #include "exec/cpu-all.h" 633 634 FIELD(TB_FLAGS, MEM_IDX, 0, 3) 635 FIELD(TB_FLAGS, LMUL, 3, 3) 636 FIELD(TB_FLAGS, SEW, 6, 3) 637 /* Skip MSTATUS_VS (0x600) bits */ 638 FIELD(TB_FLAGS, VL_EQ_VLMAX, 11, 1) 639 FIELD(TB_FLAGS, VILL, 12, 1) 640 /* Skip MSTATUS_FS (0x6000) bits */ 641 /* Is a Hypervisor instruction load/store allowed? */ 642 FIELD(TB_FLAGS, HLSX, 15, 1) 643 FIELD(TB_FLAGS, MSTATUS_HS_FS, 16, 2) 644 FIELD(TB_FLAGS, MSTATUS_HS_VS, 18, 2) 645 /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ 646 FIELD(TB_FLAGS, XL, 20, 2) 647 /* If PointerMasking should be applied */ 648 FIELD(TB_FLAGS, PM_MASK_ENABLED, 22, 1) 649 FIELD(TB_FLAGS, PM_BASE_ENABLED, 23, 1) 650 FIELD(TB_FLAGS, VTA, 24, 1) 651 FIELD(TB_FLAGS, VMA, 25, 1) 652 /* Native debug itrigger */ 653 FIELD(TB_FLAGS, ITRIGGER, 26, 1) 654 655 #ifdef TARGET_RISCV32 656 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) 657 #else 658 static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) 659 { 660 return env->misa_mxl; 661 } 662 #endif 663 #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env))) 664 665 static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURISCVState *env) 666 { 667 return &env_archcpu(env)->cfg; 668 } 669 670 #if defined(TARGET_RISCV32) 671 #define cpu_recompute_xl(env) ((void)(env), MXL_RV32) 672 #else 673 static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) 674 { 675 RISCVMXL xl = env->misa_mxl; 676 #if !defined(CONFIG_USER_ONLY) 677 /* 678 * When emulating a 32-bit-only cpu, use RV32. 679 * When emulating a 64-bit cpu, and MXL has been reduced to RV32, 680 * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened 681 * back to RV64 for lower privs. 682 */ 683 if (xl != MXL_RV32) { 684 switch (env->priv) { 685 case PRV_M: 686 break; 687 case PRV_U: 688 xl = get_field(env->mstatus, MSTATUS64_UXL); 689 break; 690 default: /* PRV_S | PRV_H */ 691 xl = get_field(env->mstatus, MSTATUS64_SXL); 692 break; 693 } 694 } 695 #endif 696 return xl; 697 } 698 #endif 699 700 static inline int riscv_cpu_xlen(CPURISCVState *env) 701 { 702 return 16 << env->xl; 703 } 704 705 #ifdef TARGET_RISCV32 706 #define riscv_cpu_sxl(env) ((void)(env), MXL_RV32) 707 #else 708 static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env) 709 { 710 #ifdef CONFIG_USER_ONLY 711 return env->misa_mxl; 712 #else 713 return get_field(env->mstatus, MSTATUS64_SXL); 714 #endif 715 } 716 #endif 717 718 /* 719 * Encode LMUL to lmul as follows: 720 * LMUL vlmul lmul 721 * 1 000 0 722 * 2 001 1 723 * 4 010 2 724 * 8 011 3 725 * - 100 - 726 * 1/8 101 -3 727 * 1/4 110 -2 728 * 1/2 111 -1 729 * 730 * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul) 731 * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8 732 * => VLMAX = vlen >> (1 + 3 - (-3)) 733 * = 256 >> 7 734 * = 2 735 */ 736 static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) 737 { 738 uint8_t sew = FIELD_EX64(vtype, VTYPE, VSEW); 739 int8_t lmul = sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3); 740 return cpu->cfg.vlen >> (sew + 3 - lmul); 741 } 742 743 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 744 target_ulong *cs_base, uint32_t *pflags); 745 746 void riscv_cpu_update_mask(CPURISCVState *env); 747 748 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, 749 target_ulong *ret_value, 750 target_ulong new_value, target_ulong write_mask); 751 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, 752 target_ulong *ret_value, 753 target_ulong new_value, 754 target_ulong write_mask); 755 756 static inline void riscv_csr_write(CPURISCVState *env, int csrno, 757 target_ulong val) 758 { 759 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); 760 } 761 762 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) 763 { 764 target_ulong val = 0; 765 riscv_csrrw(env, csrno, &val, 0, 0); 766 return val; 767 } 768 769 typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, 770 int csrno); 771 typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, 772 target_ulong *ret_value); 773 typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, 774 target_ulong new_value); 775 typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, 776 target_ulong *ret_value, 777 target_ulong new_value, 778 target_ulong write_mask); 779 780 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, 781 Int128 *ret_value, 782 Int128 new_value, Int128 write_mask); 783 784 typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno, 785 Int128 *ret_value); 786 typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int csrno, 787 Int128 new_value); 788 789 typedef struct { 790 const char *name; 791 riscv_csr_predicate_fn predicate; 792 riscv_csr_read_fn read; 793 riscv_csr_write_fn write; 794 riscv_csr_op_fn op; 795 riscv_csr_read128_fn read128; 796 riscv_csr_write128_fn write128; 797 /* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0) */ 798 uint32_t min_priv_ver; 799 } riscv_csr_operations; 800 801 /* CSR function table constants */ 802 enum { 803 CSR_TABLE_SIZE = 0x1000 804 }; 805 806 /* 807 * The event id are encoded based on the encoding specified in the 808 * SBI specification v0.3 809 */ 810 811 enum riscv_pmu_event_idx { 812 RISCV_PMU_EVENT_HW_CPU_CYCLES = 0x01, 813 RISCV_PMU_EVENT_HW_INSTRUCTIONS = 0x02, 814 RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS = 0x10019, 815 RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS = 0x1001B, 816 RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS = 0x10021, 817 }; 818 819 /* CSR function table */ 820 extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; 821 822 extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[]; 823 824 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); 825 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); 826 827 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); 828 829 uint8_t satp_mode_max_from_map(uint32_t map); 830 const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); 831 832 #endif /* RISCV_CPU_H */ 833