1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef RISCV_CPU_H 21 #define RISCV_CPU_H 22 23 #include "hw/core/cpu.h" 24 #include "hw/registerfields.h" 25 #include "exec/cpu-defs.h" 26 #include "qemu/cpu-float.h" 27 #include "qom/object.h" 28 #include "qemu/int128.h" 29 #include "cpu_bits.h" 30 31 #define TCG_GUEST_DEFAULT_MO 0 32 33 /* 34 * RISC-V-specific extra insn start words: 35 * 1: Original instruction opcode 36 */ 37 #define TARGET_INSN_START_EXTRA_WORDS 1 38 39 #define TYPE_RISCV_CPU "riscv-cpu" 40 41 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU 42 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) 43 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU 44 45 #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") 46 #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") 47 #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") 48 #define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128") 49 #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") 50 #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") 51 #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") 52 #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") 53 #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") 54 #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") 55 #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") 56 #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") 57 58 #if defined(TARGET_RISCV32) 59 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 60 #elif defined(TARGET_RISCV64) 61 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 62 #endif 63 64 #define RV(x) ((target_ulong)1 << (x - 'A')) 65 66 /* 67 * Consider updating register_cpu_props() when adding 68 * new MISA bits here. 69 */ 70 #define RVI RV('I') 71 #define RVE RV('E') /* E and I are mutually exclusive */ 72 #define RVM RV('M') 73 #define RVA RV('A') 74 #define RVF RV('F') 75 #define RVD RV('D') 76 #define RVV RV('V') 77 #define RVC RV('C') 78 #define RVS RV('S') 79 #define RVU RV('U') 80 #define RVH RV('H') 81 #define RVJ RV('J') 82 83 /* S extension denotes that Supervisor mode exists, however it is possible 84 to have a core that support S mode but does not have an MMU and there 85 is currently no bit in misa to indicate whether an MMU exists or not 86 so a cpu features bitfield is required, likewise for optional PMP support */ 87 enum { 88 RISCV_FEATURE_MMU, 89 RISCV_FEATURE_PMP, 90 RISCV_FEATURE_EPMP, 91 RISCV_FEATURE_MISA, 92 RISCV_FEATURE_DEBUG 93 }; 94 95 /* Privileged specification version */ 96 enum { 97 PRIV_VERSION_1_10_0 = 0, 98 PRIV_VERSION_1_11_0, 99 PRIV_VERSION_1_12_0, 100 }; 101 102 #define VEXT_VERSION_1_00_0 0x00010000 103 104 enum { 105 TRANSLATE_SUCCESS, 106 TRANSLATE_FAIL, 107 TRANSLATE_PMP_FAIL, 108 TRANSLATE_G_STAGE_FAIL 109 }; 110 111 #define MMU_USER_IDX 3 112 113 #define MAX_RISCV_PMPS (16) 114 115 typedef struct CPUArchState CPURISCVState; 116 117 #if !defined(CONFIG_USER_ONLY) 118 #include "pmp.h" 119 #include "debug.h" 120 #endif 121 122 #define RV_VLEN_MAX 1024 123 #define RV_MAX_MHPMEVENTS 32 124 #define RV_MAX_MHPMCOUNTERS 32 125 126 FIELD(VTYPE, VLMUL, 0, 3) 127 FIELD(VTYPE, VSEW, 3, 3) 128 FIELD(VTYPE, VTA, 6, 1) 129 FIELD(VTYPE, VMA, 7, 1) 130 FIELD(VTYPE, VEDIV, 8, 2) 131 FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) 132 133 typedef struct PMUCTRState { 134 /* Current value of a counter */ 135 target_ulong mhpmcounter_val; 136 /* Current value of a counter in RV32*/ 137 target_ulong mhpmcounterh_val; 138 /* Snapshot values of counter */ 139 target_ulong mhpmcounter_prev; 140 /* Snapshort value of a counter in RV32 */ 141 target_ulong mhpmcounterh_prev; 142 bool started; 143 /* Value beyond UINT32_MAX/UINT64_MAX before overflow interrupt trigger */ 144 target_ulong irq_overflow_left; 145 } PMUCTRState; 146 147 struct CPUArchState { 148 target_ulong gpr[32]; 149 target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ 150 uint64_t fpr[32]; /* assume both F and D extensions */ 151 152 /* vector coprocessor state. */ 153 uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); 154 target_ulong vxrm; 155 target_ulong vxsat; 156 target_ulong vl; 157 target_ulong vstart; 158 target_ulong vtype; 159 bool vill; 160 161 target_ulong pc; 162 target_ulong load_res; 163 target_ulong load_val; 164 165 target_ulong frm; 166 167 target_ulong badaddr; 168 target_ulong bins; 169 170 target_ulong guest_phys_fault_addr; 171 172 target_ulong priv_ver; 173 target_ulong bext_ver; 174 target_ulong vext_ver; 175 176 /* RISCVMXL, but uint32_t for vmstate migration */ 177 uint32_t misa_mxl; /* current mxl */ 178 uint32_t misa_mxl_max; /* max mxl for this cpu */ 179 uint32_t misa_ext; /* current extensions */ 180 uint32_t misa_ext_mask; /* max ext for this cpu */ 181 uint32_t xl; /* current xlen */ 182 183 /* 128-bit helpers upper part return value */ 184 target_ulong retxh; 185 186 uint32_t features; 187 188 #ifdef CONFIG_USER_ONLY 189 uint32_t elf_flags; 190 #endif 191 192 #ifndef CONFIG_USER_ONLY 193 target_ulong priv; 194 /* This contains QEMU specific information about the virt state. */ 195 target_ulong virt; 196 target_ulong geilen; 197 uint64_t resetvec; 198 199 target_ulong mhartid; 200 /* 201 * For RV32 this is 32-bit mstatus and 32-bit mstatush. 202 * For RV64 this is a 64-bit mstatus. 203 */ 204 uint64_t mstatus; 205 206 uint64_t mip; 207 /* 208 * MIP contains the software writable version of SEIP ORed with the 209 * external interrupt value. The MIP register is always up-to-date. 210 * To keep track of the current source, we also save booleans of the values 211 * here. 212 */ 213 bool external_seip; 214 bool software_seip; 215 216 uint64_t miclaim; 217 218 uint64_t mie; 219 uint64_t mideleg; 220 221 target_ulong satp; /* since: priv-1.10.0 */ 222 target_ulong stval; 223 target_ulong medeleg; 224 225 target_ulong stvec; 226 target_ulong sepc; 227 target_ulong scause; 228 229 target_ulong mtvec; 230 target_ulong mepc; 231 target_ulong mcause; 232 target_ulong mtval; /* since: priv-1.10.0 */ 233 234 /* Machine and Supervisor interrupt priorities */ 235 uint8_t miprio[64]; 236 uint8_t siprio[64]; 237 238 /* AIA CSRs */ 239 target_ulong miselect; 240 target_ulong siselect; 241 242 /* Hypervisor CSRs */ 243 target_ulong hstatus; 244 target_ulong hedeleg; 245 uint64_t hideleg; 246 target_ulong hcounteren; 247 target_ulong htval; 248 target_ulong htinst; 249 target_ulong hgatp; 250 target_ulong hgeie; 251 target_ulong hgeip; 252 uint64_t htimedelta; 253 254 /* Hypervisor controlled virtual interrupt priorities */ 255 target_ulong hvictl; 256 uint8_t hviprio[64]; 257 258 /* Upper 64-bits of 128-bit CSRs */ 259 uint64_t mscratchh; 260 uint64_t sscratchh; 261 262 /* Virtual CSRs */ 263 /* 264 * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. 265 * For RV64 this is a 64-bit vsstatus. 266 */ 267 uint64_t vsstatus; 268 target_ulong vstvec; 269 target_ulong vsscratch; 270 target_ulong vsepc; 271 target_ulong vscause; 272 target_ulong vstval; 273 target_ulong vsatp; 274 275 /* AIA VS-mode CSRs */ 276 target_ulong vsiselect; 277 278 target_ulong mtval2; 279 target_ulong mtinst; 280 281 /* HS Backup CSRs */ 282 target_ulong stvec_hs; 283 target_ulong sscratch_hs; 284 target_ulong sepc_hs; 285 target_ulong scause_hs; 286 target_ulong stval_hs; 287 target_ulong satp_hs; 288 uint64_t mstatus_hs; 289 290 /* Signals whether the current exception occurred with two-stage address 291 translation active. */ 292 bool two_stage_lookup; 293 /* 294 * Signals whether the current exception occurred while doing two-stage 295 * address translation for the VS-stage page table walk. 296 */ 297 bool two_stage_indirect_lookup; 298 299 target_ulong scounteren; 300 target_ulong mcounteren; 301 302 target_ulong mcountinhibit; 303 304 /* PMU counter state */ 305 PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS]; 306 307 /* PMU event selector configured values. First three are unused*/ 308 target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS]; 309 310 /* PMU event selector configured values for RV32*/ 311 target_ulong mhpmeventh_val[RV_MAX_MHPMEVENTS]; 312 313 target_ulong sscratch; 314 target_ulong mscratch; 315 316 /* Sstc CSRs */ 317 uint64_t stimecmp; 318 319 uint64_t vstimecmp; 320 321 /* physical memory protection */ 322 pmp_table_t pmp_state; 323 target_ulong mseccfg; 324 325 /* trigger module */ 326 target_ulong trigger_cur; 327 target_ulong tdata1[RV_MAX_TRIGGERS]; 328 target_ulong tdata2[RV_MAX_TRIGGERS]; 329 target_ulong tdata3[RV_MAX_TRIGGERS]; 330 struct CPUBreakpoint *cpu_breakpoint[RV_MAX_TRIGGERS]; 331 struct CPUWatchpoint *cpu_watchpoint[RV_MAX_TRIGGERS]; 332 QEMUTimer *itrigger_timer[RV_MAX_TRIGGERS]; 333 int64_t last_icount; 334 bool itrigger_enabled; 335 336 /* machine specific rdtime callback */ 337 uint64_t (*rdtime_fn)(void *); 338 void *rdtime_fn_arg; 339 340 /* machine specific AIA ireg read-modify-write callback */ 341 #define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \ 342 ((((__xlen) & 0xff) << 24) | \ 343 (((__vgein) & 0x3f) << 20) | \ 344 (((__virt) & 0x1) << 18) | \ 345 (((__priv) & 0x3) << 16) | \ 346 (__isel & 0xffff)) 347 #define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff) 348 #define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3) 349 #define AIA_IREG_VIRT(__ireg) (((__ireg) >> 18) & 0x1) 350 #define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 20) & 0x3f) 351 #define AIA_IREG_XLEN(__ireg) (((__ireg) >> 24) & 0xff) 352 int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg, 353 target_ulong *val, target_ulong new_val, target_ulong write_mask); 354 void *aia_ireg_rmw_fn_arg[4]; 355 356 /* True if in debugger mode. */ 357 bool debugger; 358 359 /* 360 * CSRs for PointerMasking extension 361 */ 362 target_ulong mmte; 363 target_ulong mpmmask; 364 target_ulong mpmbase; 365 target_ulong spmmask; 366 target_ulong spmbase; 367 target_ulong upmmask; 368 target_ulong upmbase; 369 370 /* CSRs for execution enviornment configuration */ 371 uint64_t menvcfg; 372 uint64_t mstateen[SMSTATEEN_MAX_COUNT]; 373 uint64_t hstateen[SMSTATEEN_MAX_COUNT]; 374 uint64_t sstateen[SMSTATEEN_MAX_COUNT]; 375 target_ulong senvcfg; 376 uint64_t henvcfg; 377 #endif 378 target_ulong cur_pmmask; 379 target_ulong cur_pmbase; 380 381 float_status fp_status; 382 383 /* Fields from here on are preserved across CPU reset. */ 384 QEMUTimer *stimer; /* Internal timer for S-mode interrupt */ 385 QEMUTimer *vstimer; /* Internal timer for VS-mode interrupt */ 386 bool vstime_irq; 387 388 hwaddr kernel_addr; 389 hwaddr fdt_addr; 390 391 /* kvm timer */ 392 bool kvm_timer_dirty; 393 uint64_t kvm_timer_time; 394 uint64_t kvm_timer_compare; 395 uint64_t kvm_timer_state; 396 uint64_t kvm_timer_frequency; 397 }; 398 399 OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) 400 401 /** 402 * RISCVCPUClass: 403 * @parent_realize: The parent class' realize handler. 404 * @parent_phases: The parent class' reset phase handlers. 405 * 406 * A RISCV CPU model. 407 */ 408 struct RISCVCPUClass { 409 /*< private >*/ 410 CPUClass parent_class; 411 /*< public >*/ 412 DeviceRealize parent_realize; 413 ResettablePhases parent_phases; 414 }; 415 416 struct RISCVCPUConfig { 417 bool ext_i; 418 bool ext_e; 419 bool ext_g; 420 bool ext_m; 421 bool ext_a; 422 bool ext_f; 423 bool ext_d; 424 bool ext_c; 425 bool ext_s; 426 bool ext_u; 427 bool ext_h; 428 bool ext_j; 429 bool ext_v; 430 bool ext_zba; 431 bool ext_zbb; 432 bool ext_zbc; 433 bool ext_zbkb; 434 bool ext_zbkc; 435 bool ext_zbkx; 436 bool ext_zbs; 437 bool ext_zk; 438 bool ext_zkn; 439 bool ext_zknd; 440 bool ext_zkne; 441 bool ext_zknh; 442 bool ext_zkr; 443 bool ext_zks; 444 bool ext_zksed; 445 bool ext_zksh; 446 bool ext_zkt; 447 bool ext_ifencei; 448 bool ext_icsr; 449 bool ext_zihintpause; 450 bool ext_smstateen; 451 bool ext_sstc; 452 bool ext_svinval; 453 bool ext_svnapot; 454 bool ext_svpbmt; 455 bool ext_zdinx; 456 bool ext_zawrs; 457 bool ext_zfh; 458 bool ext_zfhmin; 459 bool ext_zfinx; 460 bool ext_zhinx; 461 bool ext_zhinxmin; 462 bool ext_zve32f; 463 bool ext_zve64f; 464 bool ext_zmmul; 465 bool ext_smaia; 466 bool ext_ssaia; 467 bool ext_sscofpmf; 468 bool rvv_ta_all_1s; 469 bool rvv_ma_all_1s; 470 471 uint32_t mvendorid; 472 uint64_t marchid; 473 uint64_t mimpid; 474 475 /* Vendor-specific custom extensions */ 476 bool ext_xtheadcmo; 477 bool ext_XVentanaCondOps; 478 479 uint8_t pmu_num; 480 char *priv_spec; 481 char *user_spec; 482 char *bext_spec; 483 char *vext_spec; 484 uint16_t vlen; 485 uint16_t elen; 486 bool mmu; 487 bool pmp; 488 bool epmp; 489 bool debug; 490 491 bool short_isa_string; 492 }; 493 494 typedef struct RISCVCPUConfig RISCVCPUConfig; 495 496 /** 497 * RISCVCPU: 498 * @env: #CPURISCVState 499 * 500 * A RISCV CPU. 501 */ 502 struct ArchCPU { 503 /*< private >*/ 504 CPUState parent_obj; 505 /*< public >*/ 506 CPUNegativeOffsetState neg; 507 CPURISCVState env; 508 509 char *dyn_csr_xml; 510 char *dyn_vreg_xml; 511 512 /* Configuration Settings */ 513 RISCVCPUConfig cfg; 514 515 QEMUTimer *pmu_timer; 516 /* A bitmask of Available programmable counters */ 517 uint32_t pmu_avail_ctrs; 518 /* Mapping of events to counters */ 519 GHashTable *pmu_event_ctr_map; 520 }; 521 522 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) 523 { 524 return (env->misa_ext & ext) != 0; 525 } 526 527 static inline bool riscv_feature(CPURISCVState *env, int feature) 528 { 529 return env->features & (1ULL << feature); 530 } 531 532 static inline void riscv_set_feature(CPURISCVState *env, int feature) 533 { 534 env->features |= (1ULL << feature); 535 } 536 537 #include "cpu_user.h" 538 539 extern const char * const riscv_int_regnames[]; 540 extern const char * const riscv_int_regnamesh[]; 541 extern const char * const riscv_fpr_regnames[]; 542 543 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); 544 void riscv_cpu_do_interrupt(CPUState *cpu); 545 int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 546 int cpuid, DumpState *s); 547 int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 548 int cpuid, DumpState *s); 549 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 550 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 551 int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero); 552 uint8_t riscv_cpu_default_priority(int irq); 553 uint64_t riscv_cpu_all_pending(CPURISCVState *env); 554 int riscv_cpu_mirq_pending(CPURISCVState *env); 555 int riscv_cpu_sirq_pending(CPURISCVState *env); 556 int riscv_cpu_vsirq_pending(CPURISCVState *env); 557 bool riscv_cpu_fp_enabled(CPURISCVState *env); 558 target_ulong riscv_cpu_get_geilen(CPURISCVState *env); 559 void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); 560 bool riscv_cpu_vector_enabled(CPURISCVState *env); 561 bool riscv_cpu_virt_enabled(CPURISCVState *env); 562 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); 563 bool riscv_cpu_two_stage_lookup(int mmu_idx); 564 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); 565 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 566 G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 567 MMUAccessType access_type, int mmu_idx, 568 uintptr_t retaddr); 569 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 570 MMUAccessType access_type, int mmu_idx, 571 bool probe, uintptr_t retaddr); 572 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 573 vaddr addr, unsigned size, 574 MMUAccessType access_type, 575 int mmu_idx, MemTxAttrs attrs, 576 MemTxResult response, uintptr_t retaddr); 577 char *riscv_isa_string(RISCVCPU *cpu); 578 void riscv_cpu_list(void); 579 580 #define cpu_list riscv_cpu_list 581 #define cpu_mmu_index riscv_cpu_mmu_index 582 583 #ifndef CONFIG_USER_ONLY 584 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); 585 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); 586 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); 587 uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value); 588 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ 589 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), 590 void *arg); 591 void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, 592 int (*rmw_fn)(void *arg, 593 target_ulong reg, 594 target_ulong *val, 595 target_ulong new_val, 596 target_ulong write_mask), 597 void *rmw_fn_arg); 598 #endif 599 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); 600 601 void riscv_translate_init(void); 602 G_NORETURN void riscv_raise_exception(CPURISCVState *env, 603 uint32_t exception, uintptr_t pc); 604 605 target_ulong riscv_cpu_get_fflags(CPURISCVState *env); 606 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); 607 608 #define TB_FLAGS_PRIV_MMU_MASK 3 609 #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2) 610 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS 611 #define TB_FLAGS_MSTATUS_VS MSTATUS_VS 612 613 #include "exec/cpu-all.h" 614 615 FIELD(TB_FLAGS, MEM_IDX, 0, 3) 616 FIELD(TB_FLAGS, LMUL, 3, 3) 617 FIELD(TB_FLAGS, SEW, 6, 3) 618 /* Skip MSTATUS_VS (0x600) bits */ 619 FIELD(TB_FLAGS, VL_EQ_VLMAX, 11, 1) 620 FIELD(TB_FLAGS, VILL, 12, 1) 621 /* Skip MSTATUS_FS (0x6000) bits */ 622 /* Is a Hypervisor instruction load/store allowed? */ 623 FIELD(TB_FLAGS, HLSX, 15, 1) 624 FIELD(TB_FLAGS, MSTATUS_HS_FS, 16, 2) 625 FIELD(TB_FLAGS, MSTATUS_HS_VS, 18, 2) 626 /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ 627 FIELD(TB_FLAGS, XL, 20, 2) 628 /* If PointerMasking should be applied */ 629 FIELD(TB_FLAGS, PM_MASK_ENABLED, 22, 1) 630 FIELD(TB_FLAGS, PM_BASE_ENABLED, 23, 1) 631 FIELD(TB_FLAGS, VTA, 24, 1) 632 FIELD(TB_FLAGS, VMA, 25, 1) 633 /* Native debug itrigger */ 634 FIELD(TB_FLAGS, ITRIGGER, 26, 1) 635 636 #ifdef TARGET_RISCV32 637 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) 638 #else 639 static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) 640 { 641 return env->misa_mxl; 642 } 643 #endif 644 #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env))) 645 646 #if defined(TARGET_RISCV32) 647 #define cpu_recompute_xl(env) ((void)(env), MXL_RV32) 648 #else 649 static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) 650 { 651 RISCVMXL xl = env->misa_mxl; 652 #if !defined(CONFIG_USER_ONLY) 653 /* 654 * When emulating a 32-bit-only cpu, use RV32. 655 * When emulating a 64-bit cpu, and MXL has been reduced to RV32, 656 * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened 657 * back to RV64 for lower privs. 658 */ 659 if (xl != MXL_RV32) { 660 switch (env->priv) { 661 case PRV_M: 662 break; 663 case PRV_U: 664 xl = get_field(env->mstatus, MSTATUS64_UXL); 665 break; 666 default: /* PRV_S | PRV_H */ 667 xl = get_field(env->mstatus, MSTATUS64_SXL); 668 break; 669 } 670 } 671 #endif 672 return xl; 673 } 674 #endif 675 676 static inline int riscv_cpu_xlen(CPURISCVState *env) 677 { 678 return 16 << env->xl; 679 } 680 681 #ifdef TARGET_RISCV32 682 #define riscv_cpu_sxl(env) ((void)(env), MXL_RV32) 683 #else 684 static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env) 685 { 686 #ifdef CONFIG_USER_ONLY 687 return env->misa_mxl; 688 #else 689 return get_field(env->mstatus, MSTATUS64_SXL); 690 #endif 691 } 692 #endif 693 694 /* 695 * Encode LMUL to lmul as follows: 696 * LMUL vlmul lmul 697 * 1 000 0 698 * 2 001 1 699 * 4 010 2 700 * 8 011 3 701 * - 100 - 702 * 1/8 101 -3 703 * 1/4 110 -2 704 * 1/2 111 -1 705 * 706 * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul) 707 * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8 708 * => VLMAX = vlen >> (1 + 3 - (-3)) 709 * = 256 >> 7 710 * = 2 711 */ 712 static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) 713 { 714 uint8_t sew = FIELD_EX64(vtype, VTYPE, VSEW); 715 int8_t lmul = sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3); 716 return cpu->cfg.vlen >> (sew + 3 - lmul); 717 } 718 719 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 720 target_ulong *cs_base, uint32_t *pflags); 721 722 void riscv_cpu_update_mask(CPURISCVState *env); 723 724 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, 725 target_ulong *ret_value, 726 target_ulong new_value, target_ulong write_mask); 727 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, 728 target_ulong *ret_value, 729 target_ulong new_value, 730 target_ulong write_mask); 731 732 static inline void riscv_csr_write(CPURISCVState *env, int csrno, 733 target_ulong val) 734 { 735 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); 736 } 737 738 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) 739 { 740 target_ulong val = 0; 741 riscv_csrrw(env, csrno, &val, 0, 0); 742 return val; 743 } 744 745 typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, 746 int csrno); 747 typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, 748 target_ulong *ret_value); 749 typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, 750 target_ulong new_value); 751 typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, 752 target_ulong *ret_value, 753 target_ulong new_value, 754 target_ulong write_mask); 755 756 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, 757 Int128 *ret_value, 758 Int128 new_value, Int128 write_mask); 759 760 typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno, 761 Int128 *ret_value); 762 typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int csrno, 763 Int128 new_value); 764 765 typedef struct { 766 const char *name; 767 riscv_csr_predicate_fn predicate; 768 riscv_csr_read_fn read; 769 riscv_csr_write_fn write; 770 riscv_csr_op_fn op; 771 riscv_csr_read128_fn read128; 772 riscv_csr_write128_fn write128; 773 /* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0) */ 774 uint32_t min_priv_ver; 775 } riscv_csr_operations; 776 777 /* CSR function table constants */ 778 enum { 779 CSR_TABLE_SIZE = 0x1000 780 }; 781 782 /** 783 * The event id are encoded based on the encoding specified in the 784 * SBI specification v0.3 785 */ 786 787 enum riscv_pmu_event_idx { 788 RISCV_PMU_EVENT_HW_CPU_CYCLES = 0x01, 789 RISCV_PMU_EVENT_HW_INSTRUCTIONS = 0x02, 790 RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS = 0x10019, 791 RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS = 0x1001B, 792 RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS = 0x10021, 793 }; 794 795 /* CSR function table */ 796 extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; 797 798 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); 799 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); 800 801 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); 802 803 #endif /* RISCV_CPU_H */ 804