1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef RISCV_CPU_H 21 #define RISCV_CPU_H 22 23 #include "hw/core/cpu.h" 24 #include "hw/registerfields.h" 25 #include "exec/cpu-defs.h" 26 #include "qemu/cpu-float.h" 27 #include "qom/object.h" 28 #include "qemu/int128.h" 29 #include "cpu_bits.h" 30 #include "qapi/qapi-types-common.h" 31 32 #define TCG_GUEST_DEFAULT_MO 0 33 34 /* 35 * RISC-V-specific extra insn start words: 36 * 1: Original instruction opcode 37 */ 38 #define TARGET_INSN_START_EXTRA_WORDS 1 39 40 #define TYPE_RISCV_CPU "riscv-cpu" 41 42 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU 43 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) 44 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU 45 46 #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") 47 #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") 48 #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") 49 #define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128") 50 #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") 51 #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") 52 #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") 53 #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") 54 #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") 55 #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") 56 #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") 57 #define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906") 58 #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") 59 60 #if defined(TARGET_RISCV32) 61 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 62 #elif defined(TARGET_RISCV64) 63 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 64 #endif 65 66 #define RV(x) ((target_ulong)1 << (x - 'A')) 67 68 /* Consider updating misa_ext_cfgs[] when adding new MISA bits here */ 69 #define RVI RV('I') 70 #define RVE RV('E') /* E and I are mutually exclusive */ 71 #define RVM RV('M') 72 #define RVA RV('A') 73 #define RVF RV('F') 74 #define RVD RV('D') 75 #define RVV RV('V') 76 #define RVC RV('C') 77 #define RVS RV('S') 78 #define RVU RV('U') 79 #define RVH RV('H') 80 #define RVJ RV('J') 81 #define RVG RV('G') 82 83 84 /* Privileged specification version */ 85 enum { 86 PRIV_VERSION_1_10_0 = 0, 87 PRIV_VERSION_1_11_0, 88 PRIV_VERSION_1_12_0, 89 }; 90 91 #define VEXT_VERSION_1_00_0 0x00010000 92 93 enum { 94 TRANSLATE_SUCCESS, 95 TRANSLATE_FAIL, 96 TRANSLATE_PMP_FAIL, 97 TRANSLATE_G_STAGE_FAIL 98 }; 99 100 #define MMU_USER_IDX 3 101 102 #define MAX_RISCV_PMPS (16) 103 104 typedef struct CPUArchState CPURISCVState; 105 106 #if !defined(CONFIG_USER_ONLY) 107 #include "pmp.h" 108 #include "debug.h" 109 #endif 110 111 #define RV_VLEN_MAX 1024 112 #define RV_MAX_MHPMEVENTS 32 113 #define RV_MAX_MHPMCOUNTERS 32 114 115 FIELD(VTYPE, VLMUL, 0, 3) 116 FIELD(VTYPE, VSEW, 3, 3) 117 FIELD(VTYPE, VTA, 6, 1) 118 FIELD(VTYPE, VMA, 7, 1) 119 FIELD(VTYPE, VEDIV, 8, 2) 120 FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) 121 122 typedef struct PMUCTRState { 123 /* Current value of a counter */ 124 target_ulong mhpmcounter_val; 125 /* Current value of a counter in RV32 */ 126 target_ulong mhpmcounterh_val; 127 /* Snapshot values of counter */ 128 target_ulong mhpmcounter_prev; 129 /* Snapshort value of a counter in RV32 */ 130 target_ulong mhpmcounterh_prev; 131 bool started; 132 /* Value beyond UINT32_MAX/UINT64_MAX before overflow interrupt trigger */ 133 target_ulong irq_overflow_left; 134 } PMUCTRState; 135 136 struct CPUArchState { 137 target_ulong gpr[32]; 138 target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ 139 140 /* vector coprocessor state. */ 141 uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); 142 target_ulong vxrm; 143 target_ulong vxsat; 144 target_ulong vl; 145 target_ulong vstart; 146 target_ulong vtype; 147 bool vill; 148 149 target_ulong pc; 150 target_ulong load_res; 151 target_ulong load_val; 152 153 /* Floating-Point state */ 154 uint64_t fpr[32]; /* assume both F and D extensions */ 155 target_ulong frm; 156 float_status fp_status; 157 158 target_ulong badaddr; 159 target_ulong bins; 160 161 target_ulong guest_phys_fault_addr; 162 163 target_ulong priv_ver; 164 target_ulong bext_ver; 165 target_ulong vext_ver; 166 167 /* RISCVMXL, but uint32_t for vmstate migration */ 168 uint32_t misa_mxl; /* current mxl */ 169 uint32_t misa_mxl_max; /* max mxl for this cpu */ 170 uint32_t misa_ext; /* current extensions */ 171 uint32_t misa_ext_mask; /* max ext for this cpu */ 172 uint32_t xl; /* current xlen */ 173 174 /* 128-bit helpers upper part return value */ 175 target_ulong retxh; 176 177 target_ulong jvt; 178 179 #ifdef CONFIG_USER_ONLY 180 uint32_t elf_flags; 181 #endif 182 183 #ifndef CONFIG_USER_ONLY 184 target_ulong priv; 185 /* This contains QEMU specific information about the virt state. */ 186 bool virt_enabled; 187 target_ulong geilen; 188 uint64_t resetvec; 189 190 target_ulong mhartid; 191 /* 192 * For RV32 this is 32-bit mstatus and 32-bit mstatush. 193 * For RV64 this is a 64-bit mstatus. 194 */ 195 uint64_t mstatus; 196 197 uint64_t mip; 198 /* 199 * MIP contains the software writable version of SEIP ORed with the 200 * external interrupt value. The MIP register is always up-to-date. 201 * To keep track of the current source, we also save booleans of the values 202 * here. 203 */ 204 bool external_seip; 205 bool software_seip; 206 207 uint64_t miclaim; 208 209 uint64_t mie; 210 uint64_t mideleg; 211 212 target_ulong satp; /* since: priv-1.10.0 */ 213 target_ulong stval; 214 target_ulong medeleg; 215 216 target_ulong stvec; 217 target_ulong sepc; 218 target_ulong scause; 219 220 target_ulong mtvec; 221 target_ulong mepc; 222 target_ulong mcause; 223 target_ulong mtval; /* since: priv-1.10.0 */ 224 225 /* Machine and Supervisor interrupt priorities */ 226 uint8_t miprio[64]; 227 uint8_t siprio[64]; 228 229 /* AIA CSRs */ 230 target_ulong miselect; 231 target_ulong siselect; 232 233 /* Hypervisor CSRs */ 234 target_ulong hstatus; 235 target_ulong hedeleg; 236 uint64_t hideleg; 237 target_ulong hcounteren; 238 target_ulong htval; 239 target_ulong htinst; 240 target_ulong hgatp; 241 target_ulong hgeie; 242 target_ulong hgeip; 243 uint64_t htimedelta; 244 245 /* Hypervisor controlled virtual interrupt priorities */ 246 target_ulong hvictl; 247 uint8_t hviprio[64]; 248 249 /* Upper 64-bits of 128-bit CSRs */ 250 uint64_t mscratchh; 251 uint64_t sscratchh; 252 253 /* Virtual CSRs */ 254 /* 255 * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. 256 * For RV64 this is a 64-bit vsstatus. 257 */ 258 uint64_t vsstatus; 259 target_ulong vstvec; 260 target_ulong vsscratch; 261 target_ulong vsepc; 262 target_ulong vscause; 263 target_ulong vstval; 264 target_ulong vsatp; 265 266 /* AIA VS-mode CSRs */ 267 target_ulong vsiselect; 268 269 target_ulong mtval2; 270 target_ulong mtinst; 271 272 /* HS Backup CSRs */ 273 target_ulong stvec_hs; 274 target_ulong sscratch_hs; 275 target_ulong sepc_hs; 276 target_ulong scause_hs; 277 target_ulong stval_hs; 278 target_ulong satp_hs; 279 uint64_t mstatus_hs; 280 281 /* 282 * Signals whether the current exception occurred with two-stage address 283 * translation active. 284 */ 285 bool two_stage_lookup; 286 /* 287 * Signals whether the current exception occurred while doing two-stage 288 * address translation for the VS-stage page table walk. 289 */ 290 bool two_stage_indirect_lookup; 291 292 target_ulong scounteren; 293 target_ulong mcounteren; 294 295 target_ulong mcountinhibit; 296 297 /* PMU counter state */ 298 PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS]; 299 300 /* PMU event selector configured values. First three are unused */ 301 target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS]; 302 303 /* PMU event selector configured values for RV32 */ 304 target_ulong mhpmeventh_val[RV_MAX_MHPMEVENTS]; 305 306 target_ulong sscratch; 307 target_ulong mscratch; 308 309 /* Sstc CSRs */ 310 uint64_t stimecmp; 311 312 uint64_t vstimecmp; 313 314 /* physical memory protection */ 315 pmp_table_t pmp_state; 316 target_ulong mseccfg; 317 318 /* trigger module */ 319 target_ulong trigger_cur; 320 target_ulong tdata1[RV_MAX_TRIGGERS]; 321 target_ulong tdata2[RV_MAX_TRIGGERS]; 322 target_ulong tdata3[RV_MAX_TRIGGERS]; 323 struct CPUBreakpoint *cpu_breakpoint[RV_MAX_TRIGGERS]; 324 struct CPUWatchpoint *cpu_watchpoint[RV_MAX_TRIGGERS]; 325 QEMUTimer *itrigger_timer[RV_MAX_TRIGGERS]; 326 int64_t last_icount; 327 bool itrigger_enabled; 328 329 /* machine specific rdtime callback */ 330 uint64_t (*rdtime_fn)(void *); 331 void *rdtime_fn_arg; 332 333 /* machine specific AIA ireg read-modify-write callback */ 334 #define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \ 335 ((((__xlen) & 0xff) << 24) | \ 336 (((__vgein) & 0x3f) << 20) | \ 337 (((__virt) & 0x1) << 18) | \ 338 (((__priv) & 0x3) << 16) | \ 339 (__isel & 0xffff)) 340 #define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff) 341 #define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3) 342 #define AIA_IREG_VIRT(__ireg) (((__ireg) >> 18) & 0x1) 343 #define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 20) & 0x3f) 344 #define AIA_IREG_XLEN(__ireg) (((__ireg) >> 24) & 0xff) 345 int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg, 346 target_ulong *val, target_ulong new_val, target_ulong write_mask); 347 void *aia_ireg_rmw_fn_arg[4]; 348 349 /* True if in debugger mode. */ 350 bool debugger; 351 352 /* 353 * CSRs for PointerMasking extension 354 */ 355 target_ulong mmte; 356 target_ulong mpmmask; 357 target_ulong mpmbase; 358 target_ulong spmmask; 359 target_ulong spmbase; 360 target_ulong upmmask; 361 target_ulong upmbase; 362 363 /* CSRs for execution enviornment configuration */ 364 uint64_t menvcfg; 365 uint64_t mstateen[SMSTATEEN_MAX_COUNT]; 366 uint64_t hstateen[SMSTATEEN_MAX_COUNT]; 367 uint64_t sstateen[SMSTATEEN_MAX_COUNT]; 368 target_ulong senvcfg; 369 uint64_t henvcfg; 370 #endif 371 target_ulong cur_pmmask; 372 target_ulong cur_pmbase; 373 374 /* Fields from here on are preserved across CPU reset. */ 375 QEMUTimer *stimer; /* Internal timer for S-mode interrupt */ 376 QEMUTimer *vstimer; /* Internal timer for VS-mode interrupt */ 377 bool vstime_irq; 378 379 hwaddr kernel_addr; 380 hwaddr fdt_addr; 381 382 /* kvm timer */ 383 bool kvm_timer_dirty; 384 uint64_t kvm_timer_time; 385 uint64_t kvm_timer_compare; 386 uint64_t kvm_timer_state; 387 uint64_t kvm_timer_frequency; 388 }; 389 390 OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) 391 392 /* 393 * RISCVCPUClass: 394 * @parent_realize: The parent class' realize handler. 395 * @parent_phases: The parent class' reset phase handlers. 396 * 397 * A RISCV CPU model. 398 */ 399 struct RISCVCPUClass { 400 /* < private > */ 401 CPUClass parent_class; 402 /* < public > */ 403 DeviceRealize parent_realize; 404 ResettablePhases parent_phases; 405 }; 406 407 /* 408 * map is a 16-bit bitmap: the most significant set bit in map is the maximum 409 * satp mode that is supported. It may be chosen by the user and must respect 410 * what qemu implements (valid_1_10_32/64) and what the hw is capable of 411 * (supported bitmap below). 412 * 413 * init is a 16-bit bitmap used to make sure the user selected a correct 414 * configuration as per the specification. 415 * 416 * supported is a 16-bit bitmap used to reflect the hw capabilities. 417 */ 418 typedef struct { 419 uint16_t map, init, supported; 420 } RISCVSATPMap; 421 422 struct RISCVCPUConfig { 423 bool ext_zba; 424 bool ext_zbb; 425 bool ext_zbc; 426 bool ext_zbkb; 427 bool ext_zbkc; 428 bool ext_zbkx; 429 bool ext_zbs; 430 bool ext_zca; 431 bool ext_zcb; 432 bool ext_zcd; 433 bool ext_zce; 434 bool ext_zcf; 435 bool ext_zcmp; 436 bool ext_zcmt; 437 bool ext_zk; 438 bool ext_zkn; 439 bool ext_zknd; 440 bool ext_zkne; 441 bool ext_zknh; 442 bool ext_zkr; 443 bool ext_zks; 444 bool ext_zksed; 445 bool ext_zksh; 446 bool ext_zkt; 447 bool ext_ifencei; 448 bool ext_icsr; 449 bool ext_icbom; 450 bool ext_icboz; 451 bool ext_zicond; 452 bool ext_zihintpause; 453 bool ext_smstateen; 454 bool ext_sstc; 455 bool ext_svadu; 456 bool ext_svinval; 457 bool ext_svnapot; 458 bool ext_svpbmt; 459 bool ext_zdinx; 460 bool ext_zawrs; 461 bool ext_zfh; 462 bool ext_zfhmin; 463 bool ext_zfinx; 464 bool ext_zhinx; 465 bool ext_zhinxmin; 466 bool ext_zve32f; 467 bool ext_zve64f; 468 bool ext_zve64d; 469 bool ext_zmmul; 470 bool ext_zvfh; 471 bool ext_zvfhmin; 472 bool ext_smaia; 473 bool ext_ssaia; 474 bool ext_sscofpmf; 475 bool rvv_ta_all_1s; 476 bool rvv_ma_all_1s; 477 478 uint32_t mvendorid; 479 uint64_t marchid; 480 uint64_t mimpid; 481 482 /* Vendor-specific custom extensions */ 483 bool ext_xtheadba; 484 bool ext_xtheadbb; 485 bool ext_xtheadbs; 486 bool ext_xtheadcmo; 487 bool ext_xtheadcondmov; 488 bool ext_xtheadfmemidx; 489 bool ext_xtheadfmv; 490 bool ext_xtheadmac; 491 bool ext_xtheadmemidx; 492 bool ext_xtheadmempair; 493 bool ext_xtheadsync; 494 bool ext_XVentanaCondOps; 495 496 uint8_t pmu_num; 497 char *priv_spec; 498 char *user_spec; 499 char *bext_spec; 500 char *vext_spec; 501 uint16_t vlen; 502 uint16_t elen; 503 uint16_t cbom_blocksize; 504 uint16_t cboz_blocksize; 505 bool mmu; 506 bool pmp; 507 bool epmp; 508 bool debug; 509 bool misa_w; 510 511 bool short_isa_string; 512 513 #ifndef CONFIG_USER_ONLY 514 RISCVSATPMap satp_mode; 515 #endif 516 }; 517 518 typedef struct RISCVCPUConfig RISCVCPUConfig; 519 520 /* 521 * RISCVCPU: 522 * @env: #CPURISCVState 523 * 524 * A RISCV CPU. 525 */ 526 struct ArchCPU { 527 /* < private > */ 528 CPUState parent_obj; 529 /* < public > */ 530 CPUNegativeOffsetState neg; 531 CPURISCVState env; 532 533 char *dyn_csr_xml; 534 char *dyn_vreg_xml; 535 536 /* Configuration Settings */ 537 RISCVCPUConfig cfg; 538 539 QEMUTimer *pmu_timer; 540 /* A bitmask of Available programmable counters */ 541 uint32_t pmu_avail_ctrs; 542 /* Mapping of events to counters */ 543 GHashTable *pmu_event_ctr_map; 544 }; 545 546 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) 547 { 548 return (env->misa_ext & ext) != 0; 549 } 550 551 #include "cpu_user.h" 552 553 extern const char * const riscv_int_regnames[]; 554 extern const char * const riscv_int_regnamesh[]; 555 extern const char * const riscv_fpr_regnames[]; 556 557 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); 558 void riscv_cpu_do_interrupt(CPUState *cpu); 559 int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 560 int cpuid, DumpState *s); 561 int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 562 int cpuid, DumpState *s); 563 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 564 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 565 int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero); 566 uint8_t riscv_cpu_default_priority(int irq); 567 uint64_t riscv_cpu_all_pending(CPURISCVState *env); 568 int riscv_cpu_mirq_pending(CPURISCVState *env); 569 int riscv_cpu_sirq_pending(CPURISCVState *env); 570 int riscv_cpu_vsirq_pending(CPURISCVState *env); 571 bool riscv_cpu_fp_enabled(CPURISCVState *env); 572 target_ulong riscv_cpu_get_geilen(CPURISCVState *env); 573 void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); 574 bool riscv_cpu_vector_enabled(CPURISCVState *env); 575 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); 576 bool riscv_cpu_two_stage_lookup(int mmu_idx); 577 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); 578 G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 579 MMUAccessType access_type, 580 int mmu_idx, uintptr_t retaddr); 581 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 582 MMUAccessType access_type, int mmu_idx, 583 bool probe, uintptr_t retaddr); 584 char *riscv_isa_string(RISCVCPU *cpu); 585 void riscv_cpu_list(void); 586 587 #define cpu_list riscv_cpu_list 588 #define cpu_mmu_index riscv_cpu_mmu_index 589 590 #ifndef CONFIG_USER_ONLY 591 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 592 vaddr addr, unsigned size, 593 MMUAccessType access_type, 594 int mmu_idx, MemTxAttrs attrs, 595 MemTxResult response, uintptr_t retaddr); 596 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 597 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); 598 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); 599 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); 600 uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask, 601 uint64_t value); 602 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ 603 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), 604 void *arg); 605 void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, 606 int (*rmw_fn)(void *arg, 607 target_ulong reg, 608 target_ulong *val, 609 target_ulong new_val, 610 target_ulong write_mask), 611 void *rmw_fn_arg); 612 613 RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit); 614 #endif 615 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); 616 617 void riscv_translate_init(void); 618 G_NORETURN void riscv_raise_exception(CPURISCVState *env, 619 uint32_t exception, uintptr_t pc); 620 621 target_ulong riscv_cpu_get_fflags(CPURISCVState *env); 622 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); 623 624 #define TB_FLAGS_PRIV_MMU_MASK 3 625 #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2) 626 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS 627 #define TB_FLAGS_MSTATUS_VS MSTATUS_VS 628 629 #include "exec/cpu-all.h" 630 631 FIELD(TB_FLAGS, MEM_IDX, 0, 3) 632 FIELD(TB_FLAGS, LMUL, 3, 3) 633 FIELD(TB_FLAGS, SEW, 6, 3) 634 /* Skip MSTATUS_VS (0x600) bits */ 635 FIELD(TB_FLAGS, VL_EQ_VLMAX, 11, 1) 636 FIELD(TB_FLAGS, VILL, 12, 1) 637 /* Skip MSTATUS_FS (0x6000) bits */ 638 /* Is a Hypervisor instruction load/store allowed? */ 639 FIELD(TB_FLAGS, HLSX, 15, 1) 640 FIELD(TB_FLAGS, MSTATUS_HS_FS, 16, 2) 641 FIELD(TB_FLAGS, MSTATUS_HS_VS, 18, 2) 642 /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ 643 FIELD(TB_FLAGS, XL, 20, 2) 644 /* If PointerMasking should be applied */ 645 FIELD(TB_FLAGS, PM_MASK_ENABLED, 22, 1) 646 FIELD(TB_FLAGS, PM_BASE_ENABLED, 23, 1) 647 FIELD(TB_FLAGS, VTA, 24, 1) 648 FIELD(TB_FLAGS, VMA, 25, 1) 649 /* Native debug itrigger */ 650 FIELD(TB_FLAGS, ITRIGGER, 26, 1) 651 652 #ifdef TARGET_RISCV32 653 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) 654 #else 655 static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) 656 { 657 return env->misa_mxl; 658 } 659 #endif 660 #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env))) 661 662 static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURISCVState *env) 663 { 664 return &env_archcpu(env)->cfg; 665 } 666 667 #if defined(TARGET_RISCV32) 668 #define cpu_recompute_xl(env) ((void)(env), MXL_RV32) 669 #else 670 static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) 671 { 672 RISCVMXL xl = env->misa_mxl; 673 #if !defined(CONFIG_USER_ONLY) 674 /* 675 * When emulating a 32-bit-only cpu, use RV32. 676 * When emulating a 64-bit cpu, and MXL has been reduced to RV32, 677 * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened 678 * back to RV64 for lower privs. 679 */ 680 if (xl != MXL_RV32) { 681 switch (env->priv) { 682 case PRV_M: 683 break; 684 case PRV_U: 685 xl = get_field(env->mstatus, MSTATUS64_UXL); 686 break; 687 default: /* PRV_S */ 688 xl = get_field(env->mstatus, MSTATUS64_SXL); 689 break; 690 } 691 } 692 #endif 693 return xl; 694 } 695 #endif 696 697 static inline int riscv_cpu_xlen(CPURISCVState *env) 698 { 699 return 16 << env->xl; 700 } 701 702 #ifdef TARGET_RISCV32 703 #define riscv_cpu_sxl(env) ((void)(env), MXL_RV32) 704 #else 705 static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env) 706 { 707 #ifdef CONFIG_USER_ONLY 708 return env->misa_mxl; 709 #else 710 return get_field(env->mstatus, MSTATUS64_SXL); 711 #endif 712 } 713 #endif 714 715 /* 716 * Encode LMUL to lmul as follows: 717 * LMUL vlmul lmul 718 * 1 000 0 719 * 2 001 1 720 * 4 010 2 721 * 8 011 3 722 * - 100 - 723 * 1/8 101 -3 724 * 1/4 110 -2 725 * 1/2 111 -1 726 * 727 * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul) 728 * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8 729 * => VLMAX = vlen >> (1 + 3 - (-3)) 730 * = 256 >> 7 731 * = 2 732 */ 733 static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) 734 { 735 uint8_t sew = FIELD_EX64(vtype, VTYPE, VSEW); 736 int8_t lmul = sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3); 737 return cpu->cfg.vlen >> (sew + 3 - lmul); 738 } 739 740 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 741 target_ulong *cs_base, uint32_t *pflags); 742 743 void riscv_cpu_update_mask(CPURISCVState *env); 744 745 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, 746 target_ulong *ret_value, 747 target_ulong new_value, target_ulong write_mask); 748 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, 749 target_ulong *ret_value, 750 target_ulong new_value, 751 target_ulong write_mask); 752 753 static inline void riscv_csr_write(CPURISCVState *env, int csrno, 754 target_ulong val) 755 { 756 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); 757 } 758 759 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) 760 { 761 target_ulong val = 0; 762 riscv_csrrw(env, csrno, &val, 0, 0); 763 return val; 764 } 765 766 typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, 767 int csrno); 768 typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, 769 target_ulong *ret_value); 770 typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, 771 target_ulong new_value); 772 typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, 773 target_ulong *ret_value, 774 target_ulong new_value, 775 target_ulong write_mask); 776 777 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, 778 Int128 *ret_value, 779 Int128 new_value, Int128 write_mask); 780 781 typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno, 782 Int128 *ret_value); 783 typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int csrno, 784 Int128 new_value); 785 786 typedef struct { 787 const char *name; 788 riscv_csr_predicate_fn predicate; 789 riscv_csr_read_fn read; 790 riscv_csr_write_fn write; 791 riscv_csr_op_fn op; 792 riscv_csr_read128_fn read128; 793 riscv_csr_write128_fn write128; 794 /* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0) */ 795 uint32_t min_priv_ver; 796 } riscv_csr_operations; 797 798 /* CSR function table constants */ 799 enum { 800 CSR_TABLE_SIZE = 0x1000 801 }; 802 803 /* 804 * The event id are encoded based on the encoding specified in the 805 * SBI specification v0.3 806 */ 807 808 enum riscv_pmu_event_idx { 809 RISCV_PMU_EVENT_HW_CPU_CYCLES = 0x01, 810 RISCV_PMU_EVENT_HW_INSTRUCTIONS = 0x02, 811 RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS = 0x10019, 812 RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS = 0x1001B, 813 RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS = 0x10021, 814 }; 815 816 /* CSR function table */ 817 extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; 818 819 extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[]; 820 821 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); 822 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); 823 824 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); 825 826 uint8_t satp_mode_max_from_map(uint32_t map); 827 const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); 828 829 #endif /* RISCV_CPU_H */ 830