1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef RISCV_CPU_H 21 #define RISCV_CPU_H 22 23 #include "hw/core/cpu.h" 24 #include "hw/registerfields.h" 25 #include "exec/cpu-defs.h" 26 #include "qemu/cpu-float.h" 27 #include "qom/object.h" 28 #include "qemu/int128.h" 29 #include "cpu_bits.h" 30 31 #define TCG_GUEST_DEFAULT_MO 0 32 33 /* 34 * RISC-V-specific extra insn start words: 35 * 1: Original instruction opcode 36 */ 37 #define TARGET_INSN_START_EXTRA_WORDS 1 38 39 #define TYPE_RISCV_CPU "riscv-cpu" 40 41 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU 42 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) 43 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU 44 45 #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") 46 #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") 47 #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") 48 #define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128") 49 #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") 50 #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") 51 #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") 52 #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") 53 #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") 54 #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") 55 #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") 56 #define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906") 57 #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") 58 59 #if defined(TARGET_RISCV32) 60 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 61 #elif defined(TARGET_RISCV64) 62 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 63 #endif 64 65 #define RV(x) ((target_ulong)1 << (x - 'A')) 66 67 /* 68 * Consider updating register_cpu_props() when adding 69 * new MISA bits here. 70 */ 71 #define RVI RV('I') 72 #define RVE RV('E') /* E and I are mutually exclusive */ 73 #define RVM RV('M') 74 #define RVA RV('A') 75 #define RVF RV('F') 76 #define RVD RV('D') 77 #define RVV RV('V') 78 #define RVC RV('C') 79 #define RVS RV('S') 80 #define RVU RV('U') 81 #define RVH RV('H') 82 #define RVJ RV('J') 83 84 /* S extension denotes that Supervisor mode exists, however it is possible 85 to have a core that support S mode but does not have an MMU and there 86 is currently no bit in misa to indicate whether an MMU exists or not 87 so a cpu features bitfield is required, likewise for optional PMP support */ 88 enum { 89 RISCV_FEATURE_MMU, 90 }; 91 92 /* Privileged specification version */ 93 enum { 94 PRIV_VERSION_1_10_0 = 0, 95 PRIV_VERSION_1_11_0, 96 PRIV_VERSION_1_12_0, 97 }; 98 99 #define VEXT_VERSION_1_00_0 0x00010000 100 101 enum { 102 TRANSLATE_SUCCESS, 103 TRANSLATE_FAIL, 104 TRANSLATE_PMP_FAIL, 105 TRANSLATE_G_STAGE_FAIL 106 }; 107 108 #define MMU_USER_IDX 3 109 110 #define MAX_RISCV_PMPS (16) 111 112 typedef struct CPUArchState CPURISCVState; 113 114 #if !defined(CONFIG_USER_ONLY) 115 #include "pmp.h" 116 #include "debug.h" 117 #endif 118 119 #define RV_VLEN_MAX 1024 120 #define RV_MAX_MHPMEVENTS 32 121 #define RV_MAX_MHPMCOUNTERS 32 122 123 FIELD(VTYPE, VLMUL, 0, 3) 124 FIELD(VTYPE, VSEW, 3, 3) 125 FIELD(VTYPE, VTA, 6, 1) 126 FIELD(VTYPE, VMA, 7, 1) 127 FIELD(VTYPE, VEDIV, 8, 2) 128 FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) 129 130 typedef struct PMUCTRState { 131 /* Current value of a counter */ 132 target_ulong mhpmcounter_val; 133 /* Current value of a counter in RV32*/ 134 target_ulong mhpmcounterh_val; 135 /* Snapshot values of counter */ 136 target_ulong mhpmcounter_prev; 137 /* Snapshort value of a counter in RV32 */ 138 target_ulong mhpmcounterh_prev; 139 bool started; 140 /* Value beyond UINT32_MAX/UINT64_MAX before overflow interrupt trigger */ 141 target_ulong irq_overflow_left; 142 } PMUCTRState; 143 144 struct CPUArchState { 145 target_ulong gpr[32]; 146 target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ 147 148 /* vector coprocessor state. */ 149 uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); 150 target_ulong vxrm; 151 target_ulong vxsat; 152 target_ulong vl; 153 target_ulong vstart; 154 target_ulong vtype; 155 bool vill; 156 157 target_ulong pc; 158 target_ulong load_res; 159 target_ulong load_val; 160 161 /* Floating-Point state */ 162 uint64_t fpr[32]; /* assume both F and D extensions */ 163 target_ulong frm; 164 float_status fp_status; 165 166 target_ulong badaddr; 167 target_ulong bins; 168 169 target_ulong guest_phys_fault_addr; 170 171 target_ulong priv_ver; 172 target_ulong bext_ver; 173 target_ulong vext_ver; 174 175 /* RISCVMXL, but uint32_t for vmstate migration */ 176 uint32_t misa_mxl; /* current mxl */ 177 uint32_t misa_mxl_max; /* max mxl for this cpu */ 178 uint32_t misa_ext; /* current extensions */ 179 uint32_t misa_ext_mask; /* max ext for this cpu */ 180 uint32_t xl; /* current xlen */ 181 182 /* 128-bit helpers upper part return value */ 183 target_ulong retxh; 184 185 uint32_t features; 186 187 #ifdef CONFIG_USER_ONLY 188 uint32_t elf_flags; 189 #endif 190 191 #ifndef CONFIG_USER_ONLY 192 target_ulong priv; 193 /* This contains QEMU specific information about the virt state. */ 194 target_ulong virt; 195 target_ulong geilen; 196 uint64_t resetvec; 197 198 target_ulong mhartid; 199 /* 200 * For RV32 this is 32-bit mstatus and 32-bit mstatush. 201 * For RV64 this is a 64-bit mstatus. 202 */ 203 uint64_t mstatus; 204 205 uint64_t mip; 206 /* 207 * MIP contains the software writable version of SEIP ORed with the 208 * external interrupt value. The MIP register is always up-to-date. 209 * To keep track of the current source, we also save booleans of the values 210 * here. 211 */ 212 bool external_seip; 213 bool software_seip; 214 215 uint64_t miclaim; 216 217 uint64_t mie; 218 uint64_t mideleg; 219 220 target_ulong satp; /* since: priv-1.10.0 */ 221 target_ulong stval; 222 target_ulong medeleg; 223 224 target_ulong stvec; 225 target_ulong sepc; 226 target_ulong scause; 227 228 target_ulong mtvec; 229 target_ulong mepc; 230 target_ulong mcause; 231 target_ulong mtval; /* since: priv-1.10.0 */ 232 233 /* Machine and Supervisor interrupt priorities */ 234 uint8_t miprio[64]; 235 uint8_t siprio[64]; 236 237 /* AIA CSRs */ 238 target_ulong miselect; 239 target_ulong siselect; 240 241 /* Hypervisor CSRs */ 242 target_ulong hstatus; 243 target_ulong hedeleg; 244 uint64_t hideleg; 245 target_ulong hcounteren; 246 target_ulong htval; 247 target_ulong htinst; 248 target_ulong hgatp; 249 target_ulong hgeie; 250 target_ulong hgeip; 251 uint64_t htimedelta; 252 253 /* Hypervisor controlled virtual interrupt priorities */ 254 target_ulong hvictl; 255 uint8_t hviprio[64]; 256 257 /* Upper 64-bits of 128-bit CSRs */ 258 uint64_t mscratchh; 259 uint64_t sscratchh; 260 261 /* Virtual CSRs */ 262 /* 263 * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. 264 * For RV64 this is a 64-bit vsstatus. 265 */ 266 uint64_t vsstatus; 267 target_ulong vstvec; 268 target_ulong vsscratch; 269 target_ulong vsepc; 270 target_ulong vscause; 271 target_ulong vstval; 272 target_ulong vsatp; 273 274 /* AIA VS-mode CSRs */ 275 target_ulong vsiselect; 276 277 target_ulong mtval2; 278 target_ulong mtinst; 279 280 /* HS Backup CSRs */ 281 target_ulong stvec_hs; 282 target_ulong sscratch_hs; 283 target_ulong sepc_hs; 284 target_ulong scause_hs; 285 target_ulong stval_hs; 286 target_ulong satp_hs; 287 uint64_t mstatus_hs; 288 289 /* Signals whether the current exception occurred with two-stage address 290 translation active. */ 291 bool two_stage_lookup; 292 /* 293 * Signals whether the current exception occurred while doing two-stage 294 * address translation for the VS-stage page table walk. 295 */ 296 bool two_stage_indirect_lookup; 297 298 target_ulong scounteren; 299 target_ulong mcounteren; 300 301 target_ulong mcountinhibit; 302 303 /* PMU counter state */ 304 PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS]; 305 306 /* PMU event selector configured values. First three are unused*/ 307 target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS]; 308 309 /* PMU event selector configured values for RV32*/ 310 target_ulong mhpmeventh_val[RV_MAX_MHPMEVENTS]; 311 312 target_ulong sscratch; 313 target_ulong mscratch; 314 315 /* Sstc CSRs */ 316 uint64_t stimecmp; 317 318 uint64_t vstimecmp; 319 320 /* physical memory protection */ 321 pmp_table_t pmp_state; 322 target_ulong mseccfg; 323 324 /* trigger module */ 325 target_ulong trigger_cur; 326 target_ulong tdata1[RV_MAX_TRIGGERS]; 327 target_ulong tdata2[RV_MAX_TRIGGERS]; 328 target_ulong tdata3[RV_MAX_TRIGGERS]; 329 struct CPUBreakpoint *cpu_breakpoint[RV_MAX_TRIGGERS]; 330 struct CPUWatchpoint *cpu_watchpoint[RV_MAX_TRIGGERS]; 331 QEMUTimer *itrigger_timer[RV_MAX_TRIGGERS]; 332 int64_t last_icount; 333 bool itrigger_enabled; 334 335 /* machine specific rdtime callback */ 336 uint64_t (*rdtime_fn)(void *); 337 void *rdtime_fn_arg; 338 339 /* machine specific AIA ireg read-modify-write callback */ 340 #define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \ 341 ((((__xlen) & 0xff) << 24) | \ 342 (((__vgein) & 0x3f) << 20) | \ 343 (((__virt) & 0x1) << 18) | \ 344 (((__priv) & 0x3) << 16) | \ 345 (__isel & 0xffff)) 346 #define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff) 347 #define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3) 348 #define AIA_IREG_VIRT(__ireg) (((__ireg) >> 18) & 0x1) 349 #define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 20) & 0x3f) 350 #define AIA_IREG_XLEN(__ireg) (((__ireg) >> 24) & 0xff) 351 int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg, 352 target_ulong *val, target_ulong new_val, target_ulong write_mask); 353 void *aia_ireg_rmw_fn_arg[4]; 354 355 /* True if in debugger mode. */ 356 bool debugger; 357 358 /* 359 * CSRs for PointerMasking extension 360 */ 361 target_ulong mmte; 362 target_ulong mpmmask; 363 target_ulong mpmbase; 364 target_ulong spmmask; 365 target_ulong spmbase; 366 target_ulong upmmask; 367 target_ulong upmbase; 368 369 /* CSRs for execution enviornment configuration */ 370 uint64_t menvcfg; 371 uint64_t mstateen[SMSTATEEN_MAX_COUNT]; 372 uint64_t hstateen[SMSTATEEN_MAX_COUNT]; 373 uint64_t sstateen[SMSTATEEN_MAX_COUNT]; 374 target_ulong senvcfg; 375 uint64_t henvcfg; 376 #endif 377 target_ulong cur_pmmask; 378 target_ulong cur_pmbase; 379 380 /* Fields from here on are preserved across CPU reset. */ 381 QEMUTimer *stimer; /* Internal timer for S-mode interrupt */ 382 QEMUTimer *vstimer; /* Internal timer for VS-mode interrupt */ 383 bool vstime_irq; 384 385 hwaddr kernel_addr; 386 hwaddr fdt_addr; 387 388 /* kvm timer */ 389 bool kvm_timer_dirty; 390 uint64_t kvm_timer_time; 391 uint64_t kvm_timer_compare; 392 uint64_t kvm_timer_state; 393 uint64_t kvm_timer_frequency; 394 }; 395 396 OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) 397 398 /** 399 * RISCVCPUClass: 400 * @parent_realize: The parent class' realize handler. 401 * @parent_phases: The parent class' reset phase handlers. 402 * 403 * A RISCV CPU model. 404 */ 405 struct RISCVCPUClass { 406 /*< private >*/ 407 CPUClass parent_class; 408 /*< public >*/ 409 DeviceRealize parent_realize; 410 ResettablePhases parent_phases; 411 }; 412 413 struct RISCVCPUConfig { 414 bool ext_i; 415 bool ext_e; 416 bool ext_g; 417 bool ext_m; 418 bool ext_a; 419 bool ext_f; 420 bool ext_d; 421 bool ext_c; 422 bool ext_s; 423 bool ext_u; 424 bool ext_h; 425 bool ext_j; 426 bool ext_v; 427 bool ext_zba; 428 bool ext_zbb; 429 bool ext_zbc; 430 bool ext_zbkb; 431 bool ext_zbkc; 432 bool ext_zbkx; 433 bool ext_zbs; 434 bool ext_zk; 435 bool ext_zkn; 436 bool ext_zknd; 437 bool ext_zkne; 438 bool ext_zknh; 439 bool ext_zkr; 440 bool ext_zks; 441 bool ext_zksed; 442 bool ext_zksh; 443 bool ext_zkt; 444 bool ext_ifencei; 445 bool ext_icsr; 446 bool ext_zihintpause; 447 bool ext_smstateen; 448 bool ext_sstc; 449 bool ext_svinval; 450 bool ext_svnapot; 451 bool ext_svpbmt; 452 bool ext_zdinx; 453 bool ext_zawrs; 454 bool ext_zfh; 455 bool ext_zfhmin; 456 bool ext_zfinx; 457 bool ext_zhinx; 458 bool ext_zhinxmin; 459 bool ext_zve32f; 460 bool ext_zve64f; 461 bool ext_zmmul; 462 bool ext_smaia; 463 bool ext_ssaia; 464 bool ext_sscofpmf; 465 bool rvv_ta_all_1s; 466 bool rvv_ma_all_1s; 467 468 uint32_t mvendorid; 469 uint64_t marchid; 470 uint64_t mimpid; 471 472 /* Vendor-specific custom extensions */ 473 bool ext_xtheadba; 474 bool ext_xtheadbb; 475 bool ext_xtheadbs; 476 bool ext_xtheadcmo; 477 bool ext_xtheadcondmov; 478 bool ext_xtheadfmemidx; 479 bool ext_xtheadfmv; 480 bool ext_xtheadmac; 481 bool ext_xtheadmemidx; 482 bool ext_xtheadmempair; 483 bool ext_xtheadsync; 484 bool ext_XVentanaCondOps; 485 486 uint8_t pmu_num; 487 char *priv_spec; 488 char *user_spec; 489 char *bext_spec; 490 char *vext_spec; 491 uint16_t vlen; 492 uint16_t elen; 493 bool mmu; 494 bool pmp; 495 bool epmp; 496 bool debug; 497 bool misa_w; 498 499 bool short_isa_string; 500 }; 501 502 typedef struct RISCVCPUConfig RISCVCPUConfig; 503 504 /** 505 * RISCVCPU: 506 * @env: #CPURISCVState 507 * 508 * A RISCV CPU. 509 */ 510 struct ArchCPU { 511 /*< private >*/ 512 CPUState parent_obj; 513 /*< public >*/ 514 CPUNegativeOffsetState neg; 515 CPURISCVState env; 516 517 char *dyn_csr_xml; 518 char *dyn_vreg_xml; 519 520 /* Configuration Settings */ 521 RISCVCPUConfig cfg; 522 523 QEMUTimer *pmu_timer; 524 /* A bitmask of Available programmable counters */ 525 uint32_t pmu_avail_ctrs; 526 /* Mapping of events to counters */ 527 GHashTable *pmu_event_ctr_map; 528 }; 529 530 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) 531 { 532 return (env->misa_ext & ext) != 0; 533 } 534 535 static inline bool riscv_feature(CPURISCVState *env, int feature) 536 { 537 return env->features & (1ULL << feature); 538 } 539 540 static inline void riscv_set_feature(CPURISCVState *env, int feature) 541 { 542 env->features |= (1ULL << feature); 543 } 544 545 #include "cpu_user.h" 546 547 extern const char * const riscv_int_regnames[]; 548 extern const char * const riscv_int_regnamesh[]; 549 extern const char * const riscv_fpr_regnames[]; 550 551 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); 552 void riscv_cpu_do_interrupt(CPUState *cpu); 553 int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 554 int cpuid, DumpState *s); 555 int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 556 int cpuid, DumpState *s); 557 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 558 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 559 int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero); 560 uint8_t riscv_cpu_default_priority(int irq); 561 uint64_t riscv_cpu_all_pending(CPURISCVState *env); 562 int riscv_cpu_mirq_pending(CPURISCVState *env); 563 int riscv_cpu_sirq_pending(CPURISCVState *env); 564 int riscv_cpu_vsirq_pending(CPURISCVState *env); 565 bool riscv_cpu_fp_enabled(CPURISCVState *env); 566 target_ulong riscv_cpu_get_geilen(CPURISCVState *env); 567 void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); 568 bool riscv_cpu_vector_enabled(CPURISCVState *env); 569 bool riscv_cpu_virt_enabled(CPURISCVState *env); 570 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); 571 bool riscv_cpu_two_stage_lookup(int mmu_idx); 572 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); 573 G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 574 MMUAccessType access_type, int mmu_idx, 575 uintptr_t retaddr); 576 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 577 MMUAccessType access_type, int mmu_idx, 578 bool probe, uintptr_t retaddr); 579 char *riscv_isa_string(RISCVCPU *cpu); 580 void riscv_cpu_list(void); 581 582 #define cpu_list riscv_cpu_list 583 #define cpu_mmu_index riscv_cpu_mmu_index 584 585 #ifndef CONFIG_USER_ONLY 586 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 587 vaddr addr, unsigned size, 588 MMUAccessType access_type, 589 int mmu_idx, MemTxAttrs attrs, 590 MemTxResult response, uintptr_t retaddr); 591 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 592 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); 593 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); 594 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); 595 uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value); 596 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ 597 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), 598 void *arg); 599 void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, 600 int (*rmw_fn)(void *arg, 601 target_ulong reg, 602 target_ulong *val, 603 target_ulong new_val, 604 target_ulong write_mask), 605 void *rmw_fn_arg); 606 #endif 607 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); 608 609 void riscv_translate_init(void); 610 G_NORETURN void riscv_raise_exception(CPURISCVState *env, 611 uint32_t exception, uintptr_t pc); 612 613 target_ulong riscv_cpu_get_fflags(CPURISCVState *env); 614 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); 615 616 #define TB_FLAGS_PRIV_MMU_MASK 3 617 #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2) 618 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS 619 #define TB_FLAGS_MSTATUS_VS MSTATUS_VS 620 621 #include "exec/cpu-all.h" 622 623 FIELD(TB_FLAGS, MEM_IDX, 0, 3) 624 FIELD(TB_FLAGS, LMUL, 3, 3) 625 FIELD(TB_FLAGS, SEW, 6, 3) 626 /* Skip MSTATUS_VS (0x600) bits */ 627 FIELD(TB_FLAGS, VL_EQ_VLMAX, 11, 1) 628 FIELD(TB_FLAGS, VILL, 12, 1) 629 /* Skip MSTATUS_FS (0x6000) bits */ 630 /* Is a Hypervisor instruction load/store allowed? */ 631 FIELD(TB_FLAGS, HLSX, 15, 1) 632 FIELD(TB_FLAGS, MSTATUS_HS_FS, 16, 2) 633 FIELD(TB_FLAGS, MSTATUS_HS_VS, 18, 2) 634 /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ 635 FIELD(TB_FLAGS, XL, 20, 2) 636 /* If PointerMasking should be applied */ 637 FIELD(TB_FLAGS, PM_MASK_ENABLED, 22, 1) 638 FIELD(TB_FLAGS, PM_BASE_ENABLED, 23, 1) 639 FIELD(TB_FLAGS, VTA, 24, 1) 640 FIELD(TB_FLAGS, VMA, 25, 1) 641 /* Native debug itrigger */ 642 FIELD(TB_FLAGS, ITRIGGER, 26, 1) 643 644 #ifdef TARGET_RISCV32 645 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) 646 #else 647 static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) 648 { 649 return env->misa_mxl; 650 } 651 #endif 652 #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env))) 653 654 static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURISCVState *env) 655 { 656 return &env_archcpu(env)->cfg; 657 } 658 659 #if defined(TARGET_RISCV32) 660 #define cpu_recompute_xl(env) ((void)(env), MXL_RV32) 661 #else 662 static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) 663 { 664 RISCVMXL xl = env->misa_mxl; 665 #if !defined(CONFIG_USER_ONLY) 666 /* 667 * When emulating a 32-bit-only cpu, use RV32. 668 * When emulating a 64-bit cpu, and MXL has been reduced to RV32, 669 * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened 670 * back to RV64 for lower privs. 671 */ 672 if (xl != MXL_RV32) { 673 switch (env->priv) { 674 case PRV_M: 675 break; 676 case PRV_U: 677 xl = get_field(env->mstatus, MSTATUS64_UXL); 678 break; 679 default: /* PRV_S | PRV_H */ 680 xl = get_field(env->mstatus, MSTATUS64_SXL); 681 break; 682 } 683 } 684 #endif 685 return xl; 686 } 687 #endif 688 689 static inline int riscv_cpu_xlen(CPURISCVState *env) 690 { 691 return 16 << env->xl; 692 } 693 694 #ifdef TARGET_RISCV32 695 #define riscv_cpu_sxl(env) ((void)(env), MXL_RV32) 696 #else 697 static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env) 698 { 699 #ifdef CONFIG_USER_ONLY 700 return env->misa_mxl; 701 #else 702 return get_field(env->mstatus, MSTATUS64_SXL); 703 #endif 704 } 705 #endif 706 707 /* 708 * Encode LMUL to lmul as follows: 709 * LMUL vlmul lmul 710 * 1 000 0 711 * 2 001 1 712 * 4 010 2 713 * 8 011 3 714 * - 100 - 715 * 1/8 101 -3 716 * 1/4 110 -2 717 * 1/2 111 -1 718 * 719 * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul) 720 * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8 721 * => VLMAX = vlen >> (1 + 3 - (-3)) 722 * = 256 >> 7 723 * = 2 724 */ 725 static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) 726 { 727 uint8_t sew = FIELD_EX64(vtype, VTYPE, VSEW); 728 int8_t lmul = sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3); 729 return cpu->cfg.vlen >> (sew + 3 - lmul); 730 } 731 732 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 733 target_ulong *cs_base, uint32_t *pflags); 734 735 void riscv_cpu_update_mask(CPURISCVState *env); 736 737 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, 738 target_ulong *ret_value, 739 target_ulong new_value, target_ulong write_mask); 740 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, 741 target_ulong *ret_value, 742 target_ulong new_value, 743 target_ulong write_mask); 744 745 static inline void riscv_csr_write(CPURISCVState *env, int csrno, 746 target_ulong val) 747 { 748 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); 749 } 750 751 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) 752 { 753 target_ulong val = 0; 754 riscv_csrrw(env, csrno, &val, 0, 0); 755 return val; 756 } 757 758 typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, 759 int csrno); 760 typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, 761 target_ulong *ret_value); 762 typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, 763 target_ulong new_value); 764 typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, 765 target_ulong *ret_value, 766 target_ulong new_value, 767 target_ulong write_mask); 768 769 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, 770 Int128 *ret_value, 771 Int128 new_value, Int128 write_mask); 772 773 typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno, 774 Int128 *ret_value); 775 typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int csrno, 776 Int128 new_value); 777 778 typedef struct { 779 const char *name; 780 riscv_csr_predicate_fn predicate; 781 riscv_csr_read_fn read; 782 riscv_csr_write_fn write; 783 riscv_csr_op_fn op; 784 riscv_csr_read128_fn read128; 785 riscv_csr_write128_fn write128; 786 /* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0) */ 787 uint32_t min_priv_ver; 788 } riscv_csr_operations; 789 790 /* CSR function table constants */ 791 enum { 792 CSR_TABLE_SIZE = 0x1000 793 }; 794 795 /** 796 * The event id are encoded based on the encoding specified in the 797 * SBI specification v0.3 798 */ 799 800 enum riscv_pmu_event_idx { 801 RISCV_PMU_EVENT_HW_CPU_CYCLES = 0x01, 802 RISCV_PMU_EVENT_HW_INSTRUCTIONS = 0x02, 803 RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS = 0x10019, 804 RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS = 0x1001B, 805 RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS = 0x10021, 806 }; 807 808 /* CSR function table */ 809 extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; 810 811 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); 812 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); 813 814 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); 815 816 #endif /* RISCV_CPU_H */ 817