1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef RISCV_CPU_H 21 #define RISCV_CPU_H 22 23 #include "hw/core/cpu.h" 24 #include "hw/registerfields.h" 25 #include "exec/cpu-defs.h" 26 #include "qemu/cpu-float.h" 27 #include "qom/object.h" 28 #include "qemu/int128.h" 29 #include "cpu_bits.h" 30 31 #define TCG_GUEST_DEFAULT_MO 0 32 33 /* 34 * RISC-V-specific extra insn start words: 35 * 1: Original instruction opcode 36 */ 37 #define TARGET_INSN_START_EXTRA_WORDS 1 38 39 #define TYPE_RISCV_CPU "riscv-cpu" 40 41 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU 42 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) 43 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU 44 45 #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") 46 #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") 47 #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") 48 #define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128") 49 #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") 50 #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") 51 #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") 52 #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") 53 #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") 54 #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") 55 #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") 56 #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") 57 58 #if defined(TARGET_RISCV32) 59 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 60 #elif defined(TARGET_RISCV64) 61 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 62 #endif 63 64 #define RV(x) ((target_ulong)1 << (x - 'A')) 65 66 #define RVI RV('I') 67 #define RVE RV('E') /* E and I are mutually exclusive */ 68 #define RVM RV('M') 69 #define RVA RV('A') 70 #define RVF RV('F') 71 #define RVD RV('D') 72 #define RVV RV('V') 73 #define RVC RV('C') 74 #define RVS RV('S') 75 #define RVU RV('U') 76 #define RVH RV('H') 77 #define RVJ RV('J') 78 79 /* S extension denotes that Supervisor mode exists, however it is possible 80 to have a core that support S mode but does not have an MMU and there 81 is currently no bit in misa to indicate whether an MMU exists or not 82 so a cpu features bitfield is required, likewise for optional PMP support */ 83 enum { 84 RISCV_FEATURE_MMU, 85 RISCV_FEATURE_PMP, 86 RISCV_FEATURE_EPMP, 87 RISCV_FEATURE_MISA, 88 RISCV_FEATURE_DEBUG 89 }; 90 91 /* Privileged specification version */ 92 enum { 93 PRIV_VERSION_1_10_0 = 0, 94 PRIV_VERSION_1_11_0, 95 PRIV_VERSION_1_12_0, 96 }; 97 98 #define VEXT_VERSION_1_00_0 0x00010000 99 100 enum { 101 TRANSLATE_SUCCESS, 102 TRANSLATE_FAIL, 103 TRANSLATE_PMP_FAIL, 104 TRANSLATE_G_STAGE_FAIL 105 }; 106 107 #define MMU_USER_IDX 3 108 109 #define MAX_RISCV_PMPS (16) 110 111 typedef struct CPUArchState CPURISCVState; 112 113 #if !defined(CONFIG_USER_ONLY) 114 #include "pmp.h" 115 #include "debug.h" 116 #endif 117 118 #define RV_VLEN_MAX 1024 119 #define RV_MAX_MHPMEVENTS 32 120 #define RV_MAX_MHPMCOUNTERS 32 121 122 FIELD(VTYPE, VLMUL, 0, 3) 123 FIELD(VTYPE, VSEW, 3, 3) 124 FIELD(VTYPE, VTA, 6, 1) 125 FIELD(VTYPE, VMA, 7, 1) 126 FIELD(VTYPE, VEDIV, 8, 2) 127 FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) 128 129 typedef struct PMUCTRState { 130 /* Current value of a counter */ 131 target_ulong mhpmcounter_val; 132 /* Current value of a counter in RV32*/ 133 target_ulong mhpmcounterh_val; 134 /* Snapshot values of counter */ 135 target_ulong mhpmcounter_prev; 136 /* Snapshort value of a counter in RV32 */ 137 target_ulong mhpmcounterh_prev; 138 bool started; 139 } PMUCTRState; 140 141 struct CPUArchState { 142 target_ulong gpr[32]; 143 target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ 144 uint64_t fpr[32]; /* assume both F and D extensions */ 145 146 /* vector coprocessor state. */ 147 uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); 148 target_ulong vxrm; 149 target_ulong vxsat; 150 target_ulong vl; 151 target_ulong vstart; 152 target_ulong vtype; 153 bool vill; 154 155 target_ulong pc; 156 target_ulong load_res; 157 target_ulong load_val; 158 159 target_ulong frm; 160 161 target_ulong badaddr; 162 target_ulong bins; 163 164 target_ulong guest_phys_fault_addr; 165 166 target_ulong priv_ver; 167 target_ulong bext_ver; 168 target_ulong vext_ver; 169 170 /* RISCVMXL, but uint32_t for vmstate migration */ 171 uint32_t misa_mxl; /* current mxl */ 172 uint32_t misa_mxl_max; /* max mxl for this cpu */ 173 uint32_t misa_ext; /* current extensions */ 174 uint32_t misa_ext_mask; /* max ext for this cpu */ 175 uint32_t xl; /* current xlen */ 176 177 /* 128-bit helpers upper part return value */ 178 target_ulong retxh; 179 180 uint32_t features; 181 182 #ifdef CONFIG_USER_ONLY 183 uint32_t elf_flags; 184 #endif 185 186 #ifndef CONFIG_USER_ONLY 187 target_ulong priv; 188 /* This contains QEMU specific information about the virt state. */ 189 target_ulong virt; 190 target_ulong geilen; 191 target_ulong resetvec; 192 193 target_ulong mhartid; 194 /* 195 * For RV32 this is 32-bit mstatus and 32-bit mstatush. 196 * For RV64 this is a 64-bit mstatus. 197 */ 198 uint64_t mstatus; 199 200 uint64_t mip; 201 /* 202 * MIP contains the software writable version of SEIP ORed with the 203 * external interrupt value. The MIP register is always up-to-date. 204 * To keep track of the current source, we also save booleans of the values 205 * here. 206 */ 207 bool external_seip; 208 bool software_seip; 209 210 uint64_t miclaim; 211 212 uint64_t mie; 213 uint64_t mideleg; 214 215 target_ulong satp; /* since: priv-1.10.0 */ 216 target_ulong stval; 217 target_ulong medeleg; 218 219 target_ulong stvec; 220 target_ulong sepc; 221 target_ulong scause; 222 223 target_ulong mtvec; 224 target_ulong mepc; 225 target_ulong mcause; 226 target_ulong mtval; /* since: priv-1.10.0 */ 227 228 /* Machine and Supervisor interrupt priorities */ 229 uint8_t miprio[64]; 230 uint8_t siprio[64]; 231 232 /* AIA CSRs */ 233 target_ulong miselect; 234 target_ulong siselect; 235 236 /* Hypervisor CSRs */ 237 target_ulong hstatus; 238 target_ulong hedeleg; 239 uint64_t hideleg; 240 target_ulong hcounteren; 241 target_ulong htval; 242 target_ulong htinst; 243 target_ulong hgatp; 244 target_ulong hgeie; 245 target_ulong hgeip; 246 uint64_t htimedelta; 247 248 /* Hypervisor controlled virtual interrupt priorities */ 249 target_ulong hvictl; 250 uint8_t hviprio[64]; 251 252 /* Upper 64-bits of 128-bit CSRs */ 253 uint64_t mscratchh; 254 uint64_t sscratchh; 255 256 /* Virtual CSRs */ 257 /* 258 * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. 259 * For RV64 this is a 64-bit vsstatus. 260 */ 261 uint64_t vsstatus; 262 target_ulong vstvec; 263 target_ulong vsscratch; 264 target_ulong vsepc; 265 target_ulong vscause; 266 target_ulong vstval; 267 target_ulong vsatp; 268 269 /* AIA VS-mode CSRs */ 270 target_ulong vsiselect; 271 272 target_ulong mtval2; 273 target_ulong mtinst; 274 275 /* HS Backup CSRs */ 276 target_ulong stvec_hs; 277 target_ulong sscratch_hs; 278 target_ulong sepc_hs; 279 target_ulong scause_hs; 280 target_ulong stval_hs; 281 target_ulong satp_hs; 282 uint64_t mstatus_hs; 283 284 /* Signals whether the current exception occurred with two-stage address 285 translation active. */ 286 bool two_stage_lookup; 287 /* 288 * Signals whether the current exception occurred while doing two-stage 289 * address translation for the VS-stage page table walk. 290 */ 291 bool two_stage_indirect_lookup; 292 293 target_ulong scounteren; 294 target_ulong mcounteren; 295 296 target_ulong mcountinhibit; 297 298 /* PMU counter state */ 299 PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS]; 300 301 /* PMU event selector configured values. First three are unused*/ 302 target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS]; 303 304 target_ulong sscratch; 305 target_ulong mscratch; 306 307 /* temporary htif regs */ 308 uint64_t mfromhost; 309 uint64_t mtohost; 310 311 /* Sstc CSRs */ 312 uint64_t stimecmp; 313 314 uint64_t vstimecmp; 315 316 /* physical memory protection */ 317 pmp_table_t pmp_state; 318 target_ulong mseccfg; 319 320 /* trigger module */ 321 target_ulong trigger_cur; 322 type2_trigger_t type2_trig[TRIGGER_TYPE2_NUM]; 323 324 /* machine specific rdtime callback */ 325 uint64_t (*rdtime_fn)(void *); 326 void *rdtime_fn_arg; 327 328 /* machine specific AIA ireg read-modify-write callback */ 329 #define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \ 330 ((((__xlen) & 0xff) << 24) | \ 331 (((__vgein) & 0x3f) << 20) | \ 332 (((__virt) & 0x1) << 18) | \ 333 (((__priv) & 0x3) << 16) | \ 334 (__isel & 0xffff)) 335 #define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff) 336 #define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3) 337 #define AIA_IREG_VIRT(__ireg) (((__ireg) >> 18) & 0x1) 338 #define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 20) & 0x3f) 339 #define AIA_IREG_XLEN(__ireg) (((__ireg) >> 24) & 0xff) 340 int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg, 341 target_ulong *val, target_ulong new_val, target_ulong write_mask); 342 void *aia_ireg_rmw_fn_arg[4]; 343 344 /* True if in debugger mode. */ 345 bool debugger; 346 347 /* 348 * CSRs for PointerMasking extension 349 */ 350 target_ulong mmte; 351 target_ulong mpmmask; 352 target_ulong mpmbase; 353 target_ulong spmmask; 354 target_ulong spmbase; 355 target_ulong upmmask; 356 target_ulong upmbase; 357 358 /* CSRs for execution enviornment configuration */ 359 uint64_t menvcfg; 360 target_ulong senvcfg; 361 uint64_t henvcfg; 362 #endif 363 target_ulong cur_pmmask; 364 target_ulong cur_pmbase; 365 366 float_status fp_status; 367 368 /* Fields from here on are preserved across CPU reset. */ 369 QEMUTimer *stimer; /* Internal timer for S-mode interrupt */ 370 QEMUTimer *vstimer; /* Internal timer for VS-mode interrupt */ 371 bool vstime_irq; 372 373 hwaddr kernel_addr; 374 hwaddr fdt_addr; 375 376 /* kvm timer */ 377 bool kvm_timer_dirty; 378 uint64_t kvm_timer_time; 379 uint64_t kvm_timer_compare; 380 uint64_t kvm_timer_state; 381 uint64_t kvm_timer_frequency; 382 }; 383 384 OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) 385 386 /** 387 * RISCVCPUClass: 388 * @parent_realize: The parent class' realize handler. 389 * @parent_reset: The parent class' reset handler. 390 * 391 * A RISCV CPU model. 392 */ 393 struct RISCVCPUClass { 394 /*< private >*/ 395 CPUClass parent_class; 396 /*< public >*/ 397 DeviceRealize parent_realize; 398 DeviceReset parent_reset; 399 }; 400 401 struct RISCVCPUConfig { 402 bool ext_i; 403 bool ext_e; 404 bool ext_g; 405 bool ext_m; 406 bool ext_a; 407 bool ext_f; 408 bool ext_d; 409 bool ext_c; 410 bool ext_s; 411 bool ext_u; 412 bool ext_h; 413 bool ext_j; 414 bool ext_v; 415 bool ext_zba; 416 bool ext_zbb; 417 bool ext_zbc; 418 bool ext_zbkb; 419 bool ext_zbkc; 420 bool ext_zbkx; 421 bool ext_zbs; 422 bool ext_zk; 423 bool ext_zkn; 424 bool ext_zknd; 425 bool ext_zkne; 426 bool ext_zknh; 427 bool ext_zkr; 428 bool ext_zks; 429 bool ext_zksed; 430 bool ext_zksh; 431 bool ext_zkt; 432 bool ext_ifencei; 433 bool ext_icsr; 434 bool ext_zihintpause; 435 bool ext_sstc; 436 bool ext_svinval; 437 bool ext_svnapot; 438 bool ext_svpbmt; 439 bool ext_zdinx; 440 bool ext_zfh; 441 bool ext_zfhmin; 442 bool ext_zfinx; 443 bool ext_zhinx; 444 bool ext_zhinxmin; 445 bool ext_zve32f; 446 bool ext_zve64f; 447 bool ext_zmmul; 448 bool ext_smaia; 449 bool ext_ssaia; 450 bool rvv_ta_all_1s; 451 bool rvv_ma_all_1s; 452 453 uint32_t mvendorid; 454 uint64_t marchid; 455 uint64_t mimpid; 456 457 /* Vendor-specific custom extensions */ 458 bool ext_XVentanaCondOps; 459 460 uint8_t pmu_num; 461 char *priv_spec; 462 char *user_spec; 463 char *bext_spec; 464 char *vext_spec; 465 uint16_t vlen; 466 uint16_t elen; 467 bool mmu; 468 bool pmp; 469 bool epmp; 470 bool debug; 471 uint64_t resetvec; 472 473 bool short_isa_string; 474 }; 475 476 typedef struct RISCVCPUConfig RISCVCPUConfig; 477 478 /** 479 * RISCVCPU: 480 * @env: #CPURISCVState 481 * 482 * A RISCV CPU. 483 */ 484 struct ArchCPU { 485 /*< private >*/ 486 CPUState parent_obj; 487 /*< public >*/ 488 CPUNegativeOffsetState neg; 489 CPURISCVState env; 490 491 char *dyn_csr_xml; 492 char *dyn_vreg_xml; 493 494 /* Configuration Settings */ 495 RISCVCPUConfig cfg; 496 }; 497 498 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) 499 { 500 return (env->misa_ext & ext) != 0; 501 } 502 503 static inline bool riscv_feature(CPURISCVState *env, int feature) 504 { 505 return env->features & (1ULL << feature); 506 } 507 508 static inline void riscv_set_feature(CPURISCVState *env, int feature) 509 { 510 env->features |= (1ULL << feature); 511 } 512 513 #include "cpu_user.h" 514 515 extern const char * const riscv_int_regnames[]; 516 extern const char * const riscv_int_regnamesh[]; 517 extern const char * const riscv_fpr_regnames[]; 518 519 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); 520 void riscv_cpu_do_interrupt(CPUState *cpu); 521 int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 522 int cpuid, void *opaque); 523 int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 524 int cpuid, void *opaque); 525 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 526 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 527 int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero); 528 uint8_t riscv_cpu_default_priority(int irq); 529 uint64_t riscv_cpu_all_pending(CPURISCVState *env); 530 int riscv_cpu_mirq_pending(CPURISCVState *env); 531 int riscv_cpu_sirq_pending(CPURISCVState *env); 532 int riscv_cpu_vsirq_pending(CPURISCVState *env); 533 bool riscv_cpu_fp_enabled(CPURISCVState *env); 534 target_ulong riscv_cpu_get_geilen(CPURISCVState *env); 535 void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); 536 bool riscv_cpu_vector_enabled(CPURISCVState *env); 537 bool riscv_cpu_virt_enabled(CPURISCVState *env); 538 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); 539 bool riscv_cpu_two_stage_lookup(int mmu_idx); 540 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); 541 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 542 G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 543 MMUAccessType access_type, int mmu_idx, 544 uintptr_t retaddr); 545 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 546 MMUAccessType access_type, int mmu_idx, 547 bool probe, uintptr_t retaddr); 548 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 549 vaddr addr, unsigned size, 550 MMUAccessType access_type, 551 int mmu_idx, MemTxAttrs attrs, 552 MemTxResult response, uintptr_t retaddr); 553 char *riscv_isa_string(RISCVCPU *cpu); 554 void riscv_cpu_list(void); 555 556 #define cpu_list riscv_cpu_list 557 #define cpu_mmu_index riscv_cpu_mmu_index 558 559 #ifndef CONFIG_USER_ONLY 560 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); 561 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); 562 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); 563 uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value); 564 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ 565 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), 566 void *arg); 567 void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, 568 int (*rmw_fn)(void *arg, 569 target_ulong reg, 570 target_ulong *val, 571 target_ulong new_val, 572 target_ulong write_mask), 573 void *rmw_fn_arg); 574 #endif 575 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); 576 577 void riscv_translate_init(void); 578 G_NORETURN void riscv_raise_exception(CPURISCVState *env, 579 uint32_t exception, uintptr_t pc); 580 581 target_ulong riscv_cpu_get_fflags(CPURISCVState *env); 582 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); 583 584 #define TB_FLAGS_PRIV_MMU_MASK 3 585 #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2) 586 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS 587 #define TB_FLAGS_MSTATUS_VS MSTATUS_VS 588 589 #include "exec/cpu-all.h" 590 591 FIELD(TB_FLAGS, MEM_IDX, 0, 3) 592 FIELD(TB_FLAGS, LMUL, 3, 3) 593 FIELD(TB_FLAGS, SEW, 6, 3) 594 /* Skip MSTATUS_VS (0x600) bits */ 595 FIELD(TB_FLAGS, VL_EQ_VLMAX, 11, 1) 596 FIELD(TB_FLAGS, VILL, 12, 1) 597 /* Skip MSTATUS_FS (0x6000) bits */ 598 /* Is a Hypervisor instruction load/store allowed? */ 599 FIELD(TB_FLAGS, HLSX, 15, 1) 600 FIELD(TB_FLAGS, MSTATUS_HS_FS, 16, 2) 601 FIELD(TB_FLAGS, MSTATUS_HS_VS, 18, 2) 602 /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ 603 FIELD(TB_FLAGS, XL, 20, 2) 604 /* If PointerMasking should be applied */ 605 FIELD(TB_FLAGS, PM_MASK_ENABLED, 22, 1) 606 FIELD(TB_FLAGS, PM_BASE_ENABLED, 23, 1) 607 FIELD(TB_FLAGS, VTA, 24, 1) 608 FIELD(TB_FLAGS, VMA, 25, 1) 609 610 #ifdef TARGET_RISCV32 611 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) 612 #else 613 static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) 614 { 615 return env->misa_mxl; 616 } 617 #endif 618 #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env))) 619 620 #if defined(TARGET_RISCV32) 621 #define cpu_recompute_xl(env) ((void)(env), MXL_RV32) 622 #else 623 static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) 624 { 625 RISCVMXL xl = env->misa_mxl; 626 #if !defined(CONFIG_USER_ONLY) 627 /* 628 * When emulating a 32-bit-only cpu, use RV32. 629 * When emulating a 64-bit cpu, and MXL has been reduced to RV32, 630 * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened 631 * back to RV64 for lower privs. 632 */ 633 if (xl != MXL_RV32) { 634 switch (env->priv) { 635 case PRV_M: 636 break; 637 case PRV_U: 638 xl = get_field(env->mstatus, MSTATUS64_UXL); 639 break; 640 default: /* PRV_S | PRV_H */ 641 xl = get_field(env->mstatus, MSTATUS64_SXL); 642 break; 643 } 644 } 645 #endif 646 return xl; 647 } 648 #endif 649 650 static inline int riscv_cpu_xlen(CPURISCVState *env) 651 { 652 return 16 << env->xl; 653 } 654 655 #ifdef TARGET_RISCV32 656 #define riscv_cpu_sxl(env) ((void)(env), MXL_RV32) 657 #else 658 static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env) 659 { 660 #ifdef CONFIG_USER_ONLY 661 return env->misa_mxl; 662 #else 663 return get_field(env->mstatus, MSTATUS64_SXL); 664 #endif 665 } 666 #endif 667 668 /* 669 * Encode LMUL to lmul as follows: 670 * LMUL vlmul lmul 671 * 1 000 0 672 * 2 001 1 673 * 4 010 2 674 * 8 011 3 675 * - 100 - 676 * 1/8 101 -3 677 * 1/4 110 -2 678 * 1/2 111 -1 679 * 680 * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul) 681 * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8 682 * => VLMAX = vlen >> (1 + 3 - (-3)) 683 * = 256 >> 7 684 * = 2 685 */ 686 static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) 687 { 688 uint8_t sew = FIELD_EX64(vtype, VTYPE, VSEW); 689 int8_t lmul = sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3); 690 return cpu->cfg.vlen >> (sew + 3 - lmul); 691 } 692 693 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 694 target_ulong *cs_base, uint32_t *pflags); 695 696 void riscv_cpu_update_mask(CPURISCVState *env); 697 698 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, 699 target_ulong *ret_value, 700 target_ulong new_value, target_ulong write_mask); 701 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, 702 target_ulong *ret_value, 703 target_ulong new_value, 704 target_ulong write_mask); 705 706 static inline void riscv_csr_write(CPURISCVState *env, int csrno, 707 target_ulong val) 708 { 709 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); 710 } 711 712 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) 713 { 714 target_ulong val = 0; 715 riscv_csrrw(env, csrno, &val, 0, 0); 716 return val; 717 } 718 719 typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, 720 int csrno); 721 typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, 722 target_ulong *ret_value); 723 typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, 724 target_ulong new_value); 725 typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, 726 target_ulong *ret_value, 727 target_ulong new_value, 728 target_ulong write_mask); 729 730 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, 731 Int128 *ret_value, 732 Int128 new_value, Int128 write_mask); 733 734 typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno, 735 Int128 *ret_value); 736 typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int csrno, 737 Int128 new_value); 738 739 typedef struct { 740 const char *name; 741 riscv_csr_predicate_fn predicate; 742 riscv_csr_read_fn read; 743 riscv_csr_write_fn write; 744 riscv_csr_op_fn op; 745 riscv_csr_read128_fn read128; 746 riscv_csr_write128_fn write128; 747 /* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0) */ 748 uint32_t min_priv_ver; 749 } riscv_csr_operations; 750 751 /* CSR function table constants */ 752 enum { 753 CSR_TABLE_SIZE = 0x1000 754 }; 755 756 /* CSR function table */ 757 extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; 758 759 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); 760 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); 761 762 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); 763 764 #endif /* RISCV_CPU_H */ 765