1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef RISCV_CPU_H 21 #define RISCV_CPU_H 22 23 #include "hw/core/cpu.h" 24 #include "hw/registerfields.h" 25 #include "exec/cpu-defs.h" 26 #include "qemu/cpu-float.h" 27 #include "qom/object.h" 28 #include "qemu/int128.h" 29 #include "cpu_bits.h" 30 31 #define TCG_GUEST_DEFAULT_MO 0 32 33 /* 34 * RISC-V-specific extra insn start words: 35 * 1: Original instruction opcode 36 */ 37 #define TARGET_INSN_START_EXTRA_WORDS 1 38 39 #define TYPE_RISCV_CPU "riscv-cpu" 40 41 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU 42 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) 43 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU 44 45 #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") 46 #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") 47 #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") 48 #define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128") 49 #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") 50 #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") 51 #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") 52 #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") 53 #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") 54 #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") 55 #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") 56 #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") 57 58 #if defined(TARGET_RISCV32) 59 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 60 #elif defined(TARGET_RISCV64) 61 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 62 #endif 63 64 #define RV(x) ((target_ulong)1 << (x - 'A')) 65 66 #define RVI RV('I') 67 #define RVE RV('E') /* E and I are mutually exclusive */ 68 #define RVM RV('M') 69 #define RVA RV('A') 70 #define RVF RV('F') 71 #define RVD RV('D') 72 #define RVV RV('V') 73 #define RVC RV('C') 74 #define RVS RV('S') 75 #define RVU RV('U') 76 #define RVH RV('H') 77 #define RVJ RV('J') 78 79 /* S extension denotes that Supervisor mode exists, however it is possible 80 to have a core that support S mode but does not have an MMU and there 81 is currently no bit in misa to indicate whether an MMU exists or not 82 so a cpu features bitfield is required, likewise for optional PMP support */ 83 enum { 84 RISCV_FEATURE_MMU, 85 RISCV_FEATURE_PMP, 86 RISCV_FEATURE_EPMP, 87 RISCV_FEATURE_MISA, 88 RISCV_FEATURE_DEBUG 89 }; 90 91 /* Privileged specification version */ 92 enum { 93 PRIV_VERSION_1_10_0 = 0, 94 PRIV_VERSION_1_11_0, 95 PRIV_VERSION_1_12_0, 96 }; 97 98 #define VEXT_VERSION_1_00_0 0x00010000 99 100 enum { 101 TRANSLATE_SUCCESS, 102 TRANSLATE_FAIL, 103 TRANSLATE_PMP_FAIL, 104 TRANSLATE_G_STAGE_FAIL 105 }; 106 107 #define MMU_USER_IDX 3 108 109 #define MAX_RISCV_PMPS (16) 110 111 typedef struct CPUArchState CPURISCVState; 112 113 #if !defined(CONFIG_USER_ONLY) 114 #include "pmp.h" 115 #include "debug.h" 116 #endif 117 118 #define RV_VLEN_MAX 1024 119 #define RV_MAX_MHPMEVENTS 32 120 #define RV_MAX_MHPMCOUNTERS 32 121 122 FIELD(VTYPE, VLMUL, 0, 3) 123 FIELD(VTYPE, VSEW, 3, 3) 124 FIELD(VTYPE, VTA, 6, 1) 125 FIELD(VTYPE, VMA, 7, 1) 126 FIELD(VTYPE, VEDIV, 8, 2) 127 FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) 128 129 typedef struct PMUCTRState { 130 /* Current value of a counter */ 131 target_ulong mhpmcounter_val; 132 /* Current value of a counter in RV32*/ 133 target_ulong mhpmcounterh_val; 134 /* Snapshot values of counter */ 135 target_ulong mhpmcounter_prev; 136 /* Snapshort value of a counter in RV32 */ 137 target_ulong mhpmcounterh_prev; 138 bool started; 139 /* Value beyond UINT32_MAX/UINT64_MAX before overflow interrupt trigger */ 140 target_ulong irq_overflow_left; 141 } PMUCTRState; 142 143 struct CPUArchState { 144 target_ulong gpr[32]; 145 target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ 146 uint64_t fpr[32]; /* assume both F and D extensions */ 147 148 /* vector coprocessor state. */ 149 uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); 150 target_ulong vxrm; 151 target_ulong vxsat; 152 target_ulong vl; 153 target_ulong vstart; 154 target_ulong vtype; 155 bool vill; 156 157 target_ulong pc; 158 target_ulong load_res; 159 target_ulong load_val; 160 161 target_ulong frm; 162 163 target_ulong badaddr; 164 target_ulong bins; 165 166 target_ulong guest_phys_fault_addr; 167 168 target_ulong priv_ver; 169 target_ulong bext_ver; 170 target_ulong vext_ver; 171 172 /* RISCVMXL, but uint32_t for vmstate migration */ 173 uint32_t misa_mxl; /* current mxl */ 174 uint32_t misa_mxl_max; /* max mxl for this cpu */ 175 uint32_t misa_ext; /* current extensions */ 176 uint32_t misa_ext_mask; /* max ext for this cpu */ 177 uint32_t xl; /* current xlen */ 178 179 /* 128-bit helpers upper part return value */ 180 target_ulong retxh; 181 182 uint32_t features; 183 184 #ifdef CONFIG_USER_ONLY 185 uint32_t elf_flags; 186 #endif 187 188 #ifndef CONFIG_USER_ONLY 189 target_ulong priv; 190 /* This contains QEMU specific information about the virt state. */ 191 target_ulong virt; 192 target_ulong geilen; 193 uint64_t resetvec; 194 195 target_ulong mhartid; 196 /* 197 * For RV32 this is 32-bit mstatus and 32-bit mstatush. 198 * For RV64 this is a 64-bit mstatus. 199 */ 200 uint64_t mstatus; 201 202 uint64_t mip; 203 /* 204 * MIP contains the software writable version of SEIP ORed with the 205 * external interrupt value. The MIP register is always up-to-date. 206 * To keep track of the current source, we also save booleans of the values 207 * here. 208 */ 209 bool external_seip; 210 bool software_seip; 211 212 uint64_t miclaim; 213 214 uint64_t mie; 215 uint64_t mideleg; 216 217 target_ulong satp; /* since: priv-1.10.0 */ 218 target_ulong stval; 219 target_ulong medeleg; 220 221 target_ulong stvec; 222 target_ulong sepc; 223 target_ulong scause; 224 225 target_ulong mtvec; 226 target_ulong mepc; 227 target_ulong mcause; 228 target_ulong mtval; /* since: priv-1.10.0 */ 229 230 /* Machine and Supervisor interrupt priorities */ 231 uint8_t miprio[64]; 232 uint8_t siprio[64]; 233 234 /* AIA CSRs */ 235 target_ulong miselect; 236 target_ulong siselect; 237 238 /* Hypervisor CSRs */ 239 target_ulong hstatus; 240 target_ulong hedeleg; 241 uint64_t hideleg; 242 target_ulong hcounteren; 243 target_ulong htval; 244 target_ulong htinst; 245 target_ulong hgatp; 246 target_ulong hgeie; 247 target_ulong hgeip; 248 uint64_t htimedelta; 249 250 /* Hypervisor controlled virtual interrupt priorities */ 251 target_ulong hvictl; 252 uint8_t hviprio[64]; 253 254 /* Upper 64-bits of 128-bit CSRs */ 255 uint64_t mscratchh; 256 uint64_t sscratchh; 257 258 /* Virtual CSRs */ 259 /* 260 * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. 261 * For RV64 this is a 64-bit vsstatus. 262 */ 263 uint64_t vsstatus; 264 target_ulong vstvec; 265 target_ulong vsscratch; 266 target_ulong vsepc; 267 target_ulong vscause; 268 target_ulong vstval; 269 target_ulong vsatp; 270 271 /* AIA VS-mode CSRs */ 272 target_ulong vsiselect; 273 274 target_ulong mtval2; 275 target_ulong mtinst; 276 277 /* HS Backup CSRs */ 278 target_ulong stvec_hs; 279 target_ulong sscratch_hs; 280 target_ulong sepc_hs; 281 target_ulong scause_hs; 282 target_ulong stval_hs; 283 target_ulong satp_hs; 284 uint64_t mstatus_hs; 285 286 /* Signals whether the current exception occurred with two-stage address 287 translation active. */ 288 bool two_stage_lookup; 289 /* 290 * Signals whether the current exception occurred while doing two-stage 291 * address translation for the VS-stage page table walk. 292 */ 293 bool two_stage_indirect_lookup; 294 295 target_ulong scounteren; 296 target_ulong mcounteren; 297 298 target_ulong mcountinhibit; 299 300 /* PMU counter state */ 301 PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS]; 302 303 /* PMU event selector configured values. First three are unused*/ 304 target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS]; 305 306 /* PMU event selector configured values for RV32*/ 307 target_ulong mhpmeventh_val[RV_MAX_MHPMEVENTS]; 308 309 target_ulong sscratch; 310 target_ulong mscratch; 311 312 /* temporary htif regs */ 313 uint64_t mfromhost; 314 uint64_t mtohost; 315 316 /* Sstc CSRs */ 317 uint64_t stimecmp; 318 319 uint64_t vstimecmp; 320 321 /* physical memory protection */ 322 pmp_table_t pmp_state; 323 target_ulong mseccfg; 324 325 /* trigger module */ 326 target_ulong trigger_cur; 327 target_ulong tdata1[RV_MAX_TRIGGERS]; 328 target_ulong tdata2[RV_MAX_TRIGGERS]; 329 target_ulong tdata3[RV_MAX_TRIGGERS]; 330 struct CPUBreakpoint *cpu_breakpoint[RV_MAX_TRIGGERS]; 331 struct CPUWatchpoint *cpu_watchpoint[RV_MAX_TRIGGERS]; 332 333 /* machine specific rdtime callback */ 334 uint64_t (*rdtime_fn)(void *); 335 void *rdtime_fn_arg; 336 337 /* machine specific AIA ireg read-modify-write callback */ 338 #define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \ 339 ((((__xlen) & 0xff) << 24) | \ 340 (((__vgein) & 0x3f) << 20) | \ 341 (((__virt) & 0x1) << 18) | \ 342 (((__priv) & 0x3) << 16) | \ 343 (__isel & 0xffff)) 344 #define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff) 345 #define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3) 346 #define AIA_IREG_VIRT(__ireg) (((__ireg) >> 18) & 0x1) 347 #define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 20) & 0x3f) 348 #define AIA_IREG_XLEN(__ireg) (((__ireg) >> 24) & 0xff) 349 int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg, 350 target_ulong *val, target_ulong new_val, target_ulong write_mask); 351 void *aia_ireg_rmw_fn_arg[4]; 352 353 /* True if in debugger mode. */ 354 bool debugger; 355 356 /* 357 * CSRs for PointerMasking extension 358 */ 359 target_ulong mmte; 360 target_ulong mpmmask; 361 target_ulong mpmbase; 362 target_ulong spmmask; 363 target_ulong spmbase; 364 target_ulong upmmask; 365 target_ulong upmbase; 366 367 /* CSRs for execution enviornment configuration */ 368 uint64_t menvcfg; 369 uint64_t mstateen[SMSTATEEN_MAX_COUNT]; 370 uint64_t hstateen[SMSTATEEN_MAX_COUNT]; 371 uint64_t sstateen[SMSTATEEN_MAX_COUNT]; 372 target_ulong senvcfg; 373 uint64_t henvcfg; 374 #endif 375 target_ulong cur_pmmask; 376 target_ulong cur_pmbase; 377 378 float_status fp_status; 379 380 /* Fields from here on are preserved across CPU reset. */ 381 QEMUTimer *stimer; /* Internal timer for S-mode interrupt */ 382 QEMUTimer *vstimer; /* Internal timer for VS-mode interrupt */ 383 bool vstime_irq; 384 385 hwaddr kernel_addr; 386 hwaddr fdt_addr; 387 388 /* kvm timer */ 389 bool kvm_timer_dirty; 390 uint64_t kvm_timer_time; 391 uint64_t kvm_timer_compare; 392 uint64_t kvm_timer_state; 393 uint64_t kvm_timer_frequency; 394 }; 395 396 OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) 397 398 /** 399 * RISCVCPUClass: 400 * @parent_realize: The parent class' realize handler. 401 * @parent_phases: The parent class' reset phase handlers. 402 * 403 * A RISCV CPU model. 404 */ 405 struct RISCVCPUClass { 406 /*< private >*/ 407 CPUClass parent_class; 408 /*< public >*/ 409 DeviceRealize parent_realize; 410 ResettablePhases parent_phases; 411 }; 412 413 struct RISCVCPUConfig { 414 bool ext_i; 415 bool ext_e; 416 bool ext_g; 417 bool ext_m; 418 bool ext_a; 419 bool ext_f; 420 bool ext_d; 421 bool ext_c; 422 bool ext_s; 423 bool ext_u; 424 bool ext_h; 425 bool ext_j; 426 bool ext_v; 427 bool ext_zba; 428 bool ext_zbb; 429 bool ext_zbc; 430 bool ext_zbkb; 431 bool ext_zbkc; 432 bool ext_zbkx; 433 bool ext_zbs; 434 bool ext_zk; 435 bool ext_zkn; 436 bool ext_zknd; 437 bool ext_zkne; 438 bool ext_zknh; 439 bool ext_zkr; 440 bool ext_zks; 441 bool ext_zksed; 442 bool ext_zksh; 443 bool ext_zkt; 444 bool ext_ifencei; 445 bool ext_icsr; 446 bool ext_zihintpause; 447 bool ext_smstateen; 448 bool ext_sstc; 449 bool ext_svinval; 450 bool ext_svnapot; 451 bool ext_svpbmt; 452 bool ext_zdinx; 453 bool ext_zfh; 454 bool ext_zfhmin; 455 bool ext_zfinx; 456 bool ext_zhinx; 457 bool ext_zhinxmin; 458 bool ext_zve32f; 459 bool ext_zve64f; 460 bool ext_zmmul; 461 bool ext_smaia; 462 bool ext_ssaia; 463 bool ext_sscofpmf; 464 bool rvv_ta_all_1s; 465 bool rvv_ma_all_1s; 466 467 uint32_t mvendorid; 468 uint64_t marchid; 469 uint64_t mimpid; 470 471 /* Vendor-specific custom extensions */ 472 bool ext_XVentanaCondOps; 473 474 uint8_t pmu_num; 475 char *priv_spec; 476 char *user_spec; 477 char *bext_spec; 478 char *vext_spec; 479 uint16_t vlen; 480 uint16_t elen; 481 bool mmu; 482 bool pmp; 483 bool epmp; 484 bool debug; 485 486 bool short_isa_string; 487 }; 488 489 typedef struct RISCVCPUConfig RISCVCPUConfig; 490 491 /** 492 * RISCVCPU: 493 * @env: #CPURISCVState 494 * 495 * A RISCV CPU. 496 */ 497 struct ArchCPU { 498 /*< private >*/ 499 CPUState parent_obj; 500 /*< public >*/ 501 CPUNegativeOffsetState neg; 502 CPURISCVState env; 503 504 char *dyn_csr_xml; 505 char *dyn_vreg_xml; 506 507 /* Configuration Settings */ 508 RISCVCPUConfig cfg; 509 510 QEMUTimer *pmu_timer; 511 /* A bitmask of Available programmable counters */ 512 uint32_t pmu_avail_ctrs; 513 /* Mapping of events to counters */ 514 GHashTable *pmu_event_ctr_map; 515 }; 516 517 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) 518 { 519 return (env->misa_ext & ext) != 0; 520 } 521 522 static inline bool riscv_feature(CPURISCVState *env, int feature) 523 { 524 return env->features & (1ULL << feature); 525 } 526 527 static inline void riscv_set_feature(CPURISCVState *env, int feature) 528 { 529 env->features |= (1ULL << feature); 530 } 531 532 #include "cpu_user.h" 533 534 extern const char * const riscv_int_regnames[]; 535 extern const char * const riscv_int_regnamesh[]; 536 extern const char * const riscv_fpr_regnames[]; 537 538 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); 539 void riscv_cpu_do_interrupt(CPUState *cpu); 540 int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 541 int cpuid, DumpState *s); 542 int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 543 int cpuid, DumpState *s); 544 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 545 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 546 int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero); 547 uint8_t riscv_cpu_default_priority(int irq); 548 uint64_t riscv_cpu_all_pending(CPURISCVState *env); 549 int riscv_cpu_mirq_pending(CPURISCVState *env); 550 int riscv_cpu_sirq_pending(CPURISCVState *env); 551 int riscv_cpu_vsirq_pending(CPURISCVState *env); 552 bool riscv_cpu_fp_enabled(CPURISCVState *env); 553 target_ulong riscv_cpu_get_geilen(CPURISCVState *env); 554 void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); 555 bool riscv_cpu_vector_enabled(CPURISCVState *env); 556 bool riscv_cpu_virt_enabled(CPURISCVState *env); 557 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); 558 bool riscv_cpu_two_stage_lookup(int mmu_idx); 559 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); 560 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 561 G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 562 MMUAccessType access_type, int mmu_idx, 563 uintptr_t retaddr); 564 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 565 MMUAccessType access_type, int mmu_idx, 566 bool probe, uintptr_t retaddr); 567 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 568 vaddr addr, unsigned size, 569 MMUAccessType access_type, 570 int mmu_idx, MemTxAttrs attrs, 571 MemTxResult response, uintptr_t retaddr); 572 char *riscv_isa_string(RISCVCPU *cpu); 573 void riscv_cpu_list(void); 574 575 #define cpu_list riscv_cpu_list 576 #define cpu_mmu_index riscv_cpu_mmu_index 577 578 #ifndef CONFIG_USER_ONLY 579 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); 580 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); 581 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); 582 uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value); 583 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ 584 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), 585 void *arg); 586 void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, 587 int (*rmw_fn)(void *arg, 588 target_ulong reg, 589 target_ulong *val, 590 target_ulong new_val, 591 target_ulong write_mask), 592 void *rmw_fn_arg); 593 #endif 594 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); 595 596 void riscv_translate_init(void); 597 G_NORETURN void riscv_raise_exception(CPURISCVState *env, 598 uint32_t exception, uintptr_t pc); 599 600 target_ulong riscv_cpu_get_fflags(CPURISCVState *env); 601 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); 602 603 #define TB_FLAGS_PRIV_MMU_MASK 3 604 #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2) 605 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS 606 #define TB_FLAGS_MSTATUS_VS MSTATUS_VS 607 608 #include "exec/cpu-all.h" 609 610 FIELD(TB_FLAGS, MEM_IDX, 0, 3) 611 FIELD(TB_FLAGS, LMUL, 3, 3) 612 FIELD(TB_FLAGS, SEW, 6, 3) 613 /* Skip MSTATUS_VS (0x600) bits */ 614 FIELD(TB_FLAGS, VL_EQ_VLMAX, 11, 1) 615 FIELD(TB_FLAGS, VILL, 12, 1) 616 /* Skip MSTATUS_FS (0x6000) bits */ 617 /* Is a Hypervisor instruction load/store allowed? */ 618 FIELD(TB_FLAGS, HLSX, 15, 1) 619 FIELD(TB_FLAGS, MSTATUS_HS_FS, 16, 2) 620 FIELD(TB_FLAGS, MSTATUS_HS_VS, 18, 2) 621 /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ 622 FIELD(TB_FLAGS, XL, 20, 2) 623 /* If PointerMasking should be applied */ 624 FIELD(TB_FLAGS, PM_MASK_ENABLED, 22, 1) 625 FIELD(TB_FLAGS, PM_BASE_ENABLED, 23, 1) 626 FIELD(TB_FLAGS, VTA, 24, 1) 627 FIELD(TB_FLAGS, VMA, 25, 1) 628 629 #ifdef TARGET_RISCV32 630 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) 631 #else 632 static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) 633 { 634 return env->misa_mxl; 635 } 636 #endif 637 #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env))) 638 639 #if defined(TARGET_RISCV32) 640 #define cpu_recompute_xl(env) ((void)(env), MXL_RV32) 641 #else 642 static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) 643 { 644 RISCVMXL xl = env->misa_mxl; 645 #if !defined(CONFIG_USER_ONLY) 646 /* 647 * When emulating a 32-bit-only cpu, use RV32. 648 * When emulating a 64-bit cpu, and MXL has been reduced to RV32, 649 * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened 650 * back to RV64 for lower privs. 651 */ 652 if (xl != MXL_RV32) { 653 switch (env->priv) { 654 case PRV_M: 655 break; 656 case PRV_U: 657 xl = get_field(env->mstatus, MSTATUS64_UXL); 658 break; 659 default: /* PRV_S | PRV_H */ 660 xl = get_field(env->mstatus, MSTATUS64_SXL); 661 break; 662 } 663 } 664 #endif 665 return xl; 666 } 667 #endif 668 669 static inline int riscv_cpu_xlen(CPURISCVState *env) 670 { 671 return 16 << env->xl; 672 } 673 674 #ifdef TARGET_RISCV32 675 #define riscv_cpu_sxl(env) ((void)(env), MXL_RV32) 676 #else 677 static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env) 678 { 679 #ifdef CONFIG_USER_ONLY 680 return env->misa_mxl; 681 #else 682 return get_field(env->mstatus, MSTATUS64_SXL); 683 #endif 684 } 685 #endif 686 687 /* 688 * Encode LMUL to lmul as follows: 689 * LMUL vlmul lmul 690 * 1 000 0 691 * 2 001 1 692 * 4 010 2 693 * 8 011 3 694 * - 100 - 695 * 1/8 101 -3 696 * 1/4 110 -2 697 * 1/2 111 -1 698 * 699 * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul) 700 * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8 701 * => VLMAX = vlen >> (1 + 3 - (-3)) 702 * = 256 >> 7 703 * = 2 704 */ 705 static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) 706 { 707 uint8_t sew = FIELD_EX64(vtype, VTYPE, VSEW); 708 int8_t lmul = sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3); 709 return cpu->cfg.vlen >> (sew + 3 - lmul); 710 } 711 712 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 713 target_ulong *cs_base, uint32_t *pflags); 714 715 void riscv_cpu_update_mask(CPURISCVState *env); 716 717 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, 718 target_ulong *ret_value, 719 target_ulong new_value, target_ulong write_mask); 720 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, 721 target_ulong *ret_value, 722 target_ulong new_value, 723 target_ulong write_mask); 724 725 static inline void riscv_csr_write(CPURISCVState *env, int csrno, 726 target_ulong val) 727 { 728 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); 729 } 730 731 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) 732 { 733 target_ulong val = 0; 734 riscv_csrrw(env, csrno, &val, 0, 0); 735 return val; 736 } 737 738 typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, 739 int csrno); 740 typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, 741 target_ulong *ret_value); 742 typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, 743 target_ulong new_value); 744 typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, 745 target_ulong *ret_value, 746 target_ulong new_value, 747 target_ulong write_mask); 748 749 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, 750 Int128 *ret_value, 751 Int128 new_value, Int128 write_mask); 752 753 typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno, 754 Int128 *ret_value); 755 typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int csrno, 756 Int128 new_value); 757 758 typedef struct { 759 const char *name; 760 riscv_csr_predicate_fn predicate; 761 riscv_csr_read_fn read; 762 riscv_csr_write_fn write; 763 riscv_csr_op_fn op; 764 riscv_csr_read128_fn read128; 765 riscv_csr_write128_fn write128; 766 /* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0) */ 767 uint32_t min_priv_ver; 768 } riscv_csr_operations; 769 770 /* CSR function table constants */ 771 enum { 772 CSR_TABLE_SIZE = 0x1000 773 }; 774 775 /** 776 * The event id are encoded based on the encoding specified in the 777 * SBI specification v0.3 778 */ 779 780 enum riscv_pmu_event_idx { 781 RISCV_PMU_EVENT_HW_CPU_CYCLES = 0x01, 782 RISCV_PMU_EVENT_HW_INSTRUCTIONS = 0x02, 783 RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS = 0x10019, 784 RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS = 0x1001B, 785 RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS = 0x10021, 786 }; 787 788 /* CSR function table */ 789 extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; 790 791 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); 792 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); 793 794 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); 795 796 #endif /* RISCV_CPU_H */ 797