1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef RISCV_CPU_H 21 #define RISCV_CPU_H 22 23 #include "hw/core/cpu.h" 24 #include "exec/cpu-defs.h" 25 #include "fpu/softfloat-types.h" 26 27 #define TCG_GUEST_DEFAULT_MO 0 28 29 #define TYPE_RISCV_CPU "riscv-cpu" 30 31 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU 32 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) 33 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU 34 35 #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") 36 #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") 37 #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") 38 #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") 39 #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") 40 #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") 41 #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") 42 /* Deprecated */ 43 #define TYPE_RISCV_CPU_RV32IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv32imacu-nommu") 44 #define TYPE_RISCV_CPU_RV32GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9.1") 45 #define TYPE_RISCV_CPU_RV32GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.10.0") 46 #define TYPE_RISCV_CPU_RV64IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv64imacu-nommu") 47 #define TYPE_RISCV_CPU_RV64GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.9.1") 48 #define TYPE_RISCV_CPU_RV64GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.10.0") 49 50 #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2)) 51 #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2)) 52 53 #if defined(TARGET_RISCV32) 54 #define RVXLEN RV32 55 #elif defined(TARGET_RISCV64) 56 #define RVXLEN RV64 57 #endif 58 59 #define RV(x) ((target_ulong)1 << (x - 'A')) 60 61 #define RVI RV('I') 62 #define RVE RV('E') /* E and I are mutually exclusive */ 63 #define RVM RV('M') 64 #define RVA RV('A') 65 #define RVF RV('F') 66 #define RVD RV('D') 67 #define RVC RV('C') 68 #define RVS RV('S') 69 #define RVU RV('U') 70 #define RVH RV('H') 71 72 /* S extension denotes that Supervisor mode exists, however it is possible 73 to have a core that support S mode but does not have an MMU and there 74 is currently no bit in misa to indicate whether an MMU exists or not 75 so a cpu features bitfield is required, likewise for optional PMP support */ 76 enum { 77 RISCV_FEATURE_MMU, 78 RISCV_FEATURE_PMP, 79 RISCV_FEATURE_MISA 80 }; 81 82 #define PRIV_VERSION_1_09_1 0x00010901 83 #define PRIV_VERSION_1_10_0 0x00011000 84 #define PRIV_VERSION_1_11_0 0x00011100 85 86 #define TRANSLATE_PMP_FAIL 2 87 #define TRANSLATE_FAIL 1 88 #define TRANSLATE_SUCCESS 0 89 #define MMU_USER_IDX 3 90 91 #define MAX_RISCV_PMPS (16) 92 93 typedef struct CPURISCVState CPURISCVState; 94 95 #include "pmp.h" 96 97 struct CPURISCVState { 98 target_ulong gpr[32]; 99 uint64_t fpr[32]; /* assume both F and D extensions */ 100 target_ulong pc; 101 target_ulong load_res; 102 target_ulong load_val; 103 104 target_ulong frm; 105 106 target_ulong badaddr; 107 target_ulong guest_phys_fault_addr; 108 109 target_ulong priv_ver; 110 target_ulong misa; 111 target_ulong misa_mask; 112 113 uint32_t features; 114 115 #ifdef CONFIG_USER_ONLY 116 uint32_t elf_flags; 117 #endif 118 119 #ifndef CONFIG_USER_ONLY 120 target_ulong priv; 121 /* This contains QEMU specific information about the virt state. */ 122 target_ulong virt; 123 target_ulong resetvec; 124 125 target_ulong mhartid; 126 target_ulong mstatus; 127 128 target_ulong mip; 129 130 uint32_t miclaim; 131 132 target_ulong mie; 133 target_ulong mideleg; 134 135 target_ulong sptbr; /* until: priv-1.9.1 */ 136 target_ulong satp; /* since: priv-1.10.0 */ 137 target_ulong sbadaddr; 138 target_ulong mbadaddr; 139 target_ulong medeleg; 140 141 target_ulong stvec; 142 target_ulong sepc; 143 target_ulong scause; 144 145 target_ulong mtvec; 146 target_ulong mepc; 147 target_ulong mcause; 148 target_ulong mtval; /* since: priv-1.10.0 */ 149 150 /* Hypervisor CSRs */ 151 target_ulong hstatus; 152 target_ulong hedeleg; 153 target_ulong hideleg; 154 target_ulong hcounteren; 155 target_ulong htval; 156 target_ulong htinst; 157 target_ulong hgatp; 158 159 /* Virtual CSRs */ 160 target_ulong vsstatus; 161 target_ulong vstvec; 162 target_ulong vsscratch; 163 target_ulong vsepc; 164 target_ulong vscause; 165 target_ulong vstval; 166 target_ulong vsatp; 167 168 target_ulong mtval2; 169 target_ulong mtinst; 170 171 /* HS Backup CSRs */ 172 target_ulong stvec_hs; 173 target_ulong sscratch_hs; 174 target_ulong sepc_hs; 175 target_ulong scause_hs; 176 target_ulong stval_hs; 177 target_ulong satp_hs; 178 target_ulong mstatus_hs; 179 180 target_ulong scounteren; 181 target_ulong mcounteren; 182 183 target_ulong sscratch; 184 target_ulong mscratch; 185 186 /* temporary htif regs */ 187 uint64_t mfromhost; 188 uint64_t mtohost; 189 uint64_t timecmp; 190 191 /* physical memory protection */ 192 pmp_table_t pmp_state; 193 194 /* True if in debugger mode. */ 195 bool debugger; 196 #endif 197 198 float_status fp_status; 199 200 /* Fields from here on are preserved across CPU reset. */ 201 QEMUTimer *timer; /* Internal timer */ 202 }; 203 204 #define RISCV_CPU_CLASS(klass) \ 205 OBJECT_CLASS_CHECK(RISCVCPUClass, (klass), TYPE_RISCV_CPU) 206 #define RISCV_CPU(obj) \ 207 OBJECT_CHECK(RISCVCPU, (obj), TYPE_RISCV_CPU) 208 #define RISCV_CPU_GET_CLASS(obj) \ 209 OBJECT_GET_CLASS(RISCVCPUClass, (obj), TYPE_RISCV_CPU) 210 211 /** 212 * RISCVCPUClass: 213 * @parent_realize: The parent class' realize handler. 214 * @parent_reset: The parent class' reset handler. 215 * 216 * A RISCV CPU model. 217 */ 218 typedef struct RISCVCPUClass { 219 /*< private >*/ 220 CPUClass parent_class; 221 /*< public >*/ 222 DeviceRealize parent_realize; 223 void (*parent_reset)(CPUState *cpu); 224 } RISCVCPUClass; 225 226 /** 227 * RISCVCPU: 228 * @env: #CPURISCVState 229 * 230 * A RISCV CPU. 231 */ 232 typedef struct RISCVCPU { 233 /*< private >*/ 234 CPUState parent_obj; 235 /*< public >*/ 236 CPUNegativeOffsetState neg; 237 CPURISCVState env; 238 239 /* Configuration Settings */ 240 struct { 241 bool ext_i; 242 bool ext_e; 243 bool ext_g; 244 bool ext_m; 245 bool ext_a; 246 bool ext_f; 247 bool ext_d; 248 bool ext_c; 249 bool ext_s; 250 bool ext_u; 251 bool ext_counters; 252 bool ext_ifencei; 253 bool ext_icsr; 254 255 char *priv_spec; 256 char *user_spec; 257 bool mmu; 258 bool pmp; 259 } cfg; 260 } RISCVCPU; 261 262 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) 263 { 264 return (env->misa & ext) != 0; 265 } 266 267 static inline bool riscv_feature(CPURISCVState *env, int feature) 268 { 269 return env->features & (1ULL << feature); 270 } 271 272 #include "cpu_user.h" 273 #include "cpu_bits.h" 274 275 extern const char * const riscv_int_regnames[]; 276 extern const char * const riscv_fpr_regnames[]; 277 extern const char * const riscv_excp_names[]; 278 extern const char * const riscv_intr_names[]; 279 280 void riscv_cpu_do_interrupt(CPUState *cpu); 281 int riscv_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 282 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 283 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); 284 bool riscv_cpu_fp_enabled(CPURISCVState *env); 285 bool riscv_cpu_virt_enabled(CPURISCVState *env); 286 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); 287 bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env); 288 void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable); 289 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); 290 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 291 void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 292 MMUAccessType access_type, int mmu_idx, 293 uintptr_t retaddr); 294 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 295 MMUAccessType access_type, int mmu_idx, 296 bool probe, uintptr_t retaddr); 297 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 298 vaddr addr, unsigned size, 299 MMUAccessType access_type, 300 int mmu_idx, MemTxAttrs attrs, 301 MemTxResult response, uintptr_t retaddr); 302 char *riscv_isa_string(RISCVCPU *cpu); 303 void riscv_cpu_list(void); 304 305 #define cpu_signal_handler riscv_cpu_signal_handler 306 #define cpu_list riscv_cpu_list 307 #define cpu_mmu_index riscv_cpu_mmu_index 308 309 #ifndef CONFIG_USER_ONLY 310 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); 311 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts); 312 uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value); 313 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ 314 #endif 315 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); 316 317 void riscv_translate_init(void); 318 int riscv_cpu_signal_handler(int host_signum, void *pinfo, void *puc); 319 void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env, 320 uint32_t exception, uintptr_t pc); 321 322 target_ulong riscv_cpu_get_fflags(CPURISCVState *env); 323 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); 324 325 #define TB_FLAGS_MMU_MASK 3 326 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS 327 328 static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 329 target_ulong *cs_base, uint32_t *flags) 330 { 331 *pc = env->pc; 332 *cs_base = 0; 333 #ifdef CONFIG_USER_ONLY 334 *flags = TB_FLAGS_MSTATUS_FS; 335 #else 336 *flags = cpu_mmu_index(env, 0); 337 if (riscv_cpu_fp_enabled(env)) { 338 *flags |= env->mstatus & MSTATUS_FS; 339 } 340 #endif 341 } 342 343 int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, 344 target_ulong new_value, target_ulong write_mask); 345 int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value, 346 target_ulong new_value, target_ulong write_mask); 347 348 static inline void riscv_csr_write(CPURISCVState *env, int csrno, 349 target_ulong val) 350 { 351 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); 352 } 353 354 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) 355 { 356 target_ulong val = 0; 357 riscv_csrrw(env, csrno, &val, 0, 0); 358 return val; 359 } 360 361 typedef int (*riscv_csr_predicate_fn)(CPURISCVState *env, int csrno); 362 typedef int (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, 363 target_ulong *ret_value); 364 typedef int (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, 365 target_ulong new_value); 366 typedef int (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, 367 target_ulong *ret_value, target_ulong new_value, target_ulong write_mask); 368 369 typedef struct { 370 riscv_csr_predicate_fn predicate; 371 riscv_csr_read_fn read; 372 riscv_csr_write_fn write; 373 riscv_csr_op_fn op; 374 } riscv_csr_operations; 375 376 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); 377 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); 378 379 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); 380 381 typedef CPURISCVState CPUArchState; 382 typedef RISCVCPU ArchCPU; 383 384 #include "exec/cpu-all.h" 385 386 #endif /* RISCV_CPU_H */ 387