1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef RISCV_CPU_H 21 #define RISCV_CPU_H 22 23 #include "hw/core/cpu.h" 24 #include "hw/registerfields.h" 25 #include "exec/cpu-defs.h" 26 #include "fpu/softfloat-types.h" 27 #include "qom/object.h" 28 #include "cpu_bits.h" 29 30 #define TCG_GUEST_DEFAULT_MO 0 31 32 #define TYPE_RISCV_CPU "riscv-cpu" 33 34 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU 35 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) 36 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU 37 38 #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") 39 #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") 40 #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") 41 #define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128") 42 #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") 43 #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") 44 #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") 45 #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") 46 #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") 47 #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") 48 #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") 49 50 #if defined(TARGET_RISCV32) 51 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 52 #elif defined(TARGET_RISCV64) 53 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 54 #endif 55 56 #define RV(x) ((target_ulong)1 << (x - 'A')) 57 58 #define RVI RV('I') 59 #define RVE RV('E') /* E and I are mutually exclusive */ 60 #define RVM RV('M') 61 #define RVA RV('A') 62 #define RVF RV('F') 63 #define RVD RV('D') 64 #define RVV RV('V') 65 #define RVC RV('C') 66 #define RVS RV('S') 67 #define RVU RV('U') 68 #define RVH RV('H') 69 #define RVJ RV('J') 70 71 /* S extension denotes that Supervisor mode exists, however it is possible 72 to have a core that support S mode but does not have an MMU and there 73 is currently no bit in misa to indicate whether an MMU exists or not 74 so a cpu features bitfield is required, likewise for optional PMP support */ 75 enum { 76 RISCV_FEATURE_MMU, 77 RISCV_FEATURE_PMP, 78 RISCV_FEATURE_EPMP, 79 RISCV_FEATURE_MISA 80 }; 81 82 #define PRIV_VERSION_1_10_0 0x00011000 83 #define PRIV_VERSION_1_11_0 0x00011100 84 85 #define VEXT_VERSION_1_00_0 0x00010000 86 87 enum { 88 TRANSLATE_SUCCESS, 89 TRANSLATE_FAIL, 90 TRANSLATE_PMP_FAIL, 91 TRANSLATE_G_STAGE_FAIL 92 }; 93 94 #define MMU_USER_IDX 3 95 96 #define MAX_RISCV_PMPS (16) 97 98 typedef struct CPURISCVState CPURISCVState; 99 100 #if !defined(CONFIG_USER_ONLY) 101 #include "pmp.h" 102 #endif 103 104 #define RV_VLEN_MAX 1024 105 106 FIELD(VTYPE, VLMUL, 0, 3) 107 FIELD(VTYPE, VSEW, 3, 3) 108 FIELD(VTYPE, VTA, 6, 1) 109 FIELD(VTYPE, VMA, 7, 1) 110 FIELD(VTYPE, VEDIV, 8, 2) 111 FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) 112 FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1) 113 114 struct CPURISCVState { 115 target_ulong gpr[32]; 116 target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ 117 uint64_t fpr[32]; /* assume both F and D extensions */ 118 119 /* vector coprocessor state. */ 120 uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); 121 target_ulong vxrm; 122 target_ulong vxsat; 123 target_ulong vl; 124 target_ulong vstart; 125 target_ulong vtype; 126 127 target_ulong pc; 128 target_ulong load_res; 129 target_ulong load_val; 130 131 target_ulong frm; 132 133 target_ulong badaddr; 134 target_ulong guest_phys_fault_addr; 135 136 target_ulong priv_ver; 137 target_ulong bext_ver; 138 target_ulong vext_ver; 139 140 /* RISCVMXL, but uint32_t for vmstate migration */ 141 uint32_t misa_mxl; /* current mxl */ 142 uint32_t misa_mxl_max; /* max mxl for this cpu */ 143 uint32_t misa_ext; /* current extensions */ 144 uint32_t misa_ext_mask; /* max ext for this cpu */ 145 146 uint32_t features; 147 148 #ifdef CONFIG_USER_ONLY 149 uint32_t elf_flags; 150 #endif 151 152 #ifndef CONFIG_USER_ONLY 153 target_ulong priv; 154 /* This contains QEMU specific information about the virt state. */ 155 target_ulong virt; 156 target_ulong resetvec; 157 158 target_ulong mhartid; 159 /* 160 * For RV32 this is 32-bit mstatus and 32-bit mstatush. 161 * For RV64 this is a 64-bit mstatus. 162 */ 163 uint64_t mstatus; 164 165 target_ulong mip; 166 167 uint32_t miclaim; 168 169 target_ulong mie; 170 target_ulong mideleg; 171 172 target_ulong satp; /* since: priv-1.10.0 */ 173 target_ulong stval; 174 target_ulong medeleg; 175 176 target_ulong stvec; 177 target_ulong sepc; 178 target_ulong scause; 179 180 target_ulong mtvec; 181 target_ulong mepc; 182 target_ulong mcause; 183 target_ulong mtval; /* since: priv-1.10.0 */ 184 185 /* Hypervisor CSRs */ 186 target_ulong hstatus; 187 target_ulong hedeleg; 188 target_ulong hideleg; 189 target_ulong hcounteren; 190 target_ulong htval; 191 target_ulong htinst; 192 target_ulong hgatp; 193 uint64_t htimedelta; 194 195 /* Virtual CSRs */ 196 /* 197 * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. 198 * For RV64 this is a 64-bit vsstatus. 199 */ 200 uint64_t vsstatus; 201 target_ulong vstvec; 202 target_ulong vsscratch; 203 target_ulong vsepc; 204 target_ulong vscause; 205 target_ulong vstval; 206 target_ulong vsatp; 207 208 target_ulong mtval2; 209 target_ulong mtinst; 210 211 /* HS Backup CSRs */ 212 target_ulong stvec_hs; 213 target_ulong sscratch_hs; 214 target_ulong sepc_hs; 215 target_ulong scause_hs; 216 target_ulong stval_hs; 217 target_ulong satp_hs; 218 uint64_t mstatus_hs; 219 220 /* Signals whether the current exception occurred with two-stage address 221 translation active. */ 222 bool two_stage_lookup; 223 224 target_ulong scounteren; 225 target_ulong mcounteren; 226 227 target_ulong sscratch; 228 target_ulong mscratch; 229 230 /* temporary htif regs */ 231 uint64_t mfromhost; 232 uint64_t mtohost; 233 uint64_t timecmp; 234 235 /* physical memory protection */ 236 pmp_table_t pmp_state; 237 target_ulong mseccfg; 238 239 /* machine specific rdtime callback */ 240 uint64_t (*rdtime_fn)(uint32_t); 241 uint32_t rdtime_fn_arg; 242 243 /* True if in debugger mode. */ 244 bool debugger; 245 246 /* 247 * CSRs for PointerMasking extension 248 */ 249 target_ulong mmte; 250 target_ulong mpmmask; 251 target_ulong mpmbase; 252 target_ulong spmmask; 253 target_ulong spmbase; 254 target_ulong upmmask; 255 target_ulong upmbase; 256 #endif 257 258 float_status fp_status; 259 260 /* Fields from here on are preserved across CPU reset. */ 261 QEMUTimer *timer; /* Internal timer */ 262 }; 263 264 OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass, 265 RISCV_CPU) 266 267 /** 268 * RISCVCPUClass: 269 * @parent_realize: The parent class' realize handler. 270 * @parent_reset: The parent class' reset handler. 271 * 272 * A RISCV CPU model. 273 */ 274 struct RISCVCPUClass { 275 /*< private >*/ 276 CPUClass parent_class; 277 /*< public >*/ 278 DeviceRealize parent_realize; 279 DeviceReset parent_reset; 280 }; 281 282 /** 283 * RISCVCPU: 284 * @env: #CPURISCVState 285 * 286 * A RISCV CPU. 287 */ 288 struct RISCVCPU { 289 /*< private >*/ 290 CPUState parent_obj; 291 /*< public >*/ 292 CPUNegativeOffsetState neg; 293 CPURISCVState env; 294 295 char *dyn_csr_xml; 296 char *dyn_vreg_xml; 297 298 /* Configuration Settings */ 299 struct { 300 bool ext_i; 301 bool ext_e; 302 bool ext_g; 303 bool ext_m; 304 bool ext_a; 305 bool ext_f; 306 bool ext_d; 307 bool ext_c; 308 bool ext_s; 309 bool ext_u; 310 bool ext_h; 311 bool ext_j; 312 bool ext_v; 313 bool ext_zba; 314 bool ext_zbb; 315 bool ext_zbc; 316 bool ext_zbs; 317 bool ext_counters; 318 bool ext_ifencei; 319 bool ext_icsr; 320 bool ext_zfh; 321 bool ext_zfhmin; 322 323 char *priv_spec; 324 char *user_spec; 325 char *bext_spec; 326 char *vext_spec; 327 uint16_t vlen; 328 uint16_t elen; 329 bool mmu; 330 bool pmp; 331 bool epmp; 332 uint64_t resetvec; 333 } cfg; 334 }; 335 336 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) 337 { 338 return (env->misa_ext & ext) != 0; 339 } 340 341 static inline bool riscv_feature(CPURISCVState *env, int feature) 342 { 343 return env->features & (1ULL << feature); 344 } 345 346 #include "cpu_user.h" 347 348 extern const char * const riscv_int_regnames[]; 349 extern const char * const riscv_int_regnamesh[]; 350 extern const char * const riscv_fpr_regnames[]; 351 352 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); 353 void riscv_cpu_do_interrupt(CPUState *cpu); 354 int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 355 int cpuid, void *opaque); 356 int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 357 int cpuid, void *opaque); 358 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 359 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 360 bool riscv_cpu_fp_enabled(CPURISCVState *env); 361 bool riscv_cpu_vector_enabled(CPURISCVState *env); 362 bool riscv_cpu_virt_enabled(CPURISCVState *env); 363 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); 364 bool riscv_cpu_two_stage_lookup(int mmu_idx); 365 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); 366 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 367 void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 368 MMUAccessType access_type, int mmu_idx, 369 uintptr_t retaddr) QEMU_NORETURN; 370 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 371 MMUAccessType access_type, int mmu_idx, 372 bool probe, uintptr_t retaddr); 373 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 374 vaddr addr, unsigned size, 375 MMUAccessType access_type, 376 int mmu_idx, MemTxAttrs attrs, 377 MemTxResult response, uintptr_t retaddr); 378 char *riscv_isa_string(RISCVCPU *cpu); 379 void riscv_cpu_list(void); 380 381 #define cpu_list riscv_cpu_list 382 #define cpu_mmu_index riscv_cpu_mmu_index 383 384 #ifndef CONFIG_USER_ONLY 385 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); 386 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); 387 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts); 388 uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value); 389 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ 390 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t), 391 uint32_t arg); 392 #endif 393 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); 394 395 void riscv_translate_init(void); 396 void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env, 397 uint32_t exception, uintptr_t pc); 398 399 target_ulong riscv_cpu_get_fflags(CPURISCVState *env); 400 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); 401 402 #define TB_FLAGS_PRIV_MMU_MASK 3 403 #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2) 404 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS 405 #define TB_FLAGS_MSTATUS_VS MSTATUS_VS 406 407 typedef CPURISCVState CPUArchState; 408 typedef RISCVCPU ArchCPU; 409 #include "exec/cpu-all.h" 410 411 FIELD(TB_FLAGS, MEM_IDX, 0, 3) 412 FIELD(TB_FLAGS, LMUL, 3, 3) 413 FIELD(TB_FLAGS, SEW, 6, 3) 414 /* Skip MSTATUS_VS (0x600) bits */ 415 FIELD(TB_FLAGS, VL_EQ_VLMAX, 11, 1) 416 FIELD(TB_FLAGS, VILL, 12, 1) 417 /* Skip MSTATUS_FS (0x6000) bits */ 418 /* Is a Hypervisor instruction load/store allowed? */ 419 FIELD(TB_FLAGS, HLSX, 15, 1) 420 FIELD(TB_FLAGS, MSTATUS_HS_FS, 16, 2) 421 FIELD(TB_FLAGS, MSTATUS_HS_VS, 18, 2) 422 /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ 423 FIELD(TB_FLAGS, XL, 20, 2) 424 /* If PointerMasking should be applied */ 425 FIELD(TB_FLAGS, PM_ENABLED, 22, 1) 426 427 #ifdef TARGET_RISCV32 428 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) 429 #else 430 static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) 431 { 432 return env->misa_mxl; 433 } 434 #endif 435 436 /* 437 * Encode LMUL to lmul as follows: 438 * LMUL vlmul lmul 439 * 1 000 0 440 * 2 001 1 441 * 4 010 2 442 * 8 011 3 443 * - 100 - 444 * 1/8 101 -3 445 * 1/4 110 -2 446 * 1/2 111 -1 447 * 448 * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul) 449 * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8 450 * => VLMAX = vlen >> (1 + 3 - (-3)) 451 * = 256 >> 7 452 * = 2 453 */ 454 static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) 455 { 456 uint8_t sew = FIELD_EX64(vtype, VTYPE, VSEW); 457 int8_t lmul = sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3); 458 return cpu->cfg.vlen >> (sew + 3 - lmul); 459 } 460 461 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 462 target_ulong *cs_base, uint32_t *pflags); 463 464 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, 465 target_ulong *ret_value, 466 target_ulong new_value, target_ulong write_mask); 467 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, 468 target_ulong *ret_value, 469 target_ulong new_value, 470 target_ulong write_mask); 471 472 static inline void riscv_csr_write(CPURISCVState *env, int csrno, 473 target_ulong val) 474 { 475 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); 476 } 477 478 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) 479 { 480 target_ulong val = 0; 481 riscv_csrrw(env, csrno, &val, 0, 0); 482 return val; 483 } 484 485 typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, 486 int csrno); 487 typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, 488 target_ulong *ret_value); 489 typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, 490 target_ulong new_value); 491 typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, 492 target_ulong *ret_value, 493 target_ulong new_value, 494 target_ulong write_mask); 495 496 typedef struct { 497 const char *name; 498 riscv_csr_predicate_fn predicate; 499 riscv_csr_read_fn read; 500 riscv_csr_write_fn write; 501 riscv_csr_op_fn op; 502 } riscv_csr_operations; 503 504 /* CSR function table constants */ 505 enum { 506 CSR_TABLE_SIZE = 0x1000 507 }; 508 509 /* CSR function table */ 510 extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; 511 512 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); 513 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); 514 515 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); 516 517 #endif /* RISCV_CPU_H */ 518