1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef RISCV_CPU_H 21 #define RISCV_CPU_H 22 23 #include "hw/core/cpu.h" 24 #include "hw/registerfields.h" 25 #include "exec/cpu-defs.h" 26 #include "fpu/softfloat-types.h" 27 #include "qom/object.h" 28 #include "qemu/int128.h" 29 #include "cpu_bits.h" 30 31 #define TCG_GUEST_DEFAULT_MO 0 32 33 #define TYPE_RISCV_CPU "riscv-cpu" 34 35 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU 36 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) 37 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU 38 39 #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") 40 #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") 41 #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") 42 #define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128") 43 #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") 44 #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") 45 #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") 46 #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") 47 #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") 48 #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") 49 #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") 50 #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") 51 52 #if defined(TARGET_RISCV32) 53 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 54 #elif defined(TARGET_RISCV64) 55 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 56 #endif 57 58 #define RV(x) ((target_ulong)1 << (x - 'A')) 59 60 #define RVI RV('I') 61 #define RVE RV('E') /* E and I are mutually exclusive */ 62 #define RVM RV('M') 63 #define RVA RV('A') 64 #define RVF RV('F') 65 #define RVD RV('D') 66 #define RVV RV('V') 67 #define RVC RV('C') 68 #define RVS RV('S') 69 #define RVU RV('U') 70 #define RVH RV('H') 71 #define RVJ RV('J') 72 73 /* S extension denotes that Supervisor mode exists, however it is possible 74 to have a core that support S mode but does not have an MMU and there 75 is currently no bit in misa to indicate whether an MMU exists or not 76 so a cpu features bitfield is required, likewise for optional PMP support */ 77 enum { 78 RISCV_FEATURE_MMU, 79 RISCV_FEATURE_PMP, 80 RISCV_FEATURE_EPMP, 81 RISCV_FEATURE_MISA 82 }; 83 84 #define PRIV_VERSION_1_10_0 0x00011000 85 #define PRIV_VERSION_1_11_0 0x00011100 86 87 #define VEXT_VERSION_1_00_0 0x00010000 88 89 enum { 90 TRANSLATE_SUCCESS, 91 TRANSLATE_FAIL, 92 TRANSLATE_PMP_FAIL, 93 TRANSLATE_G_STAGE_FAIL 94 }; 95 96 #define MMU_USER_IDX 3 97 98 #define MAX_RISCV_PMPS (16) 99 100 typedef struct CPURISCVState CPURISCVState; 101 102 #if !defined(CONFIG_USER_ONLY) 103 #include "pmp.h" 104 #endif 105 106 #define RV_VLEN_MAX 1024 107 108 FIELD(VTYPE, VLMUL, 0, 3) 109 FIELD(VTYPE, VSEW, 3, 3) 110 FIELD(VTYPE, VTA, 6, 1) 111 FIELD(VTYPE, VMA, 7, 1) 112 FIELD(VTYPE, VEDIV, 8, 2) 113 FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) 114 FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1) 115 116 struct CPURISCVState { 117 target_ulong gpr[32]; 118 target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ 119 uint64_t fpr[32]; /* assume both F and D extensions */ 120 121 /* vector coprocessor state. */ 122 uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); 123 target_ulong vxrm; 124 target_ulong vxsat; 125 target_ulong vl; 126 target_ulong vstart; 127 target_ulong vtype; 128 bool vill; 129 130 target_ulong pc; 131 target_ulong load_res; 132 target_ulong load_val; 133 134 target_ulong frm; 135 136 target_ulong badaddr; 137 uint32_t bins; 138 139 target_ulong guest_phys_fault_addr; 140 141 target_ulong priv_ver; 142 target_ulong bext_ver; 143 target_ulong vext_ver; 144 145 /* RISCVMXL, but uint32_t for vmstate migration */ 146 uint32_t misa_mxl; /* current mxl */ 147 uint32_t misa_mxl_max; /* max mxl for this cpu */ 148 uint32_t misa_ext; /* current extensions */ 149 uint32_t misa_ext_mask; /* max ext for this cpu */ 150 uint32_t xl; /* current xlen */ 151 152 /* 128-bit helpers upper part return value */ 153 target_ulong retxh; 154 155 uint32_t features; 156 157 #ifdef CONFIG_USER_ONLY 158 uint32_t elf_flags; 159 #endif 160 161 #ifndef CONFIG_USER_ONLY 162 target_ulong priv; 163 /* This contains QEMU specific information about the virt state. */ 164 target_ulong virt; 165 target_ulong resetvec; 166 167 target_ulong mhartid; 168 /* 169 * For RV32 this is 32-bit mstatus and 32-bit mstatush. 170 * For RV64 this is a 64-bit mstatus. 171 */ 172 uint64_t mstatus; 173 174 target_ulong mip; 175 176 uint32_t miclaim; 177 178 target_ulong mie; 179 target_ulong mideleg; 180 181 target_ulong satp; /* since: priv-1.10.0 */ 182 target_ulong stval; 183 target_ulong medeleg; 184 185 target_ulong stvec; 186 target_ulong sepc; 187 target_ulong scause; 188 189 target_ulong mtvec; 190 target_ulong mepc; 191 target_ulong mcause; 192 target_ulong mtval; /* since: priv-1.10.0 */ 193 194 /* Hypervisor CSRs */ 195 target_ulong hstatus; 196 target_ulong hedeleg; 197 target_ulong hideleg; 198 target_ulong hcounteren; 199 target_ulong htval; 200 target_ulong htinst; 201 target_ulong hgatp; 202 uint64_t htimedelta; 203 204 /* Upper 64-bits of 128-bit CSRs */ 205 uint64_t mscratchh; 206 uint64_t sscratchh; 207 208 /* Virtual CSRs */ 209 /* 210 * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. 211 * For RV64 this is a 64-bit vsstatus. 212 */ 213 uint64_t vsstatus; 214 target_ulong vstvec; 215 target_ulong vsscratch; 216 target_ulong vsepc; 217 target_ulong vscause; 218 target_ulong vstval; 219 target_ulong vsatp; 220 221 target_ulong mtval2; 222 target_ulong mtinst; 223 224 /* HS Backup CSRs */ 225 target_ulong stvec_hs; 226 target_ulong sscratch_hs; 227 target_ulong sepc_hs; 228 target_ulong scause_hs; 229 target_ulong stval_hs; 230 target_ulong satp_hs; 231 uint64_t mstatus_hs; 232 233 /* Signals whether the current exception occurred with two-stage address 234 translation active. */ 235 bool two_stage_lookup; 236 237 target_ulong scounteren; 238 target_ulong mcounteren; 239 240 target_ulong sscratch; 241 target_ulong mscratch; 242 243 /* temporary htif regs */ 244 uint64_t mfromhost; 245 uint64_t mtohost; 246 uint64_t timecmp; 247 248 /* physical memory protection */ 249 pmp_table_t pmp_state; 250 target_ulong mseccfg; 251 252 /* machine specific rdtime callback */ 253 uint64_t (*rdtime_fn)(uint32_t); 254 uint32_t rdtime_fn_arg; 255 256 /* True if in debugger mode. */ 257 bool debugger; 258 259 /* 260 * CSRs for PointerMasking extension 261 */ 262 target_ulong mmte; 263 target_ulong mpmmask; 264 target_ulong mpmbase; 265 target_ulong spmmask; 266 target_ulong spmbase; 267 target_ulong upmmask; 268 target_ulong upmbase; 269 #endif 270 target_ulong cur_pmmask; 271 target_ulong cur_pmbase; 272 273 float_status fp_status; 274 275 /* Fields from here on are preserved across CPU reset. */ 276 QEMUTimer *timer; /* Internal timer */ 277 278 hwaddr kernel_addr; 279 hwaddr fdt_addr; 280 281 /* kvm timer */ 282 bool kvm_timer_dirty; 283 uint64_t kvm_timer_time; 284 uint64_t kvm_timer_compare; 285 uint64_t kvm_timer_state; 286 uint64_t kvm_timer_frequency; 287 }; 288 289 OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass, 290 RISCV_CPU) 291 292 /** 293 * RISCVCPUClass: 294 * @parent_realize: The parent class' realize handler. 295 * @parent_reset: The parent class' reset handler. 296 * 297 * A RISCV CPU model. 298 */ 299 struct RISCVCPUClass { 300 /*< private >*/ 301 CPUClass parent_class; 302 /*< public >*/ 303 DeviceRealize parent_realize; 304 DeviceReset parent_reset; 305 }; 306 307 /** 308 * RISCVCPU: 309 * @env: #CPURISCVState 310 * 311 * A RISCV CPU. 312 */ 313 struct RISCVCPU { 314 /*< private >*/ 315 CPUState parent_obj; 316 /*< public >*/ 317 CPUNegativeOffsetState neg; 318 CPURISCVState env; 319 320 char *dyn_csr_xml; 321 char *dyn_vreg_xml; 322 323 /* Configuration Settings */ 324 struct { 325 bool ext_i; 326 bool ext_e; 327 bool ext_g; 328 bool ext_m; 329 bool ext_a; 330 bool ext_f; 331 bool ext_d; 332 bool ext_c; 333 bool ext_s; 334 bool ext_u; 335 bool ext_h; 336 bool ext_j; 337 bool ext_v; 338 bool ext_zba; 339 bool ext_zbb; 340 bool ext_zbc; 341 bool ext_zbs; 342 bool ext_counters; 343 bool ext_ifencei; 344 bool ext_icsr; 345 bool ext_zfh; 346 bool ext_zfhmin; 347 bool ext_zve32f; 348 bool ext_zve64f; 349 350 char *priv_spec; 351 char *user_spec; 352 char *bext_spec; 353 char *vext_spec; 354 uint16_t vlen; 355 uint16_t elen; 356 bool mmu; 357 bool pmp; 358 bool epmp; 359 uint64_t resetvec; 360 } cfg; 361 }; 362 363 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) 364 { 365 return (env->misa_ext & ext) != 0; 366 } 367 368 static inline bool riscv_feature(CPURISCVState *env, int feature) 369 { 370 return env->features & (1ULL << feature); 371 } 372 373 #include "cpu_user.h" 374 375 extern const char * const riscv_int_regnames[]; 376 extern const char * const riscv_int_regnamesh[]; 377 extern const char * const riscv_fpr_regnames[]; 378 379 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); 380 void riscv_cpu_do_interrupt(CPUState *cpu); 381 int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 382 int cpuid, void *opaque); 383 int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 384 int cpuid, void *opaque); 385 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 386 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 387 bool riscv_cpu_fp_enabled(CPURISCVState *env); 388 bool riscv_cpu_vector_enabled(CPURISCVState *env); 389 bool riscv_cpu_virt_enabled(CPURISCVState *env); 390 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); 391 bool riscv_cpu_two_stage_lookup(int mmu_idx); 392 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); 393 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 394 void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 395 MMUAccessType access_type, int mmu_idx, 396 uintptr_t retaddr) QEMU_NORETURN; 397 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 398 MMUAccessType access_type, int mmu_idx, 399 bool probe, uintptr_t retaddr); 400 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 401 vaddr addr, unsigned size, 402 MMUAccessType access_type, 403 int mmu_idx, MemTxAttrs attrs, 404 MemTxResult response, uintptr_t retaddr); 405 char *riscv_isa_string(RISCVCPU *cpu); 406 void riscv_cpu_list(void); 407 408 #define cpu_list riscv_cpu_list 409 #define cpu_mmu_index riscv_cpu_mmu_index 410 411 #ifndef CONFIG_USER_ONLY 412 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); 413 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); 414 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts); 415 uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value); 416 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ 417 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t), 418 uint32_t arg); 419 #endif 420 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); 421 422 void riscv_translate_init(void); 423 void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env, 424 uint32_t exception, uintptr_t pc); 425 426 target_ulong riscv_cpu_get_fflags(CPURISCVState *env); 427 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); 428 429 #define TB_FLAGS_PRIV_MMU_MASK 3 430 #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2) 431 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS 432 #define TB_FLAGS_MSTATUS_VS MSTATUS_VS 433 434 typedef CPURISCVState CPUArchState; 435 typedef RISCVCPU ArchCPU; 436 #include "exec/cpu-all.h" 437 438 FIELD(TB_FLAGS, MEM_IDX, 0, 3) 439 FIELD(TB_FLAGS, LMUL, 3, 3) 440 FIELD(TB_FLAGS, SEW, 6, 3) 441 /* Skip MSTATUS_VS (0x600) bits */ 442 FIELD(TB_FLAGS, VL_EQ_VLMAX, 11, 1) 443 FIELD(TB_FLAGS, VILL, 12, 1) 444 /* Skip MSTATUS_FS (0x6000) bits */ 445 /* Is a Hypervisor instruction load/store allowed? */ 446 FIELD(TB_FLAGS, HLSX, 15, 1) 447 FIELD(TB_FLAGS, MSTATUS_HS_FS, 16, 2) 448 FIELD(TB_FLAGS, MSTATUS_HS_VS, 18, 2) 449 /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ 450 FIELD(TB_FLAGS, XL, 20, 2) 451 /* If PointerMasking should be applied */ 452 FIELD(TB_FLAGS, PM_MASK_ENABLED, 22, 1) 453 FIELD(TB_FLAGS, PM_BASE_ENABLED, 23, 1) 454 455 #ifdef TARGET_RISCV32 456 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) 457 #else 458 static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) 459 { 460 return env->misa_mxl; 461 } 462 #endif 463 464 #if defined(TARGET_RISCV32) 465 #define cpu_recompute_xl(env) ((void)(env), MXL_RV32) 466 #else 467 static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) 468 { 469 RISCVMXL xl = env->misa_mxl; 470 #if !defined(CONFIG_USER_ONLY) 471 /* 472 * When emulating a 32-bit-only cpu, use RV32. 473 * When emulating a 64-bit cpu, and MXL has been reduced to RV32, 474 * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened 475 * back to RV64 for lower privs. 476 */ 477 if (xl != MXL_RV32) { 478 switch (env->priv) { 479 case PRV_M: 480 break; 481 case PRV_U: 482 xl = get_field(env->mstatus, MSTATUS64_UXL); 483 break; 484 default: /* PRV_S | PRV_H */ 485 xl = get_field(env->mstatus, MSTATUS64_SXL); 486 break; 487 } 488 } 489 #endif 490 return xl; 491 } 492 #endif 493 494 static inline int riscv_cpu_xlen(CPURISCVState *env) 495 { 496 return 16 << env->xl; 497 } 498 499 /* 500 * Encode LMUL to lmul as follows: 501 * LMUL vlmul lmul 502 * 1 000 0 503 * 2 001 1 504 * 4 010 2 505 * 8 011 3 506 * - 100 - 507 * 1/8 101 -3 508 * 1/4 110 -2 509 * 1/2 111 -1 510 * 511 * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul) 512 * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8 513 * => VLMAX = vlen >> (1 + 3 - (-3)) 514 * = 256 >> 7 515 * = 2 516 */ 517 static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) 518 { 519 uint8_t sew = FIELD_EX64(vtype, VTYPE, VSEW); 520 int8_t lmul = sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3); 521 return cpu->cfg.vlen >> (sew + 3 - lmul); 522 } 523 524 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 525 target_ulong *cs_base, uint32_t *pflags); 526 527 void riscv_cpu_update_mask(CPURISCVState *env); 528 529 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, 530 target_ulong *ret_value, 531 target_ulong new_value, target_ulong write_mask); 532 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, 533 target_ulong *ret_value, 534 target_ulong new_value, 535 target_ulong write_mask); 536 537 static inline void riscv_csr_write(CPURISCVState *env, int csrno, 538 target_ulong val) 539 { 540 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); 541 } 542 543 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) 544 { 545 target_ulong val = 0; 546 riscv_csrrw(env, csrno, &val, 0, 0); 547 return val; 548 } 549 550 typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, 551 int csrno); 552 typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, 553 target_ulong *ret_value); 554 typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, 555 target_ulong new_value); 556 typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, 557 target_ulong *ret_value, 558 target_ulong new_value, 559 target_ulong write_mask); 560 561 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, 562 Int128 *ret_value, 563 Int128 new_value, Int128 write_mask); 564 565 typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno, 566 Int128 *ret_value); 567 typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int csrno, 568 Int128 new_value); 569 570 typedef struct { 571 const char *name; 572 riscv_csr_predicate_fn predicate; 573 riscv_csr_read_fn read; 574 riscv_csr_write_fn write; 575 riscv_csr_op_fn op; 576 riscv_csr_read128_fn read128; 577 riscv_csr_write128_fn write128; 578 } riscv_csr_operations; 579 580 /* CSR function table constants */ 581 enum { 582 CSR_TABLE_SIZE = 0x1000 583 }; 584 585 /* CSR function table */ 586 extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; 587 588 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); 589 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); 590 591 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); 592 593 #endif /* RISCV_CPU_H */ 594