1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef RISCV_CPU_H 21 #define RISCV_CPU_H 22 23 #include "hw/core/cpu.h" 24 #include "hw/registerfields.h" 25 #include "hw/qdev-properties.h" 26 #include "exec/cpu-defs.h" 27 #include "qemu/cpu-float.h" 28 #include "qom/object.h" 29 #include "qemu/int128.h" 30 #include "cpu_bits.h" 31 #include "cpu_cfg.h" 32 #include "qapi/qapi-types-common.h" 33 #include "cpu-qom.h" 34 35 typedef struct CPUArchState CPURISCVState; 36 37 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU 38 39 #if defined(TARGET_RISCV32) 40 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 41 #elif defined(TARGET_RISCV64) 42 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 43 #endif 44 45 #define TCG_GUEST_DEFAULT_MO 0 46 47 /* 48 * RISC-V-specific extra insn start words: 49 * 1: Original instruction opcode 50 */ 51 #define TARGET_INSN_START_EXTRA_WORDS 1 52 53 #define RV(x) ((target_ulong)1 << (x - 'A')) 54 55 /* 56 * Update misa_bits[], misa_ext_info_arr[] and misa_ext_cfgs[] 57 * when adding new MISA bits here. 58 */ 59 #define RVI RV('I') 60 #define RVE RV('E') /* E and I are mutually exclusive */ 61 #define RVM RV('M') 62 #define RVA RV('A') 63 #define RVF RV('F') 64 #define RVD RV('D') 65 #define RVV RV('V') 66 #define RVC RV('C') 67 #define RVS RV('S') 68 #define RVU RV('U') 69 #define RVH RV('H') 70 #define RVJ RV('J') 71 #define RVG RV('G') 72 73 extern const uint32_t misa_bits[]; 74 const char *riscv_get_misa_ext_name(uint32_t bit); 75 const char *riscv_get_misa_ext_description(uint32_t bit); 76 77 #define CPU_CFG_OFFSET(_prop) offsetof(struct RISCVCPUConfig, _prop) 78 79 /* Privileged specification version */ 80 enum { 81 PRIV_VERSION_1_10_0 = 0, 82 PRIV_VERSION_1_11_0, 83 PRIV_VERSION_1_12_0, 84 85 PRIV_VERSION_LATEST = PRIV_VERSION_1_12_0, 86 }; 87 88 #define VEXT_VERSION_1_00_0 0x00010000 89 90 enum { 91 TRANSLATE_SUCCESS, 92 TRANSLATE_FAIL, 93 TRANSLATE_PMP_FAIL, 94 TRANSLATE_G_STAGE_FAIL 95 }; 96 97 /* Extension context status */ 98 typedef enum { 99 EXT_STATUS_DISABLED = 0, 100 EXT_STATUS_INITIAL, 101 EXT_STATUS_CLEAN, 102 EXT_STATUS_DIRTY, 103 } RISCVExtStatus; 104 105 #define MMU_USER_IDX 3 106 107 #define MAX_RISCV_PMPS (16) 108 109 #if !defined(CONFIG_USER_ONLY) 110 #include "pmp.h" 111 #include "debug.h" 112 #endif 113 114 #define RV_VLEN_MAX 1024 115 #define RV_MAX_MHPMEVENTS 32 116 #define RV_MAX_MHPMCOUNTERS 32 117 118 FIELD(VTYPE, VLMUL, 0, 3) 119 FIELD(VTYPE, VSEW, 3, 3) 120 FIELD(VTYPE, VTA, 6, 1) 121 FIELD(VTYPE, VMA, 7, 1) 122 FIELD(VTYPE, VEDIV, 8, 2) 123 FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) 124 125 typedef struct PMUCTRState { 126 /* Current value of a counter */ 127 target_ulong mhpmcounter_val; 128 /* Current value of a counter in RV32 */ 129 target_ulong mhpmcounterh_val; 130 /* Snapshot values of counter */ 131 target_ulong mhpmcounter_prev; 132 /* Snapshort value of a counter in RV32 */ 133 target_ulong mhpmcounterh_prev; 134 bool started; 135 /* Value beyond UINT32_MAX/UINT64_MAX before overflow interrupt trigger */ 136 target_ulong irq_overflow_left; 137 } PMUCTRState; 138 139 struct CPUArchState { 140 target_ulong gpr[32]; 141 target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ 142 143 /* vector coprocessor state. */ 144 uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); 145 target_ulong vxrm; 146 target_ulong vxsat; 147 target_ulong vl; 148 target_ulong vstart; 149 target_ulong vtype; 150 bool vill; 151 152 target_ulong pc; 153 target_ulong load_res; 154 target_ulong load_val; 155 156 /* Floating-Point state */ 157 uint64_t fpr[32]; /* assume both F and D extensions */ 158 target_ulong frm; 159 float_status fp_status; 160 161 target_ulong badaddr; 162 target_ulong bins; 163 164 target_ulong guest_phys_fault_addr; 165 166 target_ulong priv_ver; 167 target_ulong bext_ver; 168 target_ulong vext_ver; 169 170 /* RISCVMXL, but uint32_t for vmstate migration */ 171 uint32_t misa_mxl; /* current mxl */ 172 uint32_t misa_mxl_max; /* max mxl for this cpu */ 173 uint32_t misa_ext; /* current extensions */ 174 uint32_t misa_ext_mask; /* max ext for this cpu */ 175 uint32_t xl; /* current xlen */ 176 177 /* 128-bit helpers upper part return value */ 178 target_ulong retxh; 179 180 target_ulong jvt; 181 182 #ifdef CONFIG_USER_ONLY 183 uint32_t elf_flags; 184 #endif 185 186 #ifndef CONFIG_USER_ONLY 187 target_ulong priv; 188 /* This contains QEMU specific information about the virt state. */ 189 bool virt_enabled; 190 target_ulong geilen; 191 uint64_t resetvec; 192 193 target_ulong mhartid; 194 /* 195 * For RV32 this is 32-bit mstatus and 32-bit mstatush. 196 * For RV64 this is a 64-bit mstatus. 197 */ 198 uint64_t mstatus; 199 200 uint64_t mip; 201 /* 202 * MIP contains the software writable version of SEIP ORed with the 203 * external interrupt value. The MIP register is always up-to-date. 204 * To keep track of the current source, we also save booleans of the values 205 * here. 206 */ 207 bool external_seip; 208 bool software_seip; 209 210 uint64_t miclaim; 211 212 uint64_t mie; 213 uint64_t mideleg; 214 215 /* 216 * When mideleg[i]=0 and mvien[i]=1, sie[i] is no more 217 * alias of mie[i] and needs to be maintained separately. 218 */ 219 uint64_t sie; 220 221 /* 222 * When hideleg[i]=0 and hvien[i]=1, vsie[i] is no more 223 * alias of sie[i] (mie[i]) and needs to be maintained separately. 224 */ 225 uint64_t vsie; 226 227 target_ulong satp; /* since: priv-1.10.0 */ 228 target_ulong stval; 229 target_ulong medeleg; 230 231 target_ulong stvec; 232 target_ulong sepc; 233 target_ulong scause; 234 235 target_ulong mtvec; 236 target_ulong mepc; 237 target_ulong mcause; 238 target_ulong mtval; /* since: priv-1.10.0 */ 239 240 /* Machine and Supervisor interrupt priorities */ 241 uint8_t miprio[64]; 242 uint8_t siprio[64]; 243 244 /* AIA CSRs */ 245 target_ulong miselect; 246 target_ulong siselect; 247 uint64_t mvien; 248 uint64_t mvip; 249 250 /* Hypervisor CSRs */ 251 target_ulong hstatus; 252 target_ulong hedeleg; 253 uint64_t hideleg; 254 target_ulong hcounteren; 255 target_ulong htval; 256 target_ulong htinst; 257 target_ulong hgatp; 258 target_ulong hgeie; 259 target_ulong hgeip; 260 uint64_t htimedelta; 261 uint64_t hvien; 262 263 /* 264 * Bits VSSIP, VSTIP and VSEIP in hvip are maintained in mip. Other bits 265 * from 0:12 are reserved. Bits 13:63 are not aliased and must be separately 266 * maintain in hvip. 267 */ 268 uint64_t hvip; 269 270 /* Hypervisor controlled virtual interrupt priorities */ 271 target_ulong hvictl; 272 uint8_t hviprio[64]; 273 274 /* Upper 64-bits of 128-bit CSRs */ 275 uint64_t mscratchh; 276 uint64_t sscratchh; 277 278 /* Virtual CSRs */ 279 /* 280 * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. 281 * For RV64 this is a 64-bit vsstatus. 282 */ 283 uint64_t vsstatus; 284 target_ulong vstvec; 285 target_ulong vsscratch; 286 target_ulong vsepc; 287 target_ulong vscause; 288 target_ulong vstval; 289 target_ulong vsatp; 290 291 /* AIA VS-mode CSRs */ 292 target_ulong vsiselect; 293 294 target_ulong mtval2; 295 target_ulong mtinst; 296 297 /* HS Backup CSRs */ 298 target_ulong stvec_hs; 299 target_ulong sscratch_hs; 300 target_ulong sepc_hs; 301 target_ulong scause_hs; 302 target_ulong stval_hs; 303 target_ulong satp_hs; 304 uint64_t mstatus_hs; 305 306 /* 307 * Signals whether the current exception occurred with two-stage address 308 * translation active. 309 */ 310 bool two_stage_lookup; 311 /* 312 * Signals whether the current exception occurred while doing two-stage 313 * address translation for the VS-stage page table walk. 314 */ 315 bool two_stage_indirect_lookup; 316 317 target_ulong scounteren; 318 target_ulong mcounteren; 319 320 target_ulong mcountinhibit; 321 322 /* PMU counter state */ 323 PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS]; 324 325 /* PMU event selector configured values. First three are unused */ 326 target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS]; 327 328 /* PMU event selector configured values for RV32 */ 329 target_ulong mhpmeventh_val[RV_MAX_MHPMEVENTS]; 330 331 target_ulong sscratch; 332 target_ulong mscratch; 333 334 /* Sstc CSRs */ 335 uint64_t stimecmp; 336 337 uint64_t vstimecmp; 338 339 /* physical memory protection */ 340 pmp_table_t pmp_state; 341 target_ulong mseccfg; 342 343 /* trigger module */ 344 target_ulong trigger_cur; 345 target_ulong tdata1[RV_MAX_TRIGGERS]; 346 target_ulong tdata2[RV_MAX_TRIGGERS]; 347 target_ulong tdata3[RV_MAX_TRIGGERS]; 348 struct CPUBreakpoint *cpu_breakpoint[RV_MAX_TRIGGERS]; 349 struct CPUWatchpoint *cpu_watchpoint[RV_MAX_TRIGGERS]; 350 QEMUTimer *itrigger_timer[RV_MAX_TRIGGERS]; 351 int64_t last_icount; 352 bool itrigger_enabled; 353 354 /* machine specific rdtime callback */ 355 uint64_t (*rdtime_fn)(void *); 356 void *rdtime_fn_arg; 357 358 /* machine specific AIA ireg read-modify-write callback */ 359 #define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \ 360 ((((__xlen) & 0xff) << 24) | \ 361 (((__vgein) & 0x3f) << 20) | \ 362 (((__virt) & 0x1) << 18) | \ 363 (((__priv) & 0x3) << 16) | \ 364 (__isel & 0xffff)) 365 #define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff) 366 #define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3) 367 #define AIA_IREG_VIRT(__ireg) (((__ireg) >> 18) & 0x1) 368 #define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 20) & 0x3f) 369 #define AIA_IREG_XLEN(__ireg) (((__ireg) >> 24) & 0xff) 370 int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg, 371 target_ulong *val, target_ulong new_val, target_ulong write_mask); 372 void *aia_ireg_rmw_fn_arg[4]; 373 374 /* True if in debugger mode. */ 375 bool debugger; 376 377 /* 378 * CSRs for PointerMasking extension 379 */ 380 target_ulong mmte; 381 target_ulong mpmmask; 382 target_ulong mpmbase; 383 target_ulong spmmask; 384 target_ulong spmbase; 385 target_ulong upmmask; 386 target_ulong upmbase; 387 388 /* CSRs for execution environment configuration */ 389 uint64_t menvcfg; 390 uint64_t mstateen[SMSTATEEN_MAX_COUNT]; 391 uint64_t hstateen[SMSTATEEN_MAX_COUNT]; 392 uint64_t sstateen[SMSTATEEN_MAX_COUNT]; 393 target_ulong senvcfg; 394 uint64_t henvcfg; 395 #endif 396 target_ulong cur_pmmask; 397 target_ulong cur_pmbase; 398 399 /* Fields from here on are preserved across CPU reset. */ 400 QEMUTimer *stimer; /* Internal timer for S-mode interrupt */ 401 QEMUTimer *vstimer; /* Internal timer for VS-mode interrupt */ 402 bool vstime_irq; 403 404 hwaddr kernel_addr; 405 hwaddr fdt_addr; 406 407 #ifdef CONFIG_KVM 408 /* kvm timer */ 409 bool kvm_timer_dirty; 410 uint64_t kvm_timer_time; 411 uint64_t kvm_timer_compare; 412 uint64_t kvm_timer_state; 413 uint64_t kvm_timer_frequency; 414 #endif /* CONFIG_KVM */ 415 }; 416 417 /* 418 * RISCVCPU: 419 * @env: #CPURISCVState 420 * 421 * A RISCV CPU. 422 */ 423 struct ArchCPU { 424 CPUState parent_obj; 425 426 CPURISCVState env; 427 428 char *dyn_csr_xml; 429 char *dyn_vreg_xml; 430 431 /* Configuration Settings */ 432 RISCVCPUConfig cfg; 433 434 QEMUTimer *pmu_timer; 435 /* A bitmask of Available programmable counters */ 436 uint32_t pmu_avail_ctrs; 437 /* Mapping of events to counters */ 438 GHashTable *pmu_event_ctr_map; 439 }; 440 441 /** 442 * RISCVCPUClass: 443 * @parent_realize: The parent class' realize handler. 444 * @parent_phases: The parent class' reset phase handlers. 445 * 446 * A RISCV CPU model. 447 */ 448 struct RISCVCPUClass { 449 CPUClass parent_class; 450 451 DeviceRealize parent_realize; 452 ResettablePhases parent_phases; 453 }; 454 455 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) 456 { 457 return (env->misa_ext & ext) != 0; 458 } 459 460 #include "cpu_user.h" 461 462 extern const char * const riscv_int_regnames[]; 463 extern const char * const riscv_int_regnamesh[]; 464 extern const char * const riscv_fpr_regnames[]; 465 466 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); 467 void riscv_cpu_do_interrupt(CPUState *cpu); 468 int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 469 int cpuid, DumpState *s); 470 int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 471 int cpuid, DumpState *s); 472 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 473 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 474 int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero); 475 uint8_t riscv_cpu_default_priority(int irq); 476 uint64_t riscv_cpu_all_pending(CPURISCVState *env); 477 int riscv_cpu_mirq_pending(CPURISCVState *env); 478 int riscv_cpu_sirq_pending(CPURISCVState *env); 479 int riscv_cpu_vsirq_pending(CPURISCVState *env); 480 bool riscv_cpu_fp_enabled(CPURISCVState *env); 481 target_ulong riscv_cpu_get_geilen(CPURISCVState *env); 482 void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); 483 bool riscv_cpu_vector_enabled(CPURISCVState *env); 484 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); 485 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); 486 G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 487 MMUAccessType access_type, 488 int mmu_idx, uintptr_t retaddr); 489 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 490 MMUAccessType access_type, int mmu_idx, 491 bool probe, uintptr_t retaddr); 492 char *riscv_isa_string(RISCVCPU *cpu); 493 void riscv_cpu_list(void); 494 495 #define cpu_list riscv_cpu_list 496 #define cpu_mmu_index riscv_cpu_mmu_index 497 498 #ifndef CONFIG_USER_ONLY 499 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 500 vaddr addr, unsigned size, 501 MMUAccessType access_type, 502 int mmu_idx, MemTxAttrs attrs, 503 MemTxResult response, uintptr_t retaddr); 504 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 505 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); 506 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); 507 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); 508 uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask, 509 uint64_t value); 510 void riscv_cpu_interrupt(CPURISCVState *env); 511 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ 512 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), 513 void *arg); 514 void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, 515 int (*rmw_fn)(void *arg, 516 target_ulong reg, 517 target_ulong *val, 518 target_ulong new_val, 519 target_ulong write_mask), 520 void *rmw_fn_arg); 521 522 RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit); 523 #endif 524 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); 525 526 void riscv_translate_init(void); 527 G_NORETURN void riscv_raise_exception(CPURISCVState *env, 528 uint32_t exception, uintptr_t pc); 529 530 target_ulong riscv_cpu_get_fflags(CPURISCVState *env); 531 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); 532 533 #include "exec/cpu-all.h" 534 535 FIELD(TB_FLAGS, MEM_IDX, 0, 3) 536 FIELD(TB_FLAGS, FS, 3, 2) 537 /* Vector flags */ 538 FIELD(TB_FLAGS, VS, 5, 2) 539 FIELD(TB_FLAGS, LMUL, 7, 3) 540 FIELD(TB_FLAGS, SEW, 10, 3) 541 FIELD(TB_FLAGS, VL_EQ_VLMAX, 13, 1) 542 FIELD(TB_FLAGS, VILL, 14, 1) 543 FIELD(TB_FLAGS, VSTART_EQ_ZERO, 15, 1) 544 /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ 545 FIELD(TB_FLAGS, XL, 16, 2) 546 /* If PointerMasking should be applied */ 547 FIELD(TB_FLAGS, PM_MASK_ENABLED, 18, 1) 548 FIELD(TB_FLAGS, PM_BASE_ENABLED, 19, 1) 549 FIELD(TB_FLAGS, VTA, 20, 1) 550 FIELD(TB_FLAGS, VMA, 21, 1) 551 /* Native debug itrigger */ 552 FIELD(TB_FLAGS, ITRIGGER, 22, 1) 553 /* Virtual mode enabled */ 554 FIELD(TB_FLAGS, VIRT_ENABLED, 23, 1) 555 FIELD(TB_FLAGS, PRIV, 24, 2) 556 FIELD(TB_FLAGS, AXL, 26, 2) 557 558 #ifdef TARGET_RISCV32 559 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) 560 #else 561 static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) 562 { 563 return env->misa_mxl; 564 } 565 #endif 566 #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env))) 567 568 static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURISCVState *env) 569 { 570 return &env_archcpu(env)->cfg; 571 } 572 573 #if !defined(CONFIG_USER_ONLY) 574 static inline int cpu_address_mode(CPURISCVState *env) 575 { 576 int mode = env->priv; 577 578 if (mode == PRV_M && get_field(env->mstatus, MSTATUS_MPRV)) { 579 mode = get_field(env->mstatus, MSTATUS_MPP); 580 } 581 return mode; 582 } 583 584 static inline RISCVMXL cpu_get_xl(CPURISCVState *env, target_ulong mode) 585 { 586 RISCVMXL xl = env->misa_mxl; 587 /* 588 * When emulating a 32-bit-only cpu, use RV32. 589 * When emulating a 64-bit cpu, and MXL has been reduced to RV32, 590 * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened 591 * back to RV64 for lower privs. 592 */ 593 if (xl != MXL_RV32) { 594 switch (mode) { 595 case PRV_M: 596 break; 597 case PRV_U: 598 xl = get_field(env->mstatus, MSTATUS64_UXL); 599 break; 600 default: /* PRV_S */ 601 xl = get_field(env->mstatus, MSTATUS64_SXL); 602 break; 603 } 604 } 605 return xl; 606 } 607 #endif 608 609 #if defined(TARGET_RISCV32) 610 #define cpu_recompute_xl(env) ((void)(env), MXL_RV32) 611 #else 612 static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) 613 { 614 #if !defined(CONFIG_USER_ONLY) 615 return cpu_get_xl(env, env->priv); 616 #else 617 return env->misa_mxl; 618 #endif 619 } 620 #endif 621 622 #if defined(TARGET_RISCV32) 623 #define cpu_address_xl(env) ((void)(env), MXL_RV32) 624 #else 625 static inline RISCVMXL cpu_address_xl(CPURISCVState *env) 626 { 627 #ifdef CONFIG_USER_ONLY 628 return env->xl; 629 #else 630 int mode = cpu_address_mode(env); 631 632 return cpu_get_xl(env, mode); 633 #endif 634 } 635 #endif 636 637 static inline int riscv_cpu_xlen(CPURISCVState *env) 638 { 639 return 16 << env->xl; 640 } 641 642 #ifdef TARGET_RISCV32 643 #define riscv_cpu_sxl(env) ((void)(env), MXL_RV32) 644 #else 645 static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env) 646 { 647 #ifdef CONFIG_USER_ONLY 648 return env->misa_mxl; 649 #else 650 return get_field(env->mstatus, MSTATUS64_SXL); 651 #endif 652 } 653 #endif 654 655 /* 656 * Encode LMUL to lmul as follows: 657 * LMUL vlmul lmul 658 * 1 000 0 659 * 2 001 1 660 * 4 010 2 661 * 8 011 3 662 * - 100 - 663 * 1/8 101 -3 664 * 1/4 110 -2 665 * 1/2 111 -1 666 * 667 * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul) 668 * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8 669 * => VLMAX = vlen >> (1 + 3 - (-3)) 670 * = 256 >> 7 671 * = 2 672 */ 673 static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) 674 { 675 uint8_t sew = FIELD_EX64(vtype, VTYPE, VSEW); 676 int8_t lmul = sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3); 677 return cpu->cfg.vlen >> (sew + 3 - lmul); 678 } 679 680 void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, 681 uint64_t *cs_base, uint32_t *pflags); 682 683 void riscv_cpu_update_mask(CPURISCVState *env); 684 685 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, 686 target_ulong *ret_value, 687 target_ulong new_value, target_ulong write_mask); 688 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, 689 target_ulong *ret_value, 690 target_ulong new_value, 691 target_ulong write_mask); 692 693 static inline void riscv_csr_write(CPURISCVState *env, int csrno, 694 target_ulong val) 695 { 696 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); 697 } 698 699 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) 700 { 701 target_ulong val = 0; 702 riscv_csrrw(env, csrno, &val, 0, 0); 703 return val; 704 } 705 706 typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, 707 int csrno); 708 typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, 709 target_ulong *ret_value); 710 typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, 711 target_ulong new_value); 712 typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, 713 target_ulong *ret_value, 714 target_ulong new_value, 715 target_ulong write_mask); 716 717 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, 718 Int128 *ret_value, 719 Int128 new_value, Int128 write_mask); 720 721 typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno, 722 Int128 *ret_value); 723 typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int csrno, 724 Int128 new_value); 725 726 typedef struct { 727 const char *name; 728 riscv_csr_predicate_fn predicate; 729 riscv_csr_read_fn read; 730 riscv_csr_write_fn write; 731 riscv_csr_op_fn op; 732 riscv_csr_read128_fn read128; 733 riscv_csr_write128_fn write128; 734 /* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0) */ 735 uint32_t min_priv_ver; 736 } riscv_csr_operations; 737 738 /* CSR function table constants */ 739 enum { 740 CSR_TABLE_SIZE = 0x1000 741 }; 742 743 /* 744 * The event id are encoded based on the encoding specified in the 745 * SBI specification v0.3 746 */ 747 748 enum riscv_pmu_event_idx { 749 RISCV_PMU_EVENT_HW_CPU_CYCLES = 0x01, 750 RISCV_PMU_EVENT_HW_INSTRUCTIONS = 0x02, 751 RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS = 0x10019, 752 RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS = 0x1001B, 753 RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS = 0x10021, 754 }; 755 756 /* used by tcg/tcg-cpu.c*/ 757 void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en); 758 bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset); 759 void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext); 760 761 typedef struct RISCVCPUMultiExtConfig { 762 const char *name; 763 uint32_t offset; 764 bool enabled; 765 } RISCVCPUMultiExtConfig; 766 767 extern const RISCVCPUMultiExtConfig riscv_cpu_extensions[]; 768 extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[]; 769 extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[]; 770 extern const RISCVCPUMultiExtConfig riscv_cpu_deprecated_exts[]; 771 extern Property riscv_cpu_options[]; 772 773 typedef struct isa_ext_data { 774 const char *name; 775 int min_version; 776 int ext_enable_offset; 777 } RISCVIsaExtData; 778 extern const RISCVIsaExtData isa_edata_arr[]; 779 char *riscv_cpu_get_name(RISCVCPU *cpu); 780 781 void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp); 782 void riscv_add_satp_mode_properties(Object *obj); 783 bool riscv_cpu_accelerator_compatible(RISCVCPU *cpu); 784 785 /* CSR function table */ 786 extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; 787 788 extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[]; 789 790 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); 791 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); 792 793 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); 794 795 uint8_t satp_mode_max_from_map(uint32_t map); 796 const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); 797 798 #endif /* RISCV_CPU_H */ 799