1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef RISCV_CPU_H 21 #define RISCV_CPU_H 22 23 #include "hw/core/cpu.h" 24 #include "exec/cpu-defs.h" 25 #include "fpu/softfloat-types.h" 26 27 #define TCG_GUEST_DEFAULT_MO 0 28 29 #define TYPE_RISCV_CPU "riscv-cpu" 30 31 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU 32 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) 33 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU 34 35 #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") 36 #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") 37 #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") 38 #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") 39 #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") 40 #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") 41 #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") 42 #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") 43 /* Deprecated */ 44 #define TYPE_RISCV_CPU_RV32IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv32imacu-nommu") 45 #define TYPE_RISCV_CPU_RV32GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9.1") 46 #define TYPE_RISCV_CPU_RV32GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.10.0") 47 #define TYPE_RISCV_CPU_RV64IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv64imacu-nommu") 48 #define TYPE_RISCV_CPU_RV64GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.9.1") 49 #define TYPE_RISCV_CPU_RV64GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.10.0") 50 51 #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2)) 52 #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2)) 53 54 #if defined(TARGET_RISCV32) 55 #define RVXLEN RV32 56 #elif defined(TARGET_RISCV64) 57 #define RVXLEN RV64 58 #endif 59 60 #define RV(x) ((target_ulong)1 << (x - 'A')) 61 62 #define RVI RV('I') 63 #define RVE RV('E') /* E and I are mutually exclusive */ 64 #define RVM RV('M') 65 #define RVA RV('A') 66 #define RVF RV('F') 67 #define RVD RV('D') 68 #define RVC RV('C') 69 #define RVS RV('S') 70 #define RVU RV('U') 71 #define RVH RV('H') 72 73 /* S extension denotes that Supervisor mode exists, however it is possible 74 to have a core that support S mode but does not have an MMU and there 75 is currently no bit in misa to indicate whether an MMU exists or not 76 so a cpu features bitfield is required, likewise for optional PMP support */ 77 enum { 78 RISCV_FEATURE_MMU, 79 RISCV_FEATURE_PMP, 80 RISCV_FEATURE_MISA 81 }; 82 83 #define PRIV_VERSION_1_09_1 0x00010901 84 #define PRIV_VERSION_1_10_0 0x00011000 85 #define PRIV_VERSION_1_11_0 0x00011100 86 87 #define TRANSLATE_PMP_FAIL 2 88 #define TRANSLATE_FAIL 1 89 #define TRANSLATE_SUCCESS 0 90 #define MMU_USER_IDX 3 91 92 #define MAX_RISCV_PMPS (16) 93 94 typedef struct CPURISCVState CPURISCVState; 95 96 #include "pmp.h" 97 98 struct CPURISCVState { 99 target_ulong gpr[32]; 100 uint64_t fpr[32]; /* assume both F and D extensions */ 101 target_ulong pc; 102 target_ulong load_res; 103 target_ulong load_val; 104 105 target_ulong frm; 106 107 target_ulong badaddr; 108 target_ulong guest_phys_fault_addr; 109 110 target_ulong priv_ver; 111 target_ulong misa; 112 target_ulong misa_mask; 113 114 uint32_t features; 115 116 #ifdef CONFIG_USER_ONLY 117 uint32_t elf_flags; 118 #endif 119 120 #ifndef CONFIG_USER_ONLY 121 target_ulong priv; 122 /* This contains QEMU specific information about the virt state. */ 123 target_ulong virt; 124 target_ulong resetvec; 125 126 target_ulong mhartid; 127 target_ulong mstatus; 128 129 target_ulong mip; 130 131 #ifdef TARGET_RISCV32 132 target_ulong mstatush; 133 #endif 134 135 uint32_t miclaim; 136 137 target_ulong mie; 138 target_ulong mideleg; 139 140 target_ulong sptbr; /* until: priv-1.9.1 */ 141 target_ulong satp; /* since: priv-1.10.0 */ 142 target_ulong sbadaddr; 143 target_ulong mbadaddr; 144 target_ulong medeleg; 145 146 target_ulong stvec; 147 target_ulong sepc; 148 target_ulong scause; 149 150 target_ulong mtvec; 151 target_ulong mepc; 152 target_ulong mcause; 153 target_ulong mtval; /* since: priv-1.10.0 */ 154 155 /* Hypervisor CSRs */ 156 target_ulong hstatus; 157 target_ulong hedeleg; 158 target_ulong hideleg; 159 target_ulong hcounteren; 160 target_ulong htval; 161 target_ulong htinst; 162 target_ulong hgatp; 163 uint64_t htimedelta; 164 165 /* Virtual CSRs */ 166 target_ulong vsstatus; 167 target_ulong vstvec; 168 target_ulong vsscratch; 169 target_ulong vsepc; 170 target_ulong vscause; 171 target_ulong vstval; 172 target_ulong vsatp; 173 #ifdef TARGET_RISCV32 174 target_ulong vsstatush; 175 #endif 176 177 target_ulong mtval2; 178 target_ulong mtinst; 179 180 /* HS Backup CSRs */ 181 target_ulong stvec_hs; 182 target_ulong sscratch_hs; 183 target_ulong sepc_hs; 184 target_ulong scause_hs; 185 target_ulong stval_hs; 186 target_ulong satp_hs; 187 target_ulong mstatus_hs; 188 #ifdef TARGET_RISCV32 189 target_ulong mstatush_hs; 190 #endif 191 192 target_ulong scounteren; 193 target_ulong mcounteren; 194 195 target_ulong sscratch; 196 target_ulong mscratch; 197 198 /* temporary htif regs */ 199 uint64_t mfromhost; 200 uint64_t mtohost; 201 uint64_t timecmp; 202 203 /* physical memory protection */ 204 pmp_table_t pmp_state; 205 206 /* machine specific rdtime callback */ 207 uint64_t (*rdtime_fn)(void); 208 209 /* True if in debugger mode. */ 210 bool debugger; 211 #endif 212 213 float_status fp_status; 214 215 /* Fields from here on are preserved across CPU reset. */ 216 QEMUTimer *timer; /* Internal timer */ 217 }; 218 219 #define RISCV_CPU_CLASS(klass) \ 220 OBJECT_CLASS_CHECK(RISCVCPUClass, (klass), TYPE_RISCV_CPU) 221 #define RISCV_CPU(obj) \ 222 OBJECT_CHECK(RISCVCPU, (obj), TYPE_RISCV_CPU) 223 #define RISCV_CPU_GET_CLASS(obj) \ 224 OBJECT_GET_CLASS(RISCVCPUClass, (obj), TYPE_RISCV_CPU) 225 226 /** 227 * RISCVCPUClass: 228 * @parent_realize: The parent class' realize handler. 229 * @parent_reset: The parent class' reset handler. 230 * 231 * A RISCV CPU model. 232 */ 233 typedef struct RISCVCPUClass { 234 /*< private >*/ 235 CPUClass parent_class; 236 /*< public >*/ 237 DeviceRealize parent_realize; 238 DeviceReset parent_reset; 239 } RISCVCPUClass; 240 241 /** 242 * RISCVCPU: 243 * @env: #CPURISCVState 244 * 245 * A RISCV CPU. 246 */ 247 typedef struct RISCVCPU { 248 /*< private >*/ 249 CPUState parent_obj; 250 /*< public >*/ 251 CPUNegativeOffsetState neg; 252 CPURISCVState env; 253 254 /* Configuration Settings */ 255 struct { 256 bool ext_i; 257 bool ext_e; 258 bool ext_g; 259 bool ext_m; 260 bool ext_a; 261 bool ext_f; 262 bool ext_d; 263 bool ext_c; 264 bool ext_s; 265 bool ext_u; 266 bool ext_h; 267 bool ext_counters; 268 bool ext_ifencei; 269 bool ext_icsr; 270 271 char *priv_spec; 272 char *user_spec; 273 bool mmu; 274 bool pmp; 275 } cfg; 276 } RISCVCPU; 277 278 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) 279 { 280 return (env->misa & ext) != 0; 281 } 282 283 static inline bool riscv_feature(CPURISCVState *env, int feature) 284 { 285 return env->features & (1ULL << feature); 286 } 287 288 #include "cpu_user.h" 289 #include "cpu_bits.h" 290 291 extern const char * const riscv_int_regnames[]; 292 extern const char * const riscv_fpr_regnames[]; 293 extern const char * const riscv_excp_names[]; 294 extern const char * const riscv_intr_names[]; 295 296 void riscv_cpu_do_interrupt(CPUState *cpu); 297 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 298 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 299 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); 300 bool riscv_cpu_fp_enabled(CPURISCVState *env); 301 bool riscv_cpu_virt_enabled(CPURISCVState *env); 302 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); 303 bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env); 304 void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable); 305 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); 306 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 307 void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 308 MMUAccessType access_type, int mmu_idx, 309 uintptr_t retaddr); 310 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 311 MMUAccessType access_type, int mmu_idx, 312 bool probe, uintptr_t retaddr); 313 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 314 vaddr addr, unsigned size, 315 MMUAccessType access_type, 316 int mmu_idx, MemTxAttrs attrs, 317 MemTxResult response, uintptr_t retaddr); 318 char *riscv_isa_string(RISCVCPU *cpu); 319 void riscv_cpu_list(void); 320 321 #define cpu_signal_handler riscv_cpu_signal_handler 322 #define cpu_list riscv_cpu_list 323 #define cpu_mmu_index riscv_cpu_mmu_index 324 325 #ifndef CONFIG_USER_ONLY 326 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); 327 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts); 328 uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value); 329 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ 330 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void)); 331 #endif 332 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); 333 334 void riscv_translate_init(void); 335 int riscv_cpu_signal_handler(int host_signum, void *pinfo, void *puc); 336 void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env, 337 uint32_t exception, uintptr_t pc); 338 339 target_ulong riscv_cpu_get_fflags(CPURISCVState *env); 340 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); 341 342 #define TB_FLAGS_MMU_MASK 3 343 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS 344 345 static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 346 target_ulong *cs_base, uint32_t *flags) 347 { 348 *pc = env->pc; 349 *cs_base = 0; 350 #ifdef CONFIG_USER_ONLY 351 *flags = TB_FLAGS_MSTATUS_FS; 352 #else 353 *flags = cpu_mmu_index(env, 0); 354 if (riscv_cpu_fp_enabled(env)) { 355 *flags |= env->mstatus & MSTATUS_FS; 356 } 357 #endif 358 } 359 360 int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, 361 target_ulong new_value, target_ulong write_mask); 362 int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value, 363 target_ulong new_value, target_ulong write_mask); 364 365 static inline void riscv_csr_write(CPURISCVState *env, int csrno, 366 target_ulong val) 367 { 368 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); 369 } 370 371 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) 372 { 373 target_ulong val = 0; 374 riscv_csrrw(env, csrno, &val, 0, 0); 375 return val; 376 } 377 378 typedef int (*riscv_csr_predicate_fn)(CPURISCVState *env, int csrno); 379 typedef int (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, 380 target_ulong *ret_value); 381 typedef int (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, 382 target_ulong new_value); 383 typedef int (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, 384 target_ulong *ret_value, target_ulong new_value, target_ulong write_mask); 385 386 typedef struct { 387 riscv_csr_predicate_fn predicate; 388 riscv_csr_read_fn read; 389 riscv_csr_write_fn write; 390 riscv_csr_op_fn op; 391 } riscv_csr_operations; 392 393 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); 394 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); 395 396 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); 397 398 typedef CPURISCVState CPUArchState; 399 typedef RISCVCPU ArchCPU; 400 401 #include "exec/cpu-all.h" 402 403 #endif /* RISCV_CPU_H */ 404