1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef RISCV_CPU_H 21 #define RISCV_CPU_H 22 23 #include "hw/core/cpu.h" 24 #include "hw/registerfields.h" 25 #include "exec/cpu-defs.h" 26 #include "fpu/softfloat-types.h" 27 #include "qom/object.h" 28 #include "cpu_bits.h" 29 30 #define TCG_GUEST_DEFAULT_MO 0 31 32 #define TYPE_RISCV_CPU "riscv-cpu" 33 34 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU 35 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) 36 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU 37 38 #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") 39 #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") 40 #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") 41 #define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128") 42 #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") 43 #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") 44 #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") 45 #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") 46 #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") 47 #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") 48 #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") 49 50 #if defined(TARGET_RISCV32) 51 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 52 #elif defined(TARGET_RISCV64) 53 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 54 #endif 55 56 #define RV(x) ((target_ulong)1 << (x - 'A')) 57 58 #define RVI RV('I') 59 #define RVE RV('E') /* E and I are mutually exclusive */ 60 #define RVM RV('M') 61 #define RVA RV('A') 62 #define RVF RV('F') 63 #define RVD RV('D') 64 #define RVV RV('V') 65 #define RVC RV('C') 66 #define RVS RV('S') 67 #define RVU RV('U') 68 #define RVH RV('H') 69 #define RVJ RV('J') 70 71 /* S extension denotes that Supervisor mode exists, however it is possible 72 to have a core that support S mode but does not have an MMU and there 73 is currently no bit in misa to indicate whether an MMU exists or not 74 so a cpu features bitfield is required, likewise for optional PMP support */ 75 enum { 76 RISCV_FEATURE_MMU, 77 RISCV_FEATURE_PMP, 78 RISCV_FEATURE_EPMP, 79 RISCV_FEATURE_MISA 80 }; 81 82 #define PRIV_VERSION_1_10_0 0x00011000 83 #define PRIV_VERSION_1_11_0 0x00011100 84 85 #define VEXT_VERSION_1_00_0 0x00010000 86 87 enum { 88 TRANSLATE_SUCCESS, 89 TRANSLATE_FAIL, 90 TRANSLATE_PMP_FAIL, 91 TRANSLATE_G_STAGE_FAIL 92 }; 93 94 #define MMU_USER_IDX 3 95 96 #define MAX_RISCV_PMPS (16) 97 98 typedef struct CPURISCVState CPURISCVState; 99 100 #if !defined(CONFIG_USER_ONLY) 101 #include "pmp.h" 102 #endif 103 104 #define RV_VLEN_MAX 1024 105 106 FIELD(VTYPE, VLMUL, 0, 3) 107 FIELD(VTYPE, VSEW, 3, 3) 108 FIELD(VTYPE, VTA, 6, 1) 109 FIELD(VTYPE, VMA, 7, 1) 110 FIELD(VTYPE, VEDIV, 8, 2) 111 FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) 112 FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1) 113 114 struct CPURISCVState { 115 target_ulong gpr[32]; 116 target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ 117 uint64_t fpr[32]; /* assume both F and D extensions */ 118 119 /* vector coprocessor state. */ 120 uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); 121 target_ulong vxrm; 122 target_ulong vxsat; 123 target_ulong vl; 124 target_ulong vstart; 125 target_ulong vtype; 126 127 target_ulong pc; 128 target_ulong load_res; 129 target_ulong load_val; 130 131 target_ulong frm; 132 133 target_ulong badaddr; 134 target_ulong guest_phys_fault_addr; 135 136 target_ulong priv_ver; 137 target_ulong bext_ver; 138 target_ulong vext_ver; 139 140 /* RISCVMXL, but uint32_t for vmstate migration */ 141 uint32_t misa_mxl; /* current mxl */ 142 uint32_t misa_mxl_max; /* max mxl for this cpu */ 143 uint32_t misa_ext; /* current extensions */ 144 uint32_t misa_ext_mask; /* max ext for this cpu */ 145 146 /* 128-bit helpers upper part return value */ 147 target_ulong retxh; 148 149 uint32_t features; 150 151 #ifdef CONFIG_USER_ONLY 152 uint32_t elf_flags; 153 #endif 154 155 #ifndef CONFIG_USER_ONLY 156 target_ulong priv; 157 /* This contains QEMU specific information about the virt state. */ 158 target_ulong virt; 159 target_ulong resetvec; 160 161 target_ulong mhartid; 162 /* 163 * For RV32 this is 32-bit mstatus and 32-bit mstatush. 164 * For RV64 this is a 64-bit mstatus. 165 */ 166 uint64_t mstatus; 167 168 target_ulong mip; 169 170 uint32_t miclaim; 171 172 target_ulong mie; 173 target_ulong mideleg; 174 175 target_ulong satp; /* since: priv-1.10.0 */ 176 target_ulong stval; 177 target_ulong medeleg; 178 179 target_ulong stvec; 180 target_ulong sepc; 181 target_ulong scause; 182 183 target_ulong mtvec; 184 target_ulong mepc; 185 target_ulong mcause; 186 target_ulong mtval; /* since: priv-1.10.0 */ 187 188 /* Hypervisor CSRs */ 189 target_ulong hstatus; 190 target_ulong hedeleg; 191 target_ulong hideleg; 192 target_ulong hcounteren; 193 target_ulong htval; 194 target_ulong htinst; 195 target_ulong hgatp; 196 uint64_t htimedelta; 197 198 /* Upper 64-bits of 128-bit CSRs */ 199 uint64_t mscratchh; 200 uint64_t sscratchh; 201 202 /* Virtual CSRs */ 203 /* 204 * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. 205 * For RV64 this is a 64-bit vsstatus. 206 */ 207 uint64_t vsstatus; 208 target_ulong vstvec; 209 target_ulong vsscratch; 210 target_ulong vsepc; 211 target_ulong vscause; 212 target_ulong vstval; 213 target_ulong vsatp; 214 215 target_ulong mtval2; 216 target_ulong mtinst; 217 218 /* HS Backup CSRs */ 219 target_ulong stvec_hs; 220 target_ulong sscratch_hs; 221 target_ulong sepc_hs; 222 target_ulong scause_hs; 223 target_ulong stval_hs; 224 target_ulong satp_hs; 225 uint64_t mstatus_hs; 226 227 /* Signals whether the current exception occurred with two-stage address 228 translation active. */ 229 bool two_stage_lookup; 230 231 target_ulong scounteren; 232 target_ulong mcounteren; 233 234 target_ulong sscratch; 235 target_ulong mscratch; 236 237 /* temporary htif regs */ 238 uint64_t mfromhost; 239 uint64_t mtohost; 240 uint64_t timecmp; 241 242 /* physical memory protection */ 243 pmp_table_t pmp_state; 244 target_ulong mseccfg; 245 246 /* machine specific rdtime callback */ 247 uint64_t (*rdtime_fn)(uint32_t); 248 uint32_t rdtime_fn_arg; 249 250 /* True if in debugger mode. */ 251 bool debugger; 252 253 /* 254 * CSRs for PointerMasking extension 255 */ 256 target_ulong mmte; 257 target_ulong mpmmask; 258 target_ulong mpmbase; 259 target_ulong spmmask; 260 target_ulong spmbase; 261 target_ulong upmmask; 262 target_ulong upmbase; 263 #endif 264 265 float_status fp_status; 266 267 /* Fields from here on are preserved across CPU reset. */ 268 QEMUTimer *timer; /* Internal timer */ 269 }; 270 271 OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass, 272 RISCV_CPU) 273 274 /** 275 * RISCVCPUClass: 276 * @parent_realize: The parent class' realize handler. 277 * @parent_reset: The parent class' reset handler. 278 * 279 * A RISCV CPU model. 280 */ 281 struct RISCVCPUClass { 282 /*< private >*/ 283 CPUClass parent_class; 284 /*< public >*/ 285 DeviceRealize parent_realize; 286 DeviceReset parent_reset; 287 }; 288 289 /** 290 * RISCVCPU: 291 * @env: #CPURISCVState 292 * 293 * A RISCV CPU. 294 */ 295 struct RISCVCPU { 296 /*< private >*/ 297 CPUState parent_obj; 298 /*< public >*/ 299 CPUNegativeOffsetState neg; 300 CPURISCVState env; 301 302 char *dyn_csr_xml; 303 char *dyn_vreg_xml; 304 305 /* Configuration Settings */ 306 struct { 307 bool ext_i; 308 bool ext_e; 309 bool ext_g; 310 bool ext_m; 311 bool ext_a; 312 bool ext_f; 313 bool ext_d; 314 bool ext_c; 315 bool ext_s; 316 bool ext_u; 317 bool ext_h; 318 bool ext_j; 319 bool ext_v; 320 bool ext_zba; 321 bool ext_zbb; 322 bool ext_zbc; 323 bool ext_zbs; 324 bool ext_counters; 325 bool ext_ifencei; 326 bool ext_icsr; 327 bool ext_zfh; 328 bool ext_zfhmin; 329 330 char *priv_spec; 331 char *user_spec; 332 char *bext_spec; 333 char *vext_spec; 334 uint16_t vlen; 335 uint16_t elen; 336 bool mmu; 337 bool pmp; 338 bool epmp; 339 uint64_t resetvec; 340 } cfg; 341 }; 342 343 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) 344 { 345 return (env->misa_ext & ext) != 0; 346 } 347 348 static inline bool riscv_feature(CPURISCVState *env, int feature) 349 { 350 return env->features & (1ULL << feature); 351 } 352 353 #include "cpu_user.h" 354 355 extern const char * const riscv_int_regnames[]; 356 extern const char * const riscv_int_regnamesh[]; 357 extern const char * const riscv_fpr_regnames[]; 358 359 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); 360 void riscv_cpu_do_interrupt(CPUState *cpu); 361 int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 362 int cpuid, void *opaque); 363 int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 364 int cpuid, void *opaque); 365 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 366 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 367 bool riscv_cpu_fp_enabled(CPURISCVState *env); 368 bool riscv_cpu_vector_enabled(CPURISCVState *env); 369 bool riscv_cpu_virt_enabled(CPURISCVState *env); 370 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); 371 bool riscv_cpu_two_stage_lookup(int mmu_idx); 372 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); 373 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 374 void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 375 MMUAccessType access_type, int mmu_idx, 376 uintptr_t retaddr) QEMU_NORETURN; 377 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 378 MMUAccessType access_type, int mmu_idx, 379 bool probe, uintptr_t retaddr); 380 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 381 vaddr addr, unsigned size, 382 MMUAccessType access_type, 383 int mmu_idx, MemTxAttrs attrs, 384 MemTxResult response, uintptr_t retaddr); 385 char *riscv_isa_string(RISCVCPU *cpu); 386 void riscv_cpu_list(void); 387 388 #define cpu_list riscv_cpu_list 389 #define cpu_mmu_index riscv_cpu_mmu_index 390 391 #ifndef CONFIG_USER_ONLY 392 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); 393 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); 394 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts); 395 uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value); 396 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ 397 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t), 398 uint32_t arg); 399 #endif 400 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); 401 402 void riscv_translate_init(void); 403 void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env, 404 uint32_t exception, uintptr_t pc); 405 406 target_ulong riscv_cpu_get_fflags(CPURISCVState *env); 407 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); 408 409 #define TB_FLAGS_PRIV_MMU_MASK 3 410 #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2) 411 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS 412 #define TB_FLAGS_MSTATUS_VS MSTATUS_VS 413 414 typedef CPURISCVState CPUArchState; 415 typedef RISCVCPU ArchCPU; 416 #include "exec/cpu-all.h" 417 418 FIELD(TB_FLAGS, MEM_IDX, 0, 3) 419 FIELD(TB_FLAGS, LMUL, 3, 3) 420 FIELD(TB_FLAGS, SEW, 6, 3) 421 /* Skip MSTATUS_VS (0x600) bits */ 422 FIELD(TB_FLAGS, VL_EQ_VLMAX, 11, 1) 423 FIELD(TB_FLAGS, VILL, 12, 1) 424 /* Skip MSTATUS_FS (0x6000) bits */ 425 /* Is a Hypervisor instruction load/store allowed? */ 426 FIELD(TB_FLAGS, HLSX, 15, 1) 427 FIELD(TB_FLAGS, MSTATUS_HS_FS, 16, 2) 428 FIELD(TB_FLAGS, MSTATUS_HS_VS, 18, 2) 429 /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ 430 FIELD(TB_FLAGS, XL, 20, 2) 431 /* If PointerMasking should be applied */ 432 FIELD(TB_FLAGS, PM_ENABLED, 22, 1) 433 434 #ifdef TARGET_RISCV32 435 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) 436 #else 437 static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) 438 { 439 return env->misa_mxl; 440 } 441 #endif 442 443 /* 444 * Encode LMUL to lmul as follows: 445 * LMUL vlmul lmul 446 * 1 000 0 447 * 2 001 1 448 * 4 010 2 449 * 8 011 3 450 * - 100 - 451 * 1/8 101 -3 452 * 1/4 110 -2 453 * 1/2 111 -1 454 * 455 * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul) 456 * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8 457 * => VLMAX = vlen >> (1 + 3 - (-3)) 458 * = 256 >> 7 459 * = 2 460 */ 461 static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) 462 { 463 uint8_t sew = FIELD_EX64(vtype, VTYPE, VSEW); 464 int8_t lmul = sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3); 465 return cpu->cfg.vlen >> (sew + 3 - lmul); 466 } 467 468 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 469 target_ulong *cs_base, uint32_t *pflags); 470 471 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, 472 target_ulong *ret_value, 473 target_ulong new_value, target_ulong write_mask); 474 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, 475 target_ulong *ret_value, 476 target_ulong new_value, 477 target_ulong write_mask); 478 479 static inline void riscv_csr_write(CPURISCVState *env, int csrno, 480 target_ulong val) 481 { 482 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); 483 } 484 485 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) 486 { 487 target_ulong val = 0; 488 riscv_csrrw(env, csrno, &val, 0, 0); 489 return val; 490 } 491 492 typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, 493 int csrno); 494 typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, 495 target_ulong *ret_value); 496 typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, 497 target_ulong new_value); 498 typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, 499 target_ulong *ret_value, 500 target_ulong new_value, 501 target_ulong write_mask); 502 503 typedef struct { 504 const char *name; 505 riscv_csr_predicate_fn predicate; 506 riscv_csr_read_fn read; 507 riscv_csr_write_fn write; 508 riscv_csr_op_fn op; 509 } riscv_csr_operations; 510 511 /* CSR function table constants */ 512 enum { 513 CSR_TABLE_SIZE = 0x1000 514 }; 515 516 /* CSR function table */ 517 extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; 518 519 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); 520 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); 521 522 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); 523 524 #endif /* RISCV_CPU_H */ 525