1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef RISCV_CPU_H 21 #define RISCV_CPU_H 22 23 #include "hw/core/cpu.h" 24 #include "hw/registerfields.h" 25 #include "exec/cpu-defs.h" 26 #include "fpu/softfloat-types.h" 27 28 #define TCG_GUEST_DEFAULT_MO 0 29 30 #define TYPE_RISCV_CPU "riscv-cpu" 31 32 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU 33 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) 34 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU 35 36 #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") 37 #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") 38 #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") 39 #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") 40 #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") 41 #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") 42 #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") 43 #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") 44 #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") 45 46 #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2)) 47 #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2)) 48 49 #if defined(TARGET_RISCV32) 50 #define RVXLEN RV32 51 #elif defined(TARGET_RISCV64) 52 #define RVXLEN RV64 53 #endif 54 55 #define RV(x) ((target_ulong)1 << (x - 'A')) 56 57 #define RVI RV('I') 58 #define RVE RV('E') /* E and I are mutually exclusive */ 59 #define RVM RV('M') 60 #define RVA RV('A') 61 #define RVF RV('F') 62 #define RVD RV('D') 63 #define RVV RV('V') 64 #define RVC RV('C') 65 #define RVS RV('S') 66 #define RVU RV('U') 67 #define RVH RV('H') 68 69 /* S extension denotes that Supervisor mode exists, however it is possible 70 to have a core that support S mode but does not have an MMU and there 71 is currently no bit in misa to indicate whether an MMU exists or not 72 so a cpu features bitfield is required, likewise for optional PMP support */ 73 enum { 74 RISCV_FEATURE_MMU, 75 RISCV_FEATURE_PMP, 76 RISCV_FEATURE_MISA 77 }; 78 79 #define PRIV_VERSION_1_10_0 0x00011000 80 #define PRIV_VERSION_1_11_0 0x00011100 81 82 #define VEXT_VERSION_0_07_1 0x00000701 83 84 #define TRANSLATE_PMP_FAIL 2 85 #define TRANSLATE_FAIL 1 86 #define TRANSLATE_SUCCESS 0 87 #define MMU_USER_IDX 3 88 89 #define MAX_RISCV_PMPS (16) 90 91 typedef struct CPURISCVState CPURISCVState; 92 93 #include "pmp.h" 94 95 #define RV_VLEN_MAX 512 96 97 FIELD(VTYPE, VLMUL, 0, 2) 98 FIELD(VTYPE, VSEW, 2, 3) 99 FIELD(VTYPE, VEDIV, 5, 2) 100 FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 9) 101 FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 2, 1) 102 103 struct CPURISCVState { 104 target_ulong gpr[32]; 105 uint64_t fpr[32]; /* assume both F and D extensions */ 106 107 /* vector coprocessor state. */ 108 uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); 109 target_ulong vxrm; 110 target_ulong vxsat; 111 target_ulong vl; 112 target_ulong vstart; 113 target_ulong vtype; 114 115 target_ulong pc; 116 target_ulong load_res; 117 target_ulong load_val; 118 119 target_ulong frm; 120 121 target_ulong badaddr; 122 target_ulong guest_phys_fault_addr; 123 124 target_ulong priv_ver; 125 target_ulong vext_ver; 126 target_ulong misa; 127 target_ulong misa_mask; 128 129 uint32_t features; 130 131 #ifdef CONFIG_USER_ONLY 132 uint32_t elf_flags; 133 #endif 134 135 #ifndef CONFIG_USER_ONLY 136 target_ulong priv; 137 /* This contains QEMU specific information about the virt state. */ 138 target_ulong virt; 139 target_ulong resetvec; 140 141 target_ulong mhartid; 142 target_ulong mstatus; 143 144 target_ulong mip; 145 146 #ifdef TARGET_RISCV32 147 target_ulong mstatush; 148 #endif 149 150 uint32_t miclaim; 151 152 target_ulong mie; 153 target_ulong mideleg; 154 155 target_ulong sptbr; /* until: priv-1.9.1 */ 156 target_ulong satp; /* since: priv-1.10.0 */ 157 target_ulong sbadaddr; 158 target_ulong mbadaddr; 159 target_ulong medeleg; 160 161 target_ulong stvec; 162 target_ulong sepc; 163 target_ulong scause; 164 165 target_ulong mtvec; 166 target_ulong mepc; 167 target_ulong mcause; 168 target_ulong mtval; /* since: priv-1.10.0 */ 169 170 /* Hypervisor CSRs */ 171 target_ulong hstatus; 172 target_ulong hedeleg; 173 target_ulong hideleg; 174 target_ulong hcounteren; 175 target_ulong htval; 176 target_ulong htinst; 177 target_ulong hgatp; 178 uint64_t htimedelta; 179 180 /* Virtual CSRs */ 181 target_ulong vsstatus; 182 target_ulong vstvec; 183 target_ulong vsscratch; 184 target_ulong vsepc; 185 target_ulong vscause; 186 target_ulong vstval; 187 target_ulong vsatp; 188 #ifdef TARGET_RISCV32 189 target_ulong vsstatush; 190 #endif 191 192 target_ulong mtval2; 193 target_ulong mtinst; 194 195 /* HS Backup CSRs */ 196 target_ulong stvec_hs; 197 target_ulong sscratch_hs; 198 target_ulong sepc_hs; 199 target_ulong scause_hs; 200 target_ulong stval_hs; 201 target_ulong satp_hs; 202 target_ulong mstatus_hs; 203 #ifdef TARGET_RISCV32 204 target_ulong mstatush_hs; 205 #endif 206 207 target_ulong scounteren; 208 target_ulong mcounteren; 209 210 target_ulong sscratch; 211 target_ulong mscratch; 212 213 /* temporary htif regs */ 214 uint64_t mfromhost; 215 uint64_t mtohost; 216 uint64_t timecmp; 217 218 /* physical memory protection */ 219 pmp_table_t pmp_state; 220 221 /* machine specific rdtime callback */ 222 uint64_t (*rdtime_fn)(void); 223 224 /* True if in debugger mode. */ 225 bool debugger; 226 #endif 227 228 float_status fp_status; 229 230 /* Fields from here on are preserved across CPU reset. */ 231 QEMUTimer *timer; /* Internal timer */ 232 }; 233 234 #define RISCV_CPU_CLASS(klass) \ 235 OBJECT_CLASS_CHECK(RISCVCPUClass, (klass), TYPE_RISCV_CPU) 236 #define RISCV_CPU(obj) \ 237 OBJECT_CHECK(RISCVCPU, (obj), TYPE_RISCV_CPU) 238 #define RISCV_CPU_GET_CLASS(obj) \ 239 OBJECT_GET_CLASS(RISCVCPUClass, (obj), TYPE_RISCV_CPU) 240 241 /** 242 * RISCVCPUClass: 243 * @parent_realize: The parent class' realize handler. 244 * @parent_reset: The parent class' reset handler. 245 * 246 * A RISCV CPU model. 247 */ 248 typedef struct RISCVCPUClass { 249 /*< private >*/ 250 CPUClass parent_class; 251 /*< public >*/ 252 DeviceRealize parent_realize; 253 DeviceReset parent_reset; 254 } RISCVCPUClass; 255 256 /** 257 * RISCVCPU: 258 * @env: #CPURISCVState 259 * 260 * A RISCV CPU. 261 */ 262 typedef struct RISCVCPU { 263 /*< private >*/ 264 CPUState parent_obj; 265 /*< public >*/ 266 CPUNegativeOffsetState neg; 267 CPURISCVState env; 268 269 /* Configuration Settings */ 270 struct { 271 bool ext_i; 272 bool ext_e; 273 bool ext_g; 274 bool ext_m; 275 bool ext_a; 276 bool ext_f; 277 bool ext_d; 278 bool ext_c; 279 bool ext_s; 280 bool ext_u; 281 bool ext_h; 282 bool ext_counters; 283 bool ext_ifencei; 284 bool ext_icsr; 285 286 char *priv_spec; 287 char *user_spec; 288 uint16_t vlen; 289 uint16_t elen; 290 bool mmu; 291 bool pmp; 292 } cfg; 293 } RISCVCPU; 294 295 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) 296 { 297 return (env->misa & ext) != 0; 298 } 299 300 static inline bool riscv_feature(CPURISCVState *env, int feature) 301 { 302 return env->features & (1ULL << feature); 303 } 304 305 #include "cpu_user.h" 306 #include "cpu_bits.h" 307 308 extern const char * const riscv_int_regnames[]; 309 extern const char * const riscv_fpr_regnames[]; 310 extern const char * const riscv_excp_names[]; 311 extern const char * const riscv_intr_names[]; 312 313 void riscv_cpu_do_interrupt(CPUState *cpu); 314 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 315 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 316 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); 317 bool riscv_cpu_fp_enabled(CPURISCVState *env); 318 bool riscv_cpu_virt_enabled(CPURISCVState *env); 319 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); 320 bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env); 321 void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable); 322 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); 323 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 324 void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 325 MMUAccessType access_type, int mmu_idx, 326 uintptr_t retaddr); 327 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 328 MMUAccessType access_type, int mmu_idx, 329 bool probe, uintptr_t retaddr); 330 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 331 vaddr addr, unsigned size, 332 MMUAccessType access_type, 333 int mmu_idx, MemTxAttrs attrs, 334 MemTxResult response, uintptr_t retaddr); 335 char *riscv_isa_string(RISCVCPU *cpu); 336 void riscv_cpu_list(void); 337 338 #define cpu_signal_handler riscv_cpu_signal_handler 339 #define cpu_list riscv_cpu_list 340 #define cpu_mmu_index riscv_cpu_mmu_index 341 342 #ifndef CONFIG_USER_ONLY 343 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); 344 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts); 345 uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value); 346 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ 347 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void)); 348 #endif 349 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); 350 351 void riscv_translate_init(void); 352 int riscv_cpu_signal_handler(int host_signum, void *pinfo, void *puc); 353 void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env, 354 uint32_t exception, uintptr_t pc); 355 356 target_ulong riscv_cpu_get_fflags(CPURISCVState *env); 357 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); 358 359 #define TB_FLAGS_MMU_MASK 3 360 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS 361 362 typedef CPURISCVState CPUArchState; 363 typedef RISCVCPU ArchCPU; 364 #include "exec/cpu-all.h" 365 366 FIELD(TB_FLAGS, VL_EQ_VLMAX, 2, 1) 367 FIELD(TB_FLAGS, LMUL, 3, 2) 368 FIELD(TB_FLAGS, SEW, 5, 3) 369 FIELD(TB_FLAGS, VILL, 8, 1) 370 371 /* 372 * A simplification for VLMAX 373 * = (1 << LMUL) * VLEN / (8 * (1 << SEW)) 374 * = (VLEN << LMUL) / (8 << SEW) 375 * = (VLEN << LMUL) >> (SEW + 3) 376 * = VLEN >> (SEW + 3 - LMUL) 377 */ 378 static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) 379 { 380 uint8_t sew, lmul; 381 382 sew = FIELD_EX64(vtype, VTYPE, VSEW); 383 lmul = FIELD_EX64(vtype, VTYPE, VLMUL); 384 return cpu->cfg.vlen >> (sew + 3 - lmul); 385 } 386 387 static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 388 target_ulong *cs_base, uint32_t *pflags) 389 { 390 uint32_t flags = 0; 391 392 *pc = env->pc; 393 *cs_base = 0; 394 395 if (riscv_has_ext(env, RVV)) { 396 uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype); 397 bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl); 398 flags = FIELD_DP32(flags, TB_FLAGS, VILL, 399 FIELD_EX64(env->vtype, VTYPE, VILL)); 400 flags = FIELD_DP32(flags, TB_FLAGS, SEW, 401 FIELD_EX64(env->vtype, VTYPE, VSEW)); 402 flags = FIELD_DP32(flags, TB_FLAGS, LMUL, 403 FIELD_EX64(env->vtype, VTYPE, VLMUL)); 404 flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); 405 } else { 406 flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1); 407 } 408 409 #ifdef CONFIG_USER_ONLY 410 flags |= TB_FLAGS_MSTATUS_FS; 411 #else 412 flags |= cpu_mmu_index(env, 0); 413 if (riscv_cpu_fp_enabled(env)) { 414 flags |= env->mstatus & MSTATUS_FS; 415 } 416 #endif 417 *pflags = flags; 418 } 419 420 int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, 421 target_ulong new_value, target_ulong write_mask); 422 int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value, 423 target_ulong new_value, target_ulong write_mask); 424 425 static inline void riscv_csr_write(CPURISCVState *env, int csrno, 426 target_ulong val) 427 { 428 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); 429 } 430 431 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) 432 { 433 target_ulong val = 0; 434 riscv_csrrw(env, csrno, &val, 0, 0); 435 return val; 436 } 437 438 typedef int (*riscv_csr_predicate_fn)(CPURISCVState *env, int csrno); 439 typedef int (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, 440 target_ulong *ret_value); 441 typedef int (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, 442 target_ulong new_value); 443 typedef int (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, 444 target_ulong *ret_value, target_ulong new_value, target_ulong write_mask); 445 446 typedef struct { 447 riscv_csr_predicate_fn predicate; 448 riscv_csr_read_fn read; 449 riscv_csr_write_fn write; 450 riscv_csr_op_fn op; 451 } riscv_csr_operations; 452 453 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); 454 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); 455 456 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); 457 458 #endif /* RISCV_CPU_H */ 459