1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef RISCV_CPU_H 21 #define RISCV_CPU_H 22 23 #include "hw/core/cpu.h" 24 #include "hw/registerfields.h" 25 #include "exec/cpu-defs.h" 26 #include "fpu/softfloat-types.h" 27 #include "qom/object.h" 28 #include "qemu/int128.h" 29 #include "cpu_bits.h" 30 31 #define TCG_GUEST_DEFAULT_MO 0 32 33 #define TYPE_RISCV_CPU "riscv-cpu" 34 35 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU 36 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) 37 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU 38 39 #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") 40 #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") 41 #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") 42 #define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128") 43 #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") 44 #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") 45 #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") 46 #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") 47 #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") 48 #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") 49 #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") 50 #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") 51 52 #if defined(TARGET_RISCV32) 53 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 54 #elif defined(TARGET_RISCV64) 55 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 56 #endif 57 58 #define RV(x) ((target_ulong)1 << (x - 'A')) 59 60 #define RVI RV('I') 61 #define RVE RV('E') /* E and I are mutually exclusive */ 62 #define RVM RV('M') 63 #define RVA RV('A') 64 #define RVF RV('F') 65 #define RVD RV('D') 66 #define RVV RV('V') 67 #define RVC RV('C') 68 #define RVS RV('S') 69 #define RVU RV('U') 70 #define RVH RV('H') 71 #define RVJ RV('J') 72 73 /* S extension denotes that Supervisor mode exists, however it is possible 74 to have a core that support S mode but does not have an MMU and there 75 is currently no bit in misa to indicate whether an MMU exists or not 76 so a cpu features bitfield is required, likewise for optional PMP support */ 77 enum { 78 RISCV_FEATURE_MMU, 79 RISCV_FEATURE_PMP, 80 RISCV_FEATURE_EPMP, 81 RISCV_FEATURE_MISA, 82 RISCV_FEATURE_AIA 83 }; 84 85 #define PRIV_VERSION_1_10_0 0x00011000 86 #define PRIV_VERSION_1_11_0 0x00011100 87 88 #define VEXT_VERSION_1_00_0 0x00010000 89 90 enum { 91 TRANSLATE_SUCCESS, 92 TRANSLATE_FAIL, 93 TRANSLATE_PMP_FAIL, 94 TRANSLATE_G_STAGE_FAIL 95 }; 96 97 #define MMU_USER_IDX 3 98 99 #define MAX_RISCV_PMPS (16) 100 101 typedef struct CPURISCVState CPURISCVState; 102 103 #if !defined(CONFIG_USER_ONLY) 104 #include "pmp.h" 105 #endif 106 107 #define RV_VLEN_MAX 1024 108 109 FIELD(VTYPE, VLMUL, 0, 3) 110 FIELD(VTYPE, VSEW, 3, 3) 111 FIELD(VTYPE, VTA, 6, 1) 112 FIELD(VTYPE, VMA, 7, 1) 113 FIELD(VTYPE, VEDIV, 8, 2) 114 FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) 115 116 struct CPURISCVState { 117 target_ulong gpr[32]; 118 target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ 119 uint64_t fpr[32]; /* assume both F and D extensions */ 120 121 /* vector coprocessor state. */ 122 uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); 123 target_ulong vxrm; 124 target_ulong vxsat; 125 target_ulong vl; 126 target_ulong vstart; 127 target_ulong vtype; 128 bool vill; 129 130 target_ulong pc; 131 target_ulong load_res; 132 target_ulong load_val; 133 134 target_ulong frm; 135 136 target_ulong badaddr; 137 uint32_t bins; 138 139 target_ulong guest_phys_fault_addr; 140 141 target_ulong priv_ver; 142 target_ulong bext_ver; 143 target_ulong vext_ver; 144 145 /* RISCVMXL, but uint32_t for vmstate migration */ 146 uint32_t misa_mxl; /* current mxl */ 147 uint32_t misa_mxl_max; /* max mxl for this cpu */ 148 uint32_t misa_ext; /* current extensions */ 149 uint32_t misa_ext_mask; /* max ext for this cpu */ 150 uint32_t xl; /* current xlen */ 151 152 /* 128-bit helpers upper part return value */ 153 target_ulong retxh; 154 155 uint32_t features; 156 157 #ifdef CONFIG_USER_ONLY 158 uint32_t elf_flags; 159 #endif 160 161 #ifndef CONFIG_USER_ONLY 162 target_ulong priv; 163 /* This contains QEMU specific information about the virt state. */ 164 target_ulong virt; 165 target_ulong geilen; 166 target_ulong resetvec; 167 168 target_ulong mhartid; 169 /* 170 * For RV32 this is 32-bit mstatus and 32-bit mstatush. 171 * For RV64 this is a 64-bit mstatus. 172 */ 173 uint64_t mstatus; 174 175 uint64_t mip; 176 177 uint64_t miclaim; 178 179 uint64_t mie; 180 uint64_t mideleg; 181 182 target_ulong satp; /* since: priv-1.10.0 */ 183 target_ulong stval; 184 target_ulong medeleg; 185 186 target_ulong stvec; 187 target_ulong sepc; 188 target_ulong scause; 189 190 target_ulong mtvec; 191 target_ulong mepc; 192 target_ulong mcause; 193 target_ulong mtval; /* since: priv-1.10.0 */ 194 195 /* Machine and Supervisor interrupt priorities */ 196 uint8_t miprio[64]; 197 uint8_t siprio[64]; 198 199 /* Hypervisor CSRs */ 200 target_ulong hstatus; 201 target_ulong hedeleg; 202 uint64_t hideleg; 203 target_ulong hcounteren; 204 target_ulong htval; 205 target_ulong htinst; 206 target_ulong hgatp; 207 target_ulong hgeie; 208 target_ulong hgeip; 209 uint64_t htimedelta; 210 211 /* Hypervisor controlled virtual interrupt priorities */ 212 target_ulong hvictl; 213 uint8_t hviprio[64]; 214 215 /* Upper 64-bits of 128-bit CSRs */ 216 uint64_t mscratchh; 217 uint64_t sscratchh; 218 219 /* Virtual CSRs */ 220 /* 221 * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. 222 * For RV64 this is a 64-bit vsstatus. 223 */ 224 uint64_t vsstatus; 225 target_ulong vstvec; 226 target_ulong vsscratch; 227 target_ulong vsepc; 228 target_ulong vscause; 229 target_ulong vstval; 230 target_ulong vsatp; 231 232 target_ulong mtval2; 233 target_ulong mtinst; 234 235 /* HS Backup CSRs */ 236 target_ulong stvec_hs; 237 target_ulong sscratch_hs; 238 target_ulong sepc_hs; 239 target_ulong scause_hs; 240 target_ulong stval_hs; 241 target_ulong satp_hs; 242 uint64_t mstatus_hs; 243 244 /* Signals whether the current exception occurred with two-stage address 245 translation active. */ 246 bool two_stage_lookup; 247 248 target_ulong scounteren; 249 target_ulong mcounteren; 250 251 target_ulong sscratch; 252 target_ulong mscratch; 253 254 /* temporary htif regs */ 255 uint64_t mfromhost; 256 uint64_t mtohost; 257 uint64_t timecmp; 258 259 /* physical memory protection */ 260 pmp_table_t pmp_state; 261 target_ulong mseccfg; 262 263 /* machine specific rdtime callback */ 264 uint64_t (*rdtime_fn)(uint32_t); 265 uint32_t rdtime_fn_arg; 266 267 /* machine specific AIA ireg read-modify-write callback */ 268 #define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \ 269 ((((__xlen) & 0xff) << 24) | \ 270 (((__vgein) & 0x3f) << 20) | \ 271 (((__virt) & 0x1) << 18) | \ 272 (((__priv) & 0x3) << 16) | \ 273 (__isel & 0xffff)) 274 #define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff) 275 #define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3) 276 #define AIA_IREG_VIRT(__ireg) (((__ireg) >> 18) & 0x1) 277 #define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 20) & 0x3f) 278 #define AIA_IREG_XLEN(__ireg) (((__ireg) >> 24) & 0xff) 279 int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg, 280 target_ulong *val, target_ulong new_val, target_ulong write_mask); 281 void *aia_ireg_rmw_fn_arg[4]; 282 283 /* True if in debugger mode. */ 284 bool debugger; 285 286 /* 287 * CSRs for PointerMasking extension 288 */ 289 target_ulong mmte; 290 target_ulong mpmmask; 291 target_ulong mpmbase; 292 target_ulong spmmask; 293 target_ulong spmbase; 294 target_ulong upmmask; 295 target_ulong upmbase; 296 #endif 297 target_ulong cur_pmmask; 298 target_ulong cur_pmbase; 299 300 float_status fp_status; 301 302 /* Fields from here on are preserved across CPU reset. */ 303 QEMUTimer *timer; /* Internal timer */ 304 305 hwaddr kernel_addr; 306 hwaddr fdt_addr; 307 308 /* kvm timer */ 309 bool kvm_timer_dirty; 310 uint64_t kvm_timer_time; 311 uint64_t kvm_timer_compare; 312 uint64_t kvm_timer_state; 313 uint64_t kvm_timer_frequency; 314 }; 315 316 OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass, 317 RISCV_CPU) 318 319 /** 320 * RISCVCPUClass: 321 * @parent_realize: The parent class' realize handler. 322 * @parent_reset: The parent class' reset handler. 323 * 324 * A RISCV CPU model. 325 */ 326 struct RISCVCPUClass { 327 /*< private >*/ 328 CPUClass parent_class; 329 /*< public >*/ 330 DeviceRealize parent_realize; 331 DeviceReset parent_reset; 332 }; 333 334 struct RISCVCPUConfig { 335 bool ext_i; 336 bool ext_e; 337 bool ext_g; 338 bool ext_m; 339 bool ext_a; 340 bool ext_f; 341 bool ext_d; 342 bool ext_c; 343 bool ext_s; 344 bool ext_u; 345 bool ext_h; 346 bool ext_j; 347 bool ext_v; 348 bool ext_zba; 349 bool ext_zbb; 350 bool ext_zbc; 351 bool ext_zbs; 352 bool ext_counters; 353 bool ext_ifencei; 354 bool ext_icsr; 355 bool ext_zfh; 356 bool ext_zfhmin; 357 bool ext_zve32f; 358 bool ext_zve64f; 359 360 /* Vendor-specific custom extensions */ 361 bool ext_XVentanaCondOps; 362 363 char *priv_spec; 364 char *user_spec; 365 char *bext_spec; 366 char *vext_spec; 367 uint16_t vlen; 368 uint16_t elen; 369 bool mmu; 370 bool pmp; 371 bool epmp; 372 uint64_t resetvec; 373 }; 374 375 typedef struct RISCVCPUConfig RISCVCPUConfig; 376 377 /** 378 * RISCVCPU: 379 * @env: #CPURISCVState 380 * 381 * A RISCV CPU. 382 */ 383 struct RISCVCPU { 384 /*< private >*/ 385 CPUState parent_obj; 386 /*< public >*/ 387 CPUNegativeOffsetState neg; 388 CPURISCVState env; 389 390 char *dyn_csr_xml; 391 char *dyn_vreg_xml; 392 393 /* Configuration Settings */ 394 RISCVCPUConfig cfg; 395 }; 396 397 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) 398 { 399 return (env->misa_ext & ext) != 0; 400 } 401 402 static inline bool riscv_feature(CPURISCVState *env, int feature) 403 { 404 return env->features & (1ULL << feature); 405 } 406 407 static inline void riscv_set_feature(CPURISCVState *env, int feature) 408 { 409 env->features |= (1ULL << feature); 410 } 411 412 #include "cpu_user.h" 413 414 extern const char * const riscv_int_regnames[]; 415 extern const char * const riscv_int_regnamesh[]; 416 extern const char * const riscv_fpr_regnames[]; 417 418 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); 419 void riscv_cpu_do_interrupt(CPUState *cpu); 420 int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 421 int cpuid, void *opaque); 422 int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 423 int cpuid, void *opaque); 424 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 425 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 426 int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero); 427 uint8_t riscv_cpu_default_priority(int irq); 428 int riscv_cpu_mirq_pending(CPURISCVState *env); 429 int riscv_cpu_sirq_pending(CPURISCVState *env); 430 int riscv_cpu_vsirq_pending(CPURISCVState *env); 431 bool riscv_cpu_fp_enabled(CPURISCVState *env); 432 target_ulong riscv_cpu_get_geilen(CPURISCVState *env); 433 void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); 434 bool riscv_cpu_vector_enabled(CPURISCVState *env); 435 bool riscv_cpu_virt_enabled(CPURISCVState *env); 436 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); 437 bool riscv_cpu_two_stage_lookup(int mmu_idx); 438 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); 439 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 440 void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 441 MMUAccessType access_type, int mmu_idx, 442 uintptr_t retaddr) QEMU_NORETURN; 443 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 444 MMUAccessType access_type, int mmu_idx, 445 bool probe, uintptr_t retaddr); 446 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 447 vaddr addr, unsigned size, 448 MMUAccessType access_type, 449 int mmu_idx, MemTxAttrs attrs, 450 MemTxResult response, uintptr_t retaddr); 451 char *riscv_isa_string(RISCVCPU *cpu); 452 void riscv_cpu_list(void); 453 454 #define cpu_list riscv_cpu_list 455 #define cpu_mmu_index riscv_cpu_mmu_index 456 457 #ifndef CONFIG_USER_ONLY 458 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); 459 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); 460 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); 461 uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value); 462 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ 463 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t), 464 uint32_t arg); 465 void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, 466 int (*rmw_fn)(void *arg, 467 target_ulong reg, 468 target_ulong *val, 469 target_ulong new_val, 470 target_ulong write_mask), 471 void *rmw_fn_arg); 472 #endif 473 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); 474 475 void riscv_translate_init(void); 476 void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env, 477 uint32_t exception, uintptr_t pc); 478 479 target_ulong riscv_cpu_get_fflags(CPURISCVState *env); 480 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); 481 482 #define TB_FLAGS_PRIV_MMU_MASK 3 483 #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2) 484 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS 485 #define TB_FLAGS_MSTATUS_VS MSTATUS_VS 486 487 typedef CPURISCVState CPUArchState; 488 typedef RISCVCPU ArchCPU; 489 #include "exec/cpu-all.h" 490 491 FIELD(TB_FLAGS, MEM_IDX, 0, 3) 492 FIELD(TB_FLAGS, LMUL, 3, 3) 493 FIELD(TB_FLAGS, SEW, 6, 3) 494 /* Skip MSTATUS_VS (0x600) bits */ 495 FIELD(TB_FLAGS, VL_EQ_VLMAX, 11, 1) 496 FIELD(TB_FLAGS, VILL, 12, 1) 497 /* Skip MSTATUS_FS (0x6000) bits */ 498 /* Is a Hypervisor instruction load/store allowed? */ 499 FIELD(TB_FLAGS, HLSX, 15, 1) 500 FIELD(TB_FLAGS, MSTATUS_HS_FS, 16, 2) 501 FIELD(TB_FLAGS, MSTATUS_HS_VS, 18, 2) 502 /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ 503 FIELD(TB_FLAGS, XL, 20, 2) 504 /* If PointerMasking should be applied */ 505 FIELD(TB_FLAGS, PM_MASK_ENABLED, 22, 1) 506 FIELD(TB_FLAGS, PM_BASE_ENABLED, 23, 1) 507 508 #ifdef TARGET_RISCV32 509 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) 510 #else 511 static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) 512 { 513 return env->misa_mxl; 514 } 515 #endif 516 #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env))) 517 518 #if defined(TARGET_RISCV32) 519 #define cpu_recompute_xl(env) ((void)(env), MXL_RV32) 520 #else 521 static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) 522 { 523 RISCVMXL xl = env->misa_mxl; 524 #if !defined(CONFIG_USER_ONLY) 525 /* 526 * When emulating a 32-bit-only cpu, use RV32. 527 * When emulating a 64-bit cpu, and MXL has been reduced to RV32, 528 * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened 529 * back to RV64 for lower privs. 530 */ 531 if (xl != MXL_RV32) { 532 switch (env->priv) { 533 case PRV_M: 534 break; 535 case PRV_U: 536 xl = get_field(env->mstatus, MSTATUS64_UXL); 537 break; 538 default: /* PRV_S | PRV_H */ 539 xl = get_field(env->mstatus, MSTATUS64_SXL); 540 break; 541 } 542 } 543 #endif 544 return xl; 545 } 546 #endif 547 548 static inline int riscv_cpu_xlen(CPURISCVState *env) 549 { 550 return 16 << env->xl; 551 } 552 553 /* 554 * Encode LMUL to lmul as follows: 555 * LMUL vlmul lmul 556 * 1 000 0 557 * 2 001 1 558 * 4 010 2 559 * 8 011 3 560 * - 100 - 561 * 1/8 101 -3 562 * 1/4 110 -2 563 * 1/2 111 -1 564 * 565 * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul) 566 * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8 567 * => VLMAX = vlen >> (1 + 3 - (-3)) 568 * = 256 >> 7 569 * = 2 570 */ 571 static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) 572 { 573 uint8_t sew = FIELD_EX64(vtype, VTYPE, VSEW); 574 int8_t lmul = sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3); 575 return cpu->cfg.vlen >> (sew + 3 - lmul); 576 } 577 578 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 579 target_ulong *cs_base, uint32_t *pflags); 580 581 void riscv_cpu_update_mask(CPURISCVState *env); 582 583 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, 584 target_ulong *ret_value, 585 target_ulong new_value, target_ulong write_mask); 586 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, 587 target_ulong *ret_value, 588 target_ulong new_value, 589 target_ulong write_mask); 590 591 static inline void riscv_csr_write(CPURISCVState *env, int csrno, 592 target_ulong val) 593 { 594 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); 595 } 596 597 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) 598 { 599 target_ulong val = 0; 600 riscv_csrrw(env, csrno, &val, 0, 0); 601 return val; 602 } 603 604 typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, 605 int csrno); 606 typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, 607 target_ulong *ret_value); 608 typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, 609 target_ulong new_value); 610 typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, 611 target_ulong *ret_value, 612 target_ulong new_value, 613 target_ulong write_mask); 614 615 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, 616 Int128 *ret_value, 617 Int128 new_value, Int128 write_mask); 618 619 typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno, 620 Int128 *ret_value); 621 typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int csrno, 622 Int128 new_value); 623 624 typedef struct { 625 const char *name; 626 riscv_csr_predicate_fn predicate; 627 riscv_csr_read_fn read; 628 riscv_csr_write_fn write; 629 riscv_csr_op_fn op; 630 riscv_csr_read128_fn read128; 631 riscv_csr_write128_fn write128; 632 } riscv_csr_operations; 633 634 /* CSR function table constants */ 635 enum { 636 CSR_TABLE_SIZE = 0x1000 637 }; 638 639 /* CSR function table */ 640 extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; 641 642 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); 643 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); 644 645 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); 646 647 #endif /* RISCV_CPU_H */ 648